Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify it | |
3 | * under the terms of the GNU General Public License as published by the | |
4 | * Free Software Foundation; either version 2 of the License, or (at your | |
5 | * option) any later version. | |
6 | * | |
7 | * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) | |
8 | */ | |
1da177e4 LT |
9 | #include <linux/kernel.h> |
10 | #include <linux/mm.h> | |
11 | #include <linux/bootmem.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/pci.h> | |
15 | ||
16 | /* | |
17 | * Indicate whether we respect the PCI setup left by the firmware. | |
18 | * | |
19 | * Make this long-lived so that we know when shutting down | |
20 | * whether we probed only or not. | |
21 | */ | |
22 | int pci_probe_only; | |
23 | ||
24 | #define PCI_ASSIGN_ALL_BUSSES 1 | |
25 | ||
26 | unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; | |
27 | ||
28 | /* | |
29 | * The PCI controller list. | |
30 | */ | |
31 | ||
32 | struct pci_controller *hose_head, **hose_tail = &hose_head; | |
33 | struct pci_controller *pci_isa_hose; | |
34 | ||
35 | unsigned long PCIBIOS_MIN_IO = 0x0000; | |
36 | unsigned long PCIBIOS_MIN_MEM = 0; | |
37 | ||
38 | /* | |
39 | * We need to avoid collisions with `mirrored' VGA ports | |
40 | * and other strange ISA hardware, so we always want the | |
41 | * addresses to be allocated in the 0x000-0x0ff region | |
42 | * modulo 0x400. | |
43 | * | |
44 | * Why? Because some silly external IO cards only decode | |
45 | * the low 10 bits of the IO address. The 0x00-0xff region | |
46 | * is reserved for motherboard devices that decode all 16 | |
47 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
48 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
49 | * which might have be mirrored at 0x0100-0x03ff.. | |
50 | */ | |
51 | void | |
52 | pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 53 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
54 | { |
55 | struct pci_dev *dev = data; | |
56 | struct pci_controller *hose = dev->sysdata; | |
e31dd6e4 | 57 | resource_size_t start = res->start; |
1da177e4 LT |
58 | |
59 | if (res->flags & IORESOURCE_IO) { | |
60 | /* Make sure we start at our min on all hoses */ | |
61 | if (start < PCIBIOS_MIN_IO + hose->io_resource->start) | |
62 | start = PCIBIOS_MIN_IO + hose->io_resource->start; | |
63 | ||
64 | /* | |
65 | * Put everything into 0x00-0xff region modulo 0x400 | |
66 | */ | |
67 | if (start & 0x300) | |
68 | start = (start + 0x3ff) & ~0x3ff; | |
69 | } else if (res->flags & IORESOURCE_MEM) { | |
70 | /* Make sure we start at our min on all hoses */ | |
71 | if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) | |
72 | start = PCIBIOS_MIN_MEM + hose->mem_resource->start; | |
73 | } | |
74 | ||
75 | res->start = start; | |
76 | } | |
77 | ||
1da177e4 LT |
78 | void __init register_pci_controller(struct pci_controller *hose) |
79 | { | |
80 | *hose_tail = hose; | |
81 | hose_tail = &hose->next; | |
140c1729 RB |
82 | |
83 | /* | |
84 | * Do not panic here but later - this might hapen before console init. | |
85 | */ | |
86 | if (!hose->io_map_base) { | |
87 | printk(KERN_WARNING | |
88 | "registering PCI controller with io_map_base unset\n"); | |
89 | } | |
1da177e4 LT |
90 | } |
91 | ||
92 | /* Most MIPS systems have straight-forward swizzling needs. */ | |
93 | ||
94 | static inline u8 bridge_swizzle(u8 pin, u8 slot) | |
95 | { | |
96 | return (((pin - 1) + slot) % 4) + 1; | |
97 | } | |
98 | ||
99 | static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp) | |
100 | { | |
101 | u8 pin = *pinp; | |
102 | ||
103 | while (dev->bus->parent) { | |
104 | pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); | |
105 | /* Move up the chain of bridges. */ | |
106 | dev = dev->bus->self; | |
107 | } | |
108 | *pinp = pin; | |
109 | ||
110 | /* The slot is the slot of the last bridge. */ | |
111 | return PCI_SLOT(dev->devfn); | |
112 | } | |
113 | ||
114 | static int __init pcibios_init(void) | |
115 | { | |
116 | struct pci_controller *hose; | |
117 | struct pci_bus *bus; | |
118 | int next_busno; | |
119 | int need_domain_info = 0; | |
120 | ||
121 | /* Scan all of the recorded PCI controllers. */ | |
122 | for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { | |
123 | ||
124 | if (request_resource(&iomem_resource, hose->mem_resource) < 0) | |
125 | goto out; | |
126 | if (request_resource(&ioport_resource, hose->io_resource) < 0) | |
127 | goto out_free_mem_resource; | |
128 | ||
129 | if (!hose->iommu) | |
130 | PCI_DMA_BUS_IS_PHYS = 1; | |
131 | ||
8a1417de AI |
132 | if (hose->get_busno && pci_probe_only) |
133 | next_busno = (*hose->get_busno)(); | |
134 | ||
1da177e4 LT |
135 | bus = pci_scan_bus(next_busno, hose->pci_ops, hose); |
136 | hose->bus = bus; | |
137 | hose->need_domain_info = need_domain_info; | |
8a1417de AI |
138 | if (bus) { |
139 | next_busno = bus->subordinate + 1; | |
140 | /* Don't allow 8-bit bus number overflow inside the hose - | |
141 | reserve some space for bridges. */ | |
142 | if (next_busno > 224) { | |
143 | next_busno = 0; | |
144 | need_domain_info = 1; | |
145 | } | |
1da177e4 LT |
146 | } |
147 | continue; | |
148 | ||
149 | out_free_mem_resource: | |
150 | release_resource(hose->mem_resource); | |
151 | ||
152 | out: | |
153 | printk(KERN_WARNING | |
154 | "Skipping PCI bus scan due to resource conflict\n"); | |
155 | } | |
156 | ||
157 | if (!pci_probe_only) | |
158 | pci_assign_unassigned_resources(); | |
159 | pci_fixup_irqs(common_swizzle, pcibios_map_irq); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | subsys_initcall(pcibios_init); | |
165 | ||
166 | static int pcibios_enable_resources(struct pci_dev *dev, int mask) | |
167 | { | |
168 | u16 cmd, old_cmd; | |
169 | int idx; | |
170 | struct resource *r; | |
171 | ||
172 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
173 | old_cmd = cmd; | |
e5de3b46 | 174 | for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { |
1da177e4 LT |
175 | /* Only set up the requested stuff */ |
176 | if (!(mask & (1<<idx))) | |
177 | continue; | |
178 | ||
179 | r = &dev->resource[idx]; | |
180 | if (!r->start && r->end) { | |
181 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); | |
182 | return -EINVAL; | |
183 | } | |
184 | if (r->flags & IORESOURCE_IO) | |
185 | cmd |= PCI_COMMAND_IO; | |
186 | if (r->flags & IORESOURCE_MEM) | |
187 | cmd |= PCI_COMMAND_MEMORY; | |
188 | } | |
189 | if (dev->resource[PCI_ROM_RESOURCE].start) | |
190 | cmd |= PCI_COMMAND_MEMORY; | |
191 | if (cmd != old_cmd) { | |
192 | printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); | |
193 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
194 | } | |
195 | return 0; | |
196 | } | |
197 | ||
198 | /* | |
199 | * If we set up a device for bus mastering, we need to check the latency | |
200 | * timer as certain crappy BIOSes forget to set it properly. | |
201 | */ | |
202 | unsigned int pcibios_max_latency = 255; | |
203 | ||
204 | void pcibios_set_master(struct pci_dev *dev) | |
205 | { | |
206 | u8 lat; | |
207 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); | |
208 | if (lat < 16) | |
209 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
210 | else if (lat > pcibios_max_latency) | |
211 | lat = pcibios_max_latency; | |
212 | else | |
213 | return; | |
214 | printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", | |
215 | pci_name(dev), lat); | |
216 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); | |
217 | } | |
218 | ||
219 | unsigned int pcibios_assign_all_busses(void) | |
220 | { | |
221 | return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; | |
222 | } | |
223 | ||
224 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
225 | { | |
226 | int err; | |
227 | ||
228 | if ((err = pcibios_enable_resources(dev, mask)) < 0) | |
229 | return err; | |
230 | ||
231 | return pcibios_plat_dev_init(dev); | |
232 | } | |
233 | ||
44197088 | 234 | static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, |
1da177e4 LT |
235 | struct pci_bus *bus) |
236 | { | |
237 | /* Update device resources. */ | |
238 | struct pci_controller *hose = (struct pci_controller *)bus->sysdata; | |
239 | unsigned long offset = 0; | |
240 | int i; | |
241 | ||
242 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
243 | if (!dev->resource[i].start) | |
244 | continue; | |
245 | if (dev->resource[i].flags & IORESOURCE_IO) | |
246 | offset = hose->io_offset; | |
247 | else if (dev->resource[i].flags & IORESOURCE_MEM) | |
248 | offset = hose->mem_offset; | |
249 | ||
250 | dev->resource[i].start += offset; | |
251 | dev->resource[i].end += offset; | |
252 | } | |
253 | } | |
254 | ||
255 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) | |
256 | { | |
257 | /* Propagate hose info into the subordinate devices. */ | |
258 | ||
259 | struct pci_controller *hose = bus->sysdata; | |
260 | struct list_head *ln; | |
261 | struct pci_dev *dev = bus->self; | |
262 | ||
263 | if (!dev) { | |
264 | bus->resource[0] = hose->io_resource; | |
265 | bus->resource[1] = hose->mem_resource; | |
266 | } else if (pci_probe_only && | |
267 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
268 | pci_read_bridge_bases(bus); | |
269 | pcibios_fixup_device_resources(dev, bus); | |
42a3b4f2 | 270 | } |
1da177e4 LT |
271 | |
272 | for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { | |
273 | struct pci_dev *dev = pci_dev_b(ln); | |
274 | ||
275 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
276 | pcibios_fixup_device_resources(dev, bus); | |
277 | } | |
278 | } | |
279 | ||
280 | void __init | |
281 | pcibios_update_irq(struct pci_dev *dev, int irq) | |
282 | { | |
283 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
284 | } | |
285 | ||
286 | void __devinit | |
287 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
288 | struct resource *res) | |
289 | { | |
290 | struct pci_controller *hose = (struct pci_controller *)dev->sysdata; | |
291 | unsigned long offset = 0; | |
292 | ||
293 | if (res->flags & IORESOURCE_IO) | |
294 | offset = hose->io_offset; | |
295 | else if (res->flags & IORESOURCE_MEM) | |
296 | offset = hose->mem_offset; | |
297 | ||
298 | region->start = res->start - offset; | |
299 | region->end = res->end - offset; | |
300 | } | |
301 | ||
e63ea56f YY |
302 | void __devinit |
303 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
304 | struct pci_bus_region *region) | |
305 | { | |
306 | struct pci_controller *hose = (struct pci_controller *)dev->sysdata; | |
307 | unsigned long offset = 0; | |
308 | ||
309 | if (res->flags & IORESOURCE_IO) | |
310 | offset = hose->io_offset; | |
311 | else if (res->flags & IORESOURCE_MEM) | |
312 | offset = hose->mem_offset; | |
313 | ||
314 | res->start = region->start + offset; | |
315 | res->end = region->end + offset; | |
316 | } | |
317 | ||
1da177e4 LT |
318 | #ifdef CONFIG_HOTPLUG |
319 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
e63ea56f | 320 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
321 | EXPORT_SYMBOL(PCIBIOS_MIN_IO); |
322 | EXPORT_SYMBOL(PCIBIOS_MIN_MEM); | |
323 | #endif | |
324 | ||
325 | char *pcibios_setup(char *str) | |
326 | { | |
327 | return str; | |
328 | } |