[deliverable/linux.git] / arch / mips / sgi-ip27 / ip27-irq.c

/*
 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
 *
 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 1999 - 2001 Kanoj Sarcar
 */

#undef DEBUG

#include <linux/config.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/smp_lock.h>
#include <linux/kernel.h>
#include <linux/kernel_stat.h>
#include <linux/delay.h>
#include <linux/bitops.h>

#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/pci/bridge.h>
#include <asm/sn/addrs.h>
#include <asm/sn/agent.h>
#include <asm/sn/arch.h>
#include <asm/sn/hub.h>
#include <asm/sn/intr.h>

/*
 * Linux has a controller-independent x86 interrupt architecture.
 * every controller has a 'controller-template', that is used
 * by the main code to do the right thing. Each driver-visible
 * interrupt source is transparently wired to the apropriate
 * controller. Thus drivers need not be aware of the
 * interrupt-controller.
 *
 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
 * (IO-APICs assumed to be messaging to Pentium local-APICs)
 *
 * the code is designed to be easily extended with new/different
 * interrupt controllers, without having to do assembly magic.
 */

extern asmlinkage void ip27_irq(void);

extern struct bridge_controller *irq_to_bridge[];
extern int irq_to_slot[];

/*
 * use these macros to get the encoded nasid and widget id
 * from the irq value
 */
#define IRQ_TO_BRIDGE(i)		irq_to_bridge[(i)]
#define	SLOT_FROM_PCI_IRQ(i)		irq_to_slot[i]

static inline int alloc_level(int cpu, int irq)
{
	struct hub_data *hub = hub_data(cpu_to_node(cpu));
	struct slice_data *si = cpu_data[cpu].data;
	int level;

	level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
	if (level >= LEVELS_PER_SLICE)
		panic("Cpu %d flooded with devices\n", cpu);

	__set_bit(level, hub->irq_alloc_mask);
	si->level_to_irq[level] = irq;

	return level;
}

static inline int find_level(cpuid_t *cpunum, int irq)
{
	int cpu, i;

	for_each_online_cpu(cpu) {
		struct slice_data *si = cpu_data[cpu].data;

		for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
			if (si->level_to_irq[i] == irq) {
				*cpunum = cpu;

				return i;
			}
	}

	panic("Could not identify cpu/level for irq %d\n", irq);
}

/*
 * Find first bit set
 */
static int ms1bit(unsigned long x)
{
	int b = 0, s;

	s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s;
	s =  8; if (x >>  8 == 0) s = 0; b += s; x >>= s;
	s =  4; if (x >>  4 == 0) s = 0; b += s; x >>= s;
	s =  2; if (x >>  2 == 0) s = 0; b += s; x >>= s;
	s =  1; if (x >>  1 == 0) s = 0; b += s;

	return b;
}

/*
 * This code is unnecessarily complex, because we do SA_INTERRUPT
 * intr enabling. Basically, once we grab the set of intrs we need
 * to service, we must mask _all_ these interrupts; firstly, to make
 * sure the same intr does not intr again, causing recursion that
 * can lead to stack overflow. Secondly, we can not just mask the
 * one intr we are do_IRQing, because the non-masked intrs in the
 * first set might intr again, causing multiple servicings of the
 * same intr. This effect is mostly seen for intercpu intrs.
 * Kanoj 05.13.00
 */

static void ip27_do_irq_mask0(struct pt_regs *regs)
{
	int irq, swlevel;
	hubreg_t pend0, mask0;
	cpuid_t cpu = smp_processor_id();
	int pi_int_mask0 =
		(cputoslice(cpu) == 0) ?  PI_INT_MASK0_A : PI_INT_MASK0_B;

	/* copied from Irix intpend0() */
	pend0 = LOCAL_HUB_L(PI_INT_PEND0);
	mask0 = LOCAL_HUB_L(pi_int_mask0);

	pend0 &= mask0;		/* Pick intrs we should look at */
	if (!pend0)
		return;

	swlevel = ms1bit(pend0);
#ifdef CONFIG_SMP
	if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
		LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
	} else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
		LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
	} else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
		LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
		smp_call_function_interrupt();
	} else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
		LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
		smp_call_function_interrupt();
	} else
#endif
	{
		/* "map" swlevel to irq */
		struct slice_data *si = cpu_data[cpu].data;

		irq = si->level_to_irq[swlevel];
		do_IRQ(irq, regs);
	}

	LOCAL_HUB_L(PI_INT_PEND0);
}

static void ip27_do_irq_mask1(struct pt_regs *regs)
{
	int irq, swlevel;
	hubreg_t pend1, mask1;
	cpuid_t cpu = smp_processor_id();
	int pi_int_mask1 = (cputoslice(cpu) == 0) ?  PI_INT_MASK1_A : PI_INT_MASK1_B;
	struct slice_data *si = cpu_data[cpu].data;

	/* copied from Irix intpend0() */
	pend1 = LOCAL_HUB_L(PI_INT_PEND1);
	mask1 = LOCAL_HUB_L(pi_int_mask1);

	pend1 &= mask1;		/* Pick intrs we should look at */
	if (!pend1)
		return;

	swlevel = ms1bit(pend1);
	/* "map" swlevel to irq */
	irq = si->level_to_irq[swlevel];
	LOCAL_HUB_CLR_INTR(swlevel);
	do_IRQ(irq, regs);

	LOCAL_HUB_L(PI_INT_PEND1);
}

static void ip27_prof_timer(struct pt_regs *regs)
{
	panic("CPU %d got a profiling interrupt", smp_processor_id());
}

static void ip27_hub_error(struct pt_regs *regs)
{
	panic("CPU %d got a hub error interrupt", smp_processor_id());
}

static int intr_connect_level(int cpu, int bit)
{
	nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	struct slice_data *si = cpu_data[cpu].data;
	unsigned long flags;

	set_bit(bit, si->irq_enable_mask);

	local_irq_save(flags);
	if (!cputoslice(cpu)) {
		REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
		REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
	} else {
		REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
		REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
	}
	local_irq_restore(flags);

	return 0;
}

static int intr_disconnect_level(int cpu, int bit)
{
	nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	struct slice_data *si = cpu_data[cpu].data;

	clear_bit(bit, si->irq_enable_mask);

	if (!cputoslice(cpu)) {
		REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
		REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
	} else {
		REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
		REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
	}

	return 0;
}

/* Startup one of the (PCI ...) IRQs routes over a bridge.  */
static unsigned int startup_bridge_irq(unsigned int irq)
{
	struct bridge_controller *bc;
	bridgereg_t device;
	bridge_t *bridge;
	int pin, swlevel;
	cpuid_t cpu;

	pin = SLOT_FROM_PCI_IRQ(irq);
	bc = IRQ_TO_BRIDGE(irq);
	bridge = bc->base;

	pr_debug("bridge_startup(): irq= 0x%x  pin=%d\n", irq, pin);
	/*
	 * "map" irq to a swlevel greater than 6 since the first 6 bits
	 * of INT_PEND0 are taken
	 */
	swlevel = find_level(&cpu, irq);
	bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
	bridge->b_int_enable |= (1 << pin);
	bridge->b_int_enable |= 0x7ffffe00;	/* more stuff in int_enable */

	/*
	 * Enable sending of an interrupt clear packt to the hub on a high to
	 * low transition of the interrupt pin.
	 *
	 * IRIX sets additional bits in the address which are documented as
	 * reserved in the bridge docs.
	 */
	bridge->b_int_mode |= (1UL << pin);

	/*
	 * We assume the bridge to have a 1:1 mapping between devices
	 * (slots) and intr pins.
	 */
	device = bridge->b_int_device;
	device &= ~(7 << (pin*3));
	device |= (pin << (pin*3));
	bridge->b_int_device = device;

        bridge->b_wid_tflush;

        return 0;       /* Never anything pending.  */
}

/* Shutdown one of the (PCI ...) IRQs routes over a bridge.  */
static void shutdown_bridge_irq(unsigned int irq)
{
	struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
	struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu));
	bridge_t *bridge = bc->base;
	struct slice_data *si = cpu_data[bc->irq_cpu].data;
	int pin, swlevel;
	cpuid_t cpu;

	pr_debug("bridge_shutdown: irq 0x%x\n", irq);
	pin = SLOT_FROM_PCI_IRQ(irq);

	/*
	 * map irq to a swlevel greater than 6 since the first 6 bits
	 * of INT_PEND0 are taken
	 */
	swlevel = find_level(&cpu, irq);
	intr_disconnect_level(cpu, swlevel);

	__clear_bit(swlevel, hub->irq_alloc_mask);
	si->level_to_irq[swlevel] = -1;

	bridge->b_int_enable &= ~(1 << pin);
	bridge->b_wid_tflush;
}

static inline void enable_bridge_irq(unsigned int irq)
{
	cpuid_t cpu;
	int swlevel;

	swlevel = find_level(&cpu, irq);	/* Criminal offence */
	intr_connect_level(cpu, swlevel);
}

static inline void disable_bridge_irq(unsigned int irq)
{
	cpuid_t cpu;
	int swlevel;

	swlevel = find_level(&cpu, irq);	/* Criminal offence */
	intr_disconnect_level(cpu, swlevel);
}

static void mask_and_ack_bridge_irq(unsigned int irq)
{
	disable_bridge_irq(irq);
}

static void end_bridge_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
	    irq_desc[irq].action)
		enable_bridge_irq(irq);
}

static struct hw_interrupt_type bridge_irq_type = {
	.typename	= "bridge",
	.startup	= startup_bridge_irq,
	.shutdown	= shutdown_bridge_irq,
	.enable		= enable_bridge_irq,
	.disable	= disable_bridge_irq,
	.ack		= mask_and_ack_bridge_irq,
	.end		= end_bridge_irq,
};

static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];

static int allocate_irqno(void)
{
	int irq;

again:
	irq = find_first_zero_bit(irq_map, NR_IRQS);

	if (irq >= NR_IRQS)
		return -ENOSPC;

	if (test_and_set_bit(irq, irq_map))
		goto again;

	return irq;
}

void free_irqno(unsigned int irq)
{
	clear_bit(irq, irq_map);
}

void __devinit register_bridge_irq(unsigned int irq)
{
	irq_desc[irq].status	= IRQ_DISABLED;
	irq_desc[irq].action	= 0;
	irq_desc[irq].depth	= 1;
	irq_desc[irq].handler	= &bridge_irq_type;
}

int __devinit request_bridge_irq(struct bridge_controller *bc)
{
	int irq = allocate_irqno();
	int swlevel, cpu;
	nasid_t nasid;

	if (irq < 0)
		return irq;

	/*
	 * "map" irq to a swlevel greater than 6 since the first 6 bits
	 * of INT_PEND0 are taken
	 */
	cpu = bc->irq_cpu;
	swlevel = alloc_level(cpu, irq);
	if (unlikely(swlevel < 0)) {
		free_irqno(irq);

		return -EAGAIN;
	}

	/* Make sure it's not already pending when we connect it. */
	nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	REMOTE_HUB_CLR_INTR(nasid, swlevel);

	intr_connect_level(cpu, swlevel);

	register_bridge_irq(irq);

	return irq;
}

extern void ip27_rt_timer_interrupt(struct pt_regs *regs);

asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
	unsigned long pending = read_c0_cause() & read_c0_status();

	if (pending & CAUSEF_IP4)
		ip27_rt_timer_interrupt(regs);
	else if (pending & CAUSEF_IP2)	/* PI_INT_PEND_0 or CC_PEND_{A|B} */
		ip27_do_irq_mask0(regs);
	else if (pending & CAUSEF_IP3)	/* PI_INT_PEND_1 */
		ip27_do_irq_mask1(regs);
	else if (pending & CAUSEF_IP5)
		ip27_prof_timer(regs);
	else if (pending & CAUSEF_IP6)
		ip27_hub_error(regs);
}

void __init arch_init_irq(void)
{
}

void install_ipi(void)
{
	int slice = LOCAL_HUB_L(PI_CPU_NUM);
	int cpu = smp_processor_id();
	struct slice_data *si = cpu_data[cpu].data;
	struct hub_data *hub = hub_data(cpu_to_node(cpu));
	int resched, call;

	resched = CPU_RESCHED_A_IRQ + slice;
	__set_bit(resched, hub->irq_alloc_mask);
	__set_bit(resched, si->irq_enable_mask);
	LOCAL_HUB_CLR_INTR(resched);

	call = CPU_CALL_A_IRQ + slice;
	__set_bit(call, hub->irq_alloc_mask);
	__set_bit(call, si->irq_enable_mask);
	LOCAL_HUB_CLR_INTR(call);

	if (slice == 0) {
		LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
		LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
	} else {
		LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
		LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
	3	*
	4	* Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
	5	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	6	* Copyright (C) 1999 - 2001 Kanoj Sarcar
	7	*/
d3ffd085 RB	8
	9	#undef DEBUG
	10
1da177e4 LT	11	#include <linux/config.h>
	12	#include <linux/init.h>
	13	#include <linux/irq.h>
	14	#include <linux/errno.h>
	15	#include <linux/signal.h>
	16	#include <linux/sched.h>
	17	#include <linux/types.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/ioport.h>
1da177e4 LT	20	#include <linux/timex.h>
	21	#include <linux/slab.h>
	22	#include <linux/random.h>
	23	#include <linux/smp_lock.h>
d3ffd085	24	#include <linux/kernel.h>
1da177e4 LT	25	#include <linux/kernel_stat.h>
	26	#include <linux/delay.h>
	27	#include <linux/bitops.h>
	28
	29	#include <asm/bootinfo.h>
	30	#include <asm/io.h>
	31	#include <asm/mipsregs.h>
	32	#include <asm/system.h>
	33
	34	#include <asm/ptrace.h>
	35	#include <asm/processor.h>
	36	#include <asm/pci/bridge.h>
	37	#include <asm/sn/addrs.h>
	38	#include <asm/sn/agent.h>
	39	#include <asm/sn/arch.h>
	40	#include <asm/sn/hub.h>
	41	#include <asm/sn/intr.h>
	42
1da177e4 LT	43	/*
	44	* Linux has a controller-independent x86 interrupt architecture.
	45	* every controller has a 'controller-template', that is used
	46	* by the main code to do the right thing. Each driver-visible
	47	* interrupt source is transparently wired to the apropriate
	48	* controller. Thus drivers need not be aware of the
	49	* interrupt-controller.
	50	*
	51	* Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
	52	* PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
	53	* (IO-APICs assumed to be messaging to Pentium local-APICs)
	54	*
	55	* the code is designed to be easily extended with new/different
	56	* interrupt controllers, without having to do assembly magic.
	57	*/
	58
	59	extern asmlinkage void ip27_irq(void);
	60
	61	extern struct bridge_controller *irq_to_bridge[];
	62	extern int irq_to_slot[];
	63
	64	/*
	65	* use these macros to get the encoded nasid and widget id
	66	* from the irq value
	67	*/
	68	#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
	69	#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
	70
	71	static inline int alloc_level(int cpu, int irq)
	72	{
4f12bfe5	73	struct hub_data *hub = hub_data(cpu_to_node(cpu));
1da177e4	74	struct slice_data *si = cpu_data[cpu].data;
4f12bfe5	75	int level;
1da177e4	76
4f12bfe5	77	level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
1da177e4 LT	78	if (level >= LEVELS_PER_SLICE)
	79	panic("Cpu %d flooded with devices\n", cpu);
	80
4f12bfe5	81	__set_bit(level, hub->irq_alloc_mask);
1da177e4 LT	82	si->level_to_irq[level] = irq;
	83
	84	return level;
	85	}
	86
	87	static inline int find_level(cpuid_t *cpunum, int irq)
	88	{
	89	int cpu, i;
	90
394e3902	91	for_each_online_cpu(cpu) {
1da177e4 LT	92	struct slice_data *si = cpu_data[cpu].data;
1da177e4 LT	93
1da177e4 LT	94	for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
	95	if (si->level_to_irq[i] == irq) {
	96	*cpunum = cpu;
	97
	98	return i;
	99	}
	100	}
	101
	102	panic("Could not identify cpu/level for irq %d\n", irq);
	103	}
	104
	105	/*
	106	* Find first bit set
	107	*/
	108	static int ms1bit(unsigned long x)
	109	{
	110	int b = 0, s;
	111
	112	s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s;
	113	s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s;
	114	s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s;
	115	s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s;
	116	s = 1; if (x >> 1 == 0) s = 0; b += s;
	117
	118	return b;
	119	}
	120
	121	/*
	122	* This code is unnecessarily complex, because we do SA_INTERRUPT
	123	* intr enabling. Basically, once we grab the set of intrs we need
	124	* to service, we must mask _all_ these interrupts; firstly, to make
	125	* sure the same intr does not intr again, causing recursion that
	126	* can lead to stack overflow. Secondly, we can not just mask the
	127	* one intr we are do_IRQing, because the non-masked intrs in the
	128	* first set might intr again, causing multiple servicings of the
	129	* same intr. This effect is mostly seen for intercpu intrs.
	130	* Kanoj 05.13.00
	131	*/
	132
e4ac58af	133	static void ip27_do_irq_mask0(struct pt_regs *regs)
1da177e4 LT	134	{
	135	int irq, swlevel;
	136	hubreg_t pend0, mask0;
	137	cpuid_t cpu = smp_processor_id();
	138	int pi_int_mask0 =
	139	(cputoslice(cpu) == 0) ? PI_INT_MASK0_A : PI_INT_MASK0_B;
	140
	141	/* copied from Irix intpend0() */
	142	pend0 = LOCAL_HUB_L(PI_INT_PEND0);
	143	mask0 = LOCAL_HUB_L(pi_int_mask0);
	144
	145	pend0 &= mask0; /* Pick intrs we should look at */
	146	if (!pend0)
	147	return;
	148
	149	swlevel = ms1bit(pend0);
	150	#ifdef CONFIG_SMP
	151	if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
	152	LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
	153	} else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
	154	LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
	155	} else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
	156	LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
	157	smp_call_function_interrupt();
	158	} else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
	159	LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
	160	smp_call_function_interrupt();
	161	} else
	162	#endif
	163	{
	164	/* "map" swlevel to irq */
	165	struct slice_data *si = cpu_data[cpu].data;
	166
	167	irq = si->level_to_irq[swlevel];
	168	do_IRQ(irq, regs);
	169	}
	170
	171	LOCAL_HUB_L(PI_INT_PEND0);
	172	}
	173
e4ac58af	174	static void ip27_do_irq_mask1(struct pt_regs *regs)
1da177e4 LT	175	{
	176	int irq, swlevel;
	177	hubreg_t pend1, mask1;
	178	cpuid_t cpu = smp_processor_id();
	179	int pi_int_mask1 = (cputoslice(cpu) == 0) ? PI_INT_MASK1_A : PI_INT_MASK1_B;
	180	struct slice_data *si = cpu_data[cpu].data;
	181
	182	/* copied from Irix intpend0() */
	183	pend1 = LOCAL_HUB_L(PI_INT_PEND1);
	184	mask1 = LOCAL_HUB_L(pi_int_mask1);
	185
	186	pend1 &= mask1; /* Pick intrs we should look at */
	187	if (!pend1)
	188	return;
	189
	190	swlevel = ms1bit(pend1);
	191	/* "map" swlevel to irq */
	192	irq = si->level_to_irq[swlevel];
	193	LOCAL_HUB_CLR_INTR(swlevel);
	194	do_IRQ(irq, regs);
	195
	196	LOCAL_HUB_L(PI_INT_PEND1);
	197	}
	198
e4ac58af	199	static void ip27_prof_timer(struct pt_regs *regs)
1da177e4 LT	200	{
	201	panic("CPU %d got a profiling interrupt", smp_processor_id());
	202	}
	203
e4ac58af	204	static void ip27_hub_error(struct pt_regs *regs)
1da177e4 LT	205	{
	206	panic("CPU %d got a hub error interrupt", smp_processor_id());
	207	}
	208
	209	static int intr_connect_level(int cpu, int bit)
	210	{
	211	nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	212	struct slice_data *si = cpu_data[cpu].data;
4f12bfe5	213	unsigned long flags;
1da177e4	214
4f12bfe5	215	set_bit(bit, si->irq_enable_mask);
1da177e4	216
4f12bfe5	217	local_irq_save(flags);
1da177e4 LT	218	if (!cputoslice(cpu)) {
	219	REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
	220	REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
	221	} else {
	222	REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
	223	REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
	224	}
4f12bfe5	225	local_irq_restore(flags);
1da177e4 LT	226
	227	return 0;
	228	}
	229
	230	static int intr_disconnect_level(int cpu, int bit)
	231	{
	232	nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	233	struct slice_data *si = cpu_data[cpu].data;
	234
4f12bfe5	235	clear_bit(bit, si->irq_enable_mask);
1da177e4 LT	236
	237	if (!cputoslice(cpu)) {
	238	REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
	239	REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
	240	} else {
	241	REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
	242	REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
	243	}
	244
	245	return 0;
	246	}
	247
	248	/* Startup one of the (PCI ...) IRQs routes over a bridge. */
	249	static unsigned int startup_bridge_irq(unsigned int irq)
	250	{
	251	struct bridge_controller *bc;
	252	bridgereg_t device;
	253	bridge_t *bridge;
	254	int pin, swlevel;
	255	cpuid_t cpu;
	256
	257	pin = SLOT_FROM_PCI_IRQ(irq);
	258	bc = IRQ_TO_BRIDGE(irq);
	259	bridge = bc->base;
	260
d3ffd085	261	pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin);
1da177e4 LT	262	/*
	263	* "map" irq to a swlevel greater than 6 since the first 6 bits
	264	* of INT_PEND0 are taken
	265	*/
	266	swlevel = find_level(&cpu, irq);
	267	bridge->b_int_addr[pin].addr = (0x20000 \| swlevel \| (bc->nasid << 8));
	268	bridge->b_int_enable \|= (1 << pin);
	269	bridge->b_int_enable \|= 0x7ffffe00; /* more stuff in int_enable */
	270
	271	/*
	272	* Enable sending of an interrupt clear packt to the hub on a high to
	273	* low transition of the interrupt pin.
	274	*
	275	* IRIX sets additional bits in the address which are documented as
	276	* reserved in the bridge docs.
	277	*/
	278	bridge->b_int_mode \|= (1UL << pin);
	279
	280	/*
	281	* We assume the bridge to have a 1:1 mapping between devices
	282	* (slots) and intr pins.
	283	*/
	284	device = bridge->b_int_device;
	285	device &= ~(7 << (pin*3));
	286	device \|= (pin << (pin*3));
	287	bridge->b_int_device = device;
	288
	289	bridge->b_wid_tflush;
	290
	291	return 0; /* Never anything pending. */
	292	}
	293
	294	/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
	295	static void shutdown_bridge_irq(unsigned int irq)
	296	{
	297	struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
4f12bfe5	298	struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu));
1da177e4 LT	299	bridge_t *bridge = bc->base;
	300	struct slice_data *si = cpu_data[bc->irq_cpu].data;
	301	int pin, swlevel;
	302	cpuid_t cpu;
	303
d3ffd085	304	pr_debug("bridge_shutdown: irq 0x%x\n", irq);
1da177e4 LT	305	pin = SLOT_FROM_PCI_IRQ(irq);
	306
	307	/*
	308	* map irq to a swlevel greater than 6 since the first 6 bits
	309	* of INT_PEND0 are taken
	310	*/
	311	swlevel = find_level(&cpu, irq);
	312	intr_disconnect_level(cpu, swlevel);
	313
4f12bfe5	314	__clear_bit(swlevel, hub->irq_alloc_mask);
1da177e4 LT	315	si->level_to_irq[swlevel] = -1;
	316
	317	bridge->b_int_enable &= ~(1 << pin);
	318	bridge->b_wid_tflush;
	319	}
	320
	321	static inline void enable_bridge_irq(unsigned int irq)
	322	{
	323	cpuid_t cpu;
	324	int swlevel;
	325
	326	swlevel = find_level(&cpu, irq); /* Criminal offence */
	327	intr_connect_level(cpu, swlevel);
	328	}
	329
	330	static inline void disable_bridge_irq(unsigned int irq)
	331	{
	332	cpuid_t cpu;
	333	int swlevel;
	334
	335	swlevel = find_level(&cpu, irq); /* Criminal offence */
	336	intr_disconnect_level(cpu, swlevel);
	337	}
	338
	339	static void mask_and_ack_bridge_irq(unsigned int irq)
	340	{
	341	disable_bridge_irq(irq);
	342	}
	343
	344	static void end_bridge_irq(unsigned int irq)
	345	{
	346	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)) &&
	347	irq_desc[irq].action)
	348	enable_bridge_irq(irq);
	349	}
	350
	351	static struct hw_interrupt_type bridge_irq_type = {
	352	.typename = "bridge",
	353	.startup = startup_bridge_irq,
	354	.shutdown = shutdown_bridge_irq,
	355	.enable = enable_bridge_irq,
	356	.disable = disable_bridge_irq,
	357	.ack = mask_and_ack_bridge_irq,
	358	.end = end_bridge_irq,
	359	};
	360
	361	static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
	362
	363	static int allocate_irqno(void)
	364	{
	365	int irq;
	366
	367	again:
	368	irq = find_first_zero_bit(irq_map, NR_IRQS);
	369
	370	if (irq >= NR_IRQS)
	371	return -ENOSPC;
	372
	373	if (test_and_set_bit(irq, irq_map))
	374	goto again;
	375
	376	return irq;
	377	}
	378
379	void free_irqno(unsigned int irq)
380	{
381	clear_bit(irq, irq_map);
382	}
383
384	void __devinit register_bridge_irq(unsigned int irq)
385	{
386	irq_desc[irq].status = IRQ_DISABLED;
387	irq_desc[irq].action = 0;
388	irq_desc[irq].depth = 1;
389	irq_desc[irq].handler = &bridge_irq_type;
390	}
391
392	int __devinit request_bridge_irq(struct bridge_controller *bc)
393	{
394	int irq = allocate_irqno();
395	int swlevel, cpu;
396	nasid_t nasid;
397
398	if (irq < 0)
399	return irq;
400
401	/*
402	* "map" irq to a swlevel greater than 6 since the first 6 bits
403	* of INT_PEND0 are taken
404	*/
405	cpu = bc->irq_cpu;
406	swlevel = alloc_level(cpu, irq);
407	if (unlikely(swlevel < 0)) {
408	free_irqno(irq);
409
410	return -EAGAIN;
411	}
412
413	/* Make sure it's not already pending when we connect it. */
414	nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
415	REMOTE_HUB_CLR_INTR(nasid, swlevel);
416
417	intr_connect_level(cpu, swlevel);
418
419	register_bridge_irq(irq);
420
421	return irq;
422	}
423
e4ac58af RB	424	extern void ip27_rt_timer_interrupt(struct pt_regs *regs);
	425
	426	asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
	427	{
	428	unsigned long pending = read_c0_cause() & read_c0_status();
	429
	430	if (pending & CAUSEF_IP4)
	431	ip27_rt_timer_interrupt(regs);
	432	else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A\|B} */
	433	ip27_do_irq_mask0(regs);
	434	else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */
	435	ip27_do_irq_mask1(regs);
	436	else if (pending & CAUSEF_IP5)
	437	ip27_prof_timer(regs);
	438	else if (pending & CAUSEF_IP6)
	439	ip27_hub_error(regs);
	440	}
	441
1da177e4 LT	442	void __init arch_init_irq(void)
1da177e4 LT	443	{
1da177e4 LT	444	}
	445
	446	void install_ipi(void)
	447	{
	448	int slice = LOCAL_HUB_L(PI_CPU_NUM);
	449	int cpu = smp_processor_id();
	450	struct slice_data *si = cpu_data[cpu].data;
4f12bfe5 RB	451	struct hub_data *hub = hub_data(cpu_to_node(cpu));
	452	int resched, call;
	453
	454	resched = CPU_RESCHED_A_IRQ + slice;
	455	__set_bit(resched, hub->irq_alloc_mask);
	456	__set_bit(resched, si->irq_enable_mask);
	457	LOCAL_HUB_CLR_INTR(resched);
	458
	459	call = CPU_CALL_A_IRQ + slice;
	460	__set_bit(call, hub->irq_alloc_mask);
	461	__set_bit(call, si->irq_enable_mask);
	462	LOCAL_HUB_CLR_INTR(call);
1da177e4 LT	463
1da177e4 LT	464	if (slice == 0) {
4f12bfe5 RB	465	LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
4f12bfe5 RB	466	LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
1da177e4	467	} else {
4f12bfe5 RB	468	LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
4f12bfe5 RB	469	LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);
1da177e4 LT	470	}
1da177e4 LT	471	}