Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Code to handle IP32 IRQs | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 2000 Harald Koerfgen | |
9 | * Copyright (C) 2001 Keith M Wesolowski | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/bitops.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/random.h> | |
21 | #include <linux/sched.h> | |
22 | ||
dd67b155 | 23 | #include <asm/irq_cpu.h> |
1da177e4 LT |
24 | #include <asm/mipsregs.h> |
25 | #include <asm/signal.h> | |
26 | #include <asm/system.h> | |
27 | #include <asm/time.h> | |
28 | #include <asm/ip32/crime.h> | |
29 | #include <asm/ip32/mace.h> | |
30 | #include <asm/ip32/ip32_ints.h> | |
31 | ||
32 | /* issue a PIO read to make sure no PIO writes are pending */ | |
33 | static void inline flush_crime_bus(void) | |
34 | { | |
b6d7c7a9 | 35 | crime->control; |
1da177e4 LT |
36 | } |
37 | ||
38 | static void inline flush_mace_bus(void) | |
39 | { | |
b6d7c7a9 | 40 | mace->perif.ctrl.misc; |
1da177e4 LT |
41 | } |
42 | ||
dd67b155 RB |
43 | /* |
44 | * O2 irq map | |
1da177e4 LT |
45 | * |
46 | * IP0 -> software (ignored) | |
47 | * IP1 -> software (ignored) | |
48 | * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? | |
49 | * IP3 -> (irq1) X unknown | |
50 | * IP4 -> (irq2) X unknown | |
51 | * IP5 -> (irq3) X unknown | |
52 | * IP6 -> (irq4) X unknown | |
dd67b155 | 53 | * IP7 -> (irq5) 7 CPU count/compare timer (system timer) |
1da177e4 LT |
54 | * |
55 | * crime: (C) | |
56 | * | |
57 | * CRIME_INT_STAT 31:0: | |
58 | * | |
dd67b155 RB |
59 | * 0 -> 8 Video in 1 |
60 | * 1 -> 9 Video in 2 | |
61 | * 2 -> 10 Video out | |
62 | * 3 -> 11 Mace ethernet | |
1da177e4 LT |
63 | * 4 -> S SuperIO sub-interrupt |
64 | * 5 -> M Miscellaneous sub-interrupt | |
65 | * 6 -> A Audio sub-interrupt | |
dd67b155 RB |
66 | * 7 -> 15 PCI bridge errors |
67 | * 8 -> 16 PCI SCSI aic7xxx 0 | |
68 | * 9 -> 17 PCI SCSI aic7xxx 1 | |
69 | * 10 -> 18 PCI slot 0 | |
70 | * 11 -> 19 unused (PCI slot 1) | |
71 | * 12 -> 20 unused (PCI slot 2) | |
72 | * 13 -> 21 unused (PCI shared 0) | |
73 | * 14 -> 22 unused (PCI shared 1) | |
74 | * 15 -> 23 unused (PCI shared 2) | |
75 | * 16 -> 24 GBE0 (E) | |
76 | * 17 -> 25 GBE1 (E) | |
77 | * 18 -> 26 GBE2 (E) | |
78 | * 19 -> 27 GBE3 (E) | |
79 | * 20 -> 28 CPU errors | |
80 | * 21 -> 29 Memory errors | |
81 | * 22 -> 30 RE empty edge (E) | |
82 | * 23 -> 31 RE full edge (E) | |
83 | * 24 -> 32 RE idle edge (E) | |
84 | * 25 -> 33 RE empty level | |
85 | * 26 -> 34 RE full level | |
86 | * 27 -> 35 RE idle level | |
87 | * 28 -> 36 unused (software 0) (E) | |
88 | * 29 -> 37 unused (software 1) (E) | |
89 | * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E) | |
90 | * 31 -> 39 VICE | |
1da177e4 LT |
91 | * |
92 | * S, M, A: Use the MACE ISA interrupt register | |
93 | * MACE_ISA_INT_STAT 31:0 | |
94 | * | |
dd67b155 RB |
95 | * 0-7 -> 40-47 Audio |
96 | * 8 -> 48 RTC | |
97 | * 9 -> 49 Keyboard | |
1da177e4 | 98 | * 10 -> X Keyboard polled |
dd67b155 | 99 | * 11 -> 51 Mouse |
1da177e4 | 100 | * 12 -> X Mouse polled |
dd67b155 RB |
101 | * 13-15 -> 53-55 Count/compare timers |
102 | * 16-19 -> 56-59 Parallel (16 E) | |
103 | * 20-25 -> 60-62 Serial 1 (22 E) | |
104 | * 26-31 -> 66-71 Serial 2 (28 E) | |
1da177e4 | 105 | * |
dd67b155 | 106 | * Note that this means IRQs 12-14, 50, and 52 do not exist. This is a |
1da177e4 LT |
107 | * different IRQ map than IRIX uses, but that's OK as Linux irq handling |
108 | * is quite different anyway. | |
109 | */ | |
110 | ||
1da177e4 | 111 | /* Some initial interrupts to set up */ |
937a8015 RB |
112 | extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); |
113 | extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); | |
1da177e4 | 114 | |
4e45171c TG |
115 | struct irqaction memerr_irq = { |
116 | .handler = crime_memerr_intr, | |
117 | .flags = IRQF_DISABLED, | |
118 | .mask = CPU_MASK_NONE, | |
119 | .name = "CRIME memory error", | |
120 | }; | |
8a13ecd7 | 121 | |
4e45171c TG |
122 | struct irqaction cpuerr_irq = { |
123 | .handler = crime_cpuerr_intr, | |
124 | .flags = IRQF_DISABLED, | |
125 | .mask = CPU_MASK_NONE, | |
126 | .name = "CRIME CPU error", | |
127 | }; | |
1da177e4 | 128 | |
1da177e4 LT |
129 | /* |
130 | * This is for pure CRIME interrupts - ie not MACE. The advantage? | |
131 | * We get to split the register in half and do faster lookups. | |
132 | */ | |
133 | ||
134 | static uint64_t crime_mask; | |
135 | ||
8a13ecd7 | 136 | static inline void crime_enable_irq(unsigned int irq) |
1da177e4 | 137 | { |
8a13ecd7 RB |
138 | unsigned int bit = irq - CRIME_IRQ_BASE; |
139 | ||
140 | crime_mask |= 1 << bit; | |
1da177e4 | 141 | crime->imask = crime_mask; |
1da177e4 LT |
142 | } |
143 | ||
8a13ecd7 | 144 | static inline void crime_disable_irq(unsigned int irq) |
1da177e4 | 145 | { |
8a13ecd7 RB |
146 | unsigned int bit = irq - CRIME_IRQ_BASE; |
147 | ||
148 | crime_mask &= ~(1 << bit); | |
1da177e4 LT |
149 | crime->imask = crime_mask; |
150 | flush_crime_bus(); | |
1da177e4 LT |
151 | } |
152 | ||
8a13ecd7 RB |
153 | static void crime_level_mask_and_ack_irq(unsigned int irq) |
154 | { | |
155 | crime_disable_irq(irq); | |
156 | } | |
157 | ||
158 | static void crime_level_end_irq(unsigned int irq) | |
159 | { | |
160 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | |
161 | crime_enable_irq(irq); | |
162 | } | |
163 | ||
164 | static struct irq_chip crime_level_interrupt = { | |
165 | .name = "IP32 CRIME", | |
166 | .ack = crime_level_mask_and_ack_irq, | |
167 | .mask = crime_disable_irq, | |
168 | .mask_ack = crime_level_mask_and_ack_irq, | |
169 | .unmask = crime_enable_irq, | |
170 | .end = crime_level_end_irq, | |
171 | }; | |
172 | ||
173 | static void crime_edge_mask_and_ack_irq(unsigned int irq) | |
1da177e4 | 174 | { |
8a13ecd7 RB |
175 | unsigned int bit = irq - CRIME_IRQ_BASE; |
176 | uint64_t crime_int; | |
177 | ||
1da177e4 | 178 | /* Edge triggered interrupts must be cleared. */ |
8a13ecd7 RB |
179 | |
180 | crime_int = crime->hard_int; | |
181 | crime_int &= ~(1 << bit); | |
182 | crime->hard_int = crime_int; | |
183 | ||
184 | crime_disable_irq(irq); | |
1da177e4 LT |
185 | } |
186 | ||
8a13ecd7 | 187 | static void crime_edge_end_irq(unsigned int irq) |
1da177e4 LT |
188 | { |
189 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | |
8a13ecd7 | 190 | crime_enable_irq(irq); |
1da177e4 LT |
191 | } |
192 | ||
8a13ecd7 RB |
193 | static struct irq_chip crime_edge_interrupt = { |
194 | .name = "IP32 CRIME", | |
195 | .ack = crime_edge_mask_and_ack_irq, | |
196 | .mask = crime_disable_irq, | |
197 | .mask_ack = crime_edge_mask_and_ack_irq, | |
198 | .unmask = crime_enable_irq, | |
199 | .end = crime_edge_end_irq, | |
1da177e4 LT |
200 | }; |
201 | ||
202 | /* | |
203 | * This is for MACE PCI interrupts. We can decrease bus traffic by masking | |
204 | * as close to the source as possible. This also means we can take the | |
205 | * next chunk of the CRIME register in one piece. | |
206 | */ | |
207 | ||
208 | static unsigned long macepci_mask; | |
209 | ||
210 | static void enable_macepci_irq(unsigned int irq) | |
211 | { | |
1da177e4 LT |
212 | macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); |
213 | mace->pci.control = macepci_mask; | |
214 | crime_mask |= 1 << (irq - 1); | |
215 | crime->imask = crime_mask; | |
1da177e4 LT |
216 | } |
217 | ||
218 | static void disable_macepci_irq(unsigned int irq) | |
219 | { | |
1da177e4 LT |
220 | crime_mask &= ~(1 << (irq - 1)); |
221 | crime->imask = crime_mask; | |
222 | flush_crime_bus(); | |
223 | macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); | |
224 | mace->pci.control = macepci_mask; | |
225 | flush_mace_bus(); | |
1da177e4 LT |
226 | } |
227 | ||
228 | static void end_macepci_irq(unsigned int irq) | |
229 | { | |
230 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
231 | enable_macepci_irq(irq); | |
232 | } | |
233 | ||
94dee171 | 234 | static struct irq_chip ip32_macepci_interrupt = { |
70d21cde | 235 | .name = "IP32 MACE PCI", |
1603b5ac AN |
236 | .ack = disable_macepci_irq, |
237 | .mask = disable_macepci_irq, | |
238 | .mask_ack = disable_macepci_irq, | |
239 | .unmask = enable_macepci_irq, | |
8ab00b9a | 240 | .end = end_macepci_irq, |
1da177e4 LT |
241 | }; |
242 | ||
243 | /* This is used for MACE ISA interrupts. That means bits 4-6 in the | |
244 | * CRIME register. | |
245 | */ | |
246 | ||
247 | #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \ | |
248 | MACEISA_AUDIO_SC_INT | \ | |
249 | MACEISA_AUDIO1_DMAT_INT | \ | |
250 | MACEISA_AUDIO1_OF_INT | \ | |
251 | MACEISA_AUDIO2_DMAT_INT | \ | |
252 | MACEISA_AUDIO2_MERR_INT | \ | |
253 | MACEISA_AUDIO3_DMAT_INT | \ | |
254 | MACEISA_AUDIO3_MERR_INT) | |
255 | #define MACEISA_MISC_INT (MACEISA_RTC_INT | \ | |
256 | MACEISA_KEYB_INT | \ | |
257 | MACEISA_KEYB_POLL_INT | \ | |
258 | MACEISA_MOUSE_INT | \ | |
259 | MACEISA_MOUSE_POLL_INT | \ | |
cfbae5d3 TS |
260 | MACEISA_TIMER0_INT | \ |
261 | MACEISA_TIMER1_INT | \ | |
262 | MACEISA_TIMER2_INT) | |
1da177e4 LT |
263 | #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \ |
264 | MACEISA_PAR_CTXA_INT | \ | |
265 | MACEISA_PAR_CTXB_INT | \ | |
266 | MACEISA_PAR_MERR_INT | \ | |
267 | MACEISA_SERIAL1_INT | \ | |
268 | MACEISA_SERIAL1_TDMAT_INT | \ | |
269 | MACEISA_SERIAL1_TDMAPR_INT | \ | |
270 | MACEISA_SERIAL1_TDMAME_INT | \ | |
271 | MACEISA_SERIAL1_RDMAT_INT | \ | |
272 | MACEISA_SERIAL1_RDMAOR_INT | \ | |
273 | MACEISA_SERIAL2_INT | \ | |
274 | MACEISA_SERIAL2_TDMAT_INT | \ | |
275 | MACEISA_SERIAL2_TDMAPR_INT | \ | |
276 | MACEISA_SERIAL2_TDMAME_INT | \ | |
277 | MACEISA_SERIAL2_RDMAT_INT | \ | |
278 | MACEISA_SERIAL2_RDMAOR_INT) | |
279 | ||
280 | static unsigned long maceisa_mask; | |
281 | ||
49a89efb | 282 | static void enable_maceisa_irq(unsigned int irq) |
1da177e4 LT |
283 | { |
284 | unsigned int crime_int = 0; | |
1da177e4 | 285 | |
8a13ecd7 | 286 | pr_debug("maceisa enable: %u\n", irq); |
1da177e4 LT |
287 | |
288 | switch (irq) { | |
289 | case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: | |
290 | crime_int = MACE_AUDIO_INT; | |
291 | break; | |
cfbae5d3 | 292 | case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: |
1da177e4 LT |
293 | crime_int = MACE_MISC_INT; |
294 | break; | |
295 | case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: | |
296 | crime_int = MACE_SUPERIO_INT; | |
297 | break; | |
298 | } | |
8a13ecd7 | 299 | pr_debug("crime_int %08x enabled\n", crime_int); |
1da177e4 LT |
300 | crime_mask |= crime_int; |
301 | crime->imask = crime_mask; | |
302 | maceisa_mask |= 1 << (irq - 33); | |
303 | mace->perif.ctrl.imask = maceisa_mask; | |
1da177e4 LT |
304 | } |
305 | ||
306 | static void disable_maceisa_irq(unsigned int irq) | |
307 | { | |
308 | unsigned int crime_int = 0; | |
1da177e4 | 309 | |
1da177e4 | 310 | maceisa_mask &= ~(1 << (irq - 33)); |
8a13ecd7 | 311 | if (!(maceisa_mask & MACEISA_AUDIO_INT)) |
1da177e4 | 312 | crime_int |= MACE_AUDIO_INT; |
8a13ecd7 | 313 | if (!(maceisa_mask & MACEISA_MISC_INT)) |
1da177e4 | 314 | crime_int |= MACE_MISC_INT; |
8a13ecd7 | 315 | if (!(maceisa_mask & MACEISA_SUPERIO_INT)) |
1da177e4 LT |
316 | crime_int |= MACE_SUPERIO_INT; |
317 | crime_mask &= ~crime_int; | |
318 | crime->imask = crime_mask; | |
319 | flush_crime_bus(); | |
320 | mace->perif.ctrl.imask = maceisa_mask; | |
321 | flush_mace_bus(); | |
1da177e4 LT |
322 | } |
323 | ||
324 | static void mask_and_ack_maceisa_irq(unsigned int irq) | |
325 | { | |
1603b5ac | 326 | unsigned long mace_int; |
1da177e4 LT |
327 | |
328 | switch (irq) { | |
329 | case MACEISA_PARALLEL_IRQ: | |
330 | case MACEISA_SERIAL1_TDMAPR_IRQ: | |
331 | case MACEISA_SERIAL2_TDMAPR_IRQ: | |
332 | /* edge triggered */ | |
1da177e4 LT |
333 | mace_int = mace->perif.ctrl.istat; |
334 | mace_int &= ~(1 << (irq - 33)); | |
335 | mace->perif.ctrl.istat = mace_int; | |
1da177e4 LT |
336 | break; |
337 | } | |
338 | disable_maceisa_irq(irq); | |
339 | } | |
340 | ||
341 | static void end_maceisa_irq(unsigned irq) | |
342 | { | |
343 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | |
344 | enable_maceisa_irq(irq); | |
345 | } | |
346 | ||
94dee171 | 347 | static struct irq_chip ip32_maceisa_interrupt = { |
8a13ecd7 RB |
348 | .name = "IP32 MACE ISA", |
349 | .ack = mask_and_ack_maceisa_irq, | |
350 | .mask = disable_maceisa_irq, | |
351 | .mask_ack = mask_and_ack_maceisa_irq, | |
352 | .unmask = enable_maceisa_irq, | |
353 | .end = end_maceisa_irq, | |
1da177e4 LT |
354 | }; |
355 | ||
356 | /* This is used for regular non-ISA, non-PCI MACE interrupts. That means | |
357 | * bits 0-3 and 7 in the CRIME register. | |
358 | */ | |
359 | ||
360 | static void enable_mace_irq(unsigned int irq) | |
361 | { | |
1da177e4 LT |
362 | crime_mask |= 1 << (irq - 1); |
363 | crime->imask = crime_mask; | |
1da177e4 LT |
364 | } |
365 | ||
366 | static void disable_mace_irq(unsigned int irq) | |
367 | { | |
1da177e4 LT |
368 | crime_mask &= ~(1 << (irq - 1)); |
369 | crime->imask = crime_mask; | |
370 | flush_crime_bus(); | |
1da177e4 LT |
371 | } |
372 | ||
373 | static void end_mace_irq(unsigned int irq) | |
374 | { | |
375 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
376 | enable_mace_irq(irq); | |
377 | } | |
378 | ||
94dee171 | 379 | static struct irq_chip ip32_mace_interrupt = { |
70d21cde | 380 | .name = "IP32 MACE", |
1603b5ac AN |
381 | .ack = disable_mace_irq, |
382 | .mask = disable_mace_irq, | |
383 | .mask_ack = disable_mace_irq, | |
384 | .unmask = enable_mace_irq, | |
8ab00b9a | 385 | .end = end_mace_irq, |
1da177e4 LT |
386 | }; |
387 | ||
937a8015 | 388 | static void ip32_unknown_interrupt(void) |
1da177e4 | 389 | { |
49a89efb RB |
390 | printk("Unknown interrupt occurred!\n"); |
391 | printk("cp0_status: %08x\n", read_c0_status()); | |
392 | printk("cp0_cause: %08x\n", read_c0_cause()); | |
393 | printk("CRIME intr mask: %016lx\n", crime->imask); | |
394 | printk("CRIME intr status: %016lx\n", crime->istat); | |
395 | printk("CRIME hardware intr register: %016lx\n", crime->hard_int); | |
396 | printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); | |
397 | printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); | |
398 | printk("MACE PCI control register: %08x\n", mace->pci.control); | |
1da177e4 LT |
399 | |
400 | printk("Register dump:\n"); | |
937a8015 | 401 | show_regs(get_irq_regs()); |
1da177e4 LT |
402 | |
403 | printk("Please mail this report to linux-mips@linux-mips.org\n"); | |
404 | printk("Spinning..."); | |
405 | while(1) ; | |
406 | } | |
407 | ||
408 | /* CRIME 1.1 appears to deliver all interrupts to this one pin. */ | |
409 | /* change this to loop over all edge-triggered irqs, exception masked out ones */ | |
937a8015 | 410 | static void ip32_irq0(void) |
1da177e4 LT |
411 | { |
412 | uint64_t crime_int; | |
413 | int irq = 0; | |
414 | ||
dd67b155 RB |
415 | /* |
416 | * Sanity check interrupt numbering enum. | |
417 | * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy | |
418 | * chained. | |
419 | */ | |
420 | BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31); | |
421 | BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31); | |
422 | ||
1da177e4 | 423 | crime_int = crime->istat & crime_mask; |
dd67b155 | 424 | irq = MACE_VID_IN1_IRQ + __ffs(crime_int); |
6f8782c4 | 425 | crime_int = 1 << irq; |
1da177e4 LT |
426 | |
427 | if (crime_int & CRIME_MACEISA_INT_MASK) { | |
428 | unsigned long mace_int = mace->perif.ctrl.istat; | |
dd67b155 | 429 | irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ; |
1da177e4 | 430 | } |
dd67b155 | 431 | |
8a13ecd7 | 432 | pr_debug("*irq %u*\n", irq); |
937a8015 | 433 | do_IRQ(irq); |
1da177e4 LT |
434 | } |
435 | ||
937a8015 | 436 | static void ip32_irq1(void) |
1da177e4 | 437 | { |
937a8015 | 438 | ip32_unknown_interrupt(); |
1da177e4 LT |
439 | } |
440 | ||
937a8015 | 441 | static void ip32_irq2(void) |
1da177e4 | 442 | { |
937a8015 | 443 | ip32_unknown_interrupt(); |
1da177e4 LT |
444 | } |
445 | ||
937a8015 | 446 | static void ip32_irq3(void) |
1da177e4 | 447 | { |
937a8015 | 448 | ip32_unknown_interrupt(); |
1da177e4 LT |
449 | } |
450 | ||
937a8015 | 451 | static void ip32_irq4(void) |
1da177e4 | 452 | { |
937a8015 | 453 | ip32_unknown_interrupt(); |
1da177e4 LT |
454 | } |
455 | ||
937a8015 | 456 | static void ip32_irq5(void) |
1da177e4 | 457 | { |
dd67b155 | 458 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
1da177e4 LT |
459 | } |
460 | ||
937a8015 | 461 | asmlinkage void plat_irq_dispatch(void) |
e4ac58af | 462 | { |
119537c0 | 463 | unsigned int pending = read_c0_status() & read_c0_cause(); |
e4ac58af RB |
464 | |
465 | if (likely(pending & IE_IRQ0)) | |
937a8015 | 466 | ip32_irq0(); |
e4ac58af | 467 | else if (unlikely(pending & IE_IRQ1)) |
937a8015 | 468 | ip32_irq1(); |
e4ac58af | 469 | else if (unlikely(pending & IE_IRQ2)) |
937a8015 | 470 | ip32_irq2(); |
e4ac58af | 471 | else if (unlikely(pending & IE_IRQ3)) |
937a8015 | 472 | ip32_irq3(); |
e4ac58af | 473 | else if (unlikely(pending & IE_IRQ4)) |
937a8015 | 474 | ip32_irq4(); |
e4ac58af | 475 | else if (likely(pending & IE_IRQ5)) |
937a8015 | 476 | ip32_irq5(); |
e4ac58af RB |
477 | } |
478 | ||
1da177e4 LT |
479 | void __init arch_init_irq(void) |
480 | { | |
481 | unsigned int irq; | |
482 | ||
483 | /* Install our interrupt handler, then clear and disable all | |
484 | * CRIME and MACE interrupts. */ | |
485 | crime->imask = 0; | |
486 | crime->hard_int = 0; | |
487 | crime->soft_int = 0; | |
488 | mace->perif.ctrl.istat = 0; | |
489 | mace->perif.ctrl.imask = 0; | |
1da177e4 | 490 | |
dd67b155 RB |
491 | mips_cpu_irq_init(); |
492 | for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) { | |
dd67b155 RB |
493 | switch (irq) { |
494 | case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: | |
8a13ecd7 | 495 | set_irq_chip(irq, &ip32_mace_interrupt); |
dd67b155 RB |
496 | break; |
497 | case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: | |
8a13ecd7 RB |
498 | set_irq_chip(irq, &ip32_macepci_interrupt); |
499 | break; | |
500 | case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: | |
501 | set_irq_chip(irq, &crime_edge_interrupt); | |
502 | break; | |
503 | case CRIME_CPUERR_IRQ: | |
504 | case CRIME_MEMERR_IRQ: | |
505 | set_irq_chip(irq, &crime_level_interrupt); | |
dd67b155 | 506 | break; |
8a13ecd7 RB |
507 | case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: |
508 | case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: | |
509 | set_irq_chip(irq, &crime_edge_interrupt); | |
510 | break; | |
511 | case CRIME_VICE_IRQ: | |
512 | set_irq_chip(irq, &crime_edge_interrupt); | |
dd67b155 RB |
513 | break; |
514 | default: | |
8a13ecd7 RB |
515 | set_irq_chip(irq, &ip32_maceisa_interrupt); |
516 | break; | |
dd67b155 | 517 | } |
1da177e4 LT |
518 | } |
519 | setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); | |
520 | setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); | |
521 | ||
522 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) | |
523 | change_c0_status(ST0_IM, ALLINTS); | |
524 | } |