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1da177e4 LT |
1 | /* |
2 | * Code to handle IP32 IRQs | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 2000 Harald Koerfgen | |
9 | * Copyright (C) 2001 Keith M Wesolowski | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/bitops.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/random.h> | |
21 | #include <linux/sched.h> | |
22 | ||
23 | #include <asm/mipsregs.h> | |
24 | #include <asm/signal.h> | |
25 | #include <asm/system.h> | |
26 | #include <asm/time.h> | |
27 | #include <asm/ip32/crime.h> | |
28 | #include <asm/ip32/mace.h> | |
29 | #include <asm/ip32/ip32_ints.h> | |
30 | ||
31 | /* issue a PIO read to make sure no PIO writes are pending */ | |
32 | static void inline flush_crime_bus(void) | |
33 | { | |
b6d7c7a9 | 34 | crime->control; |
1da177e4 LT |
35 | } |
36 | ||
37 | static void inline flush_mace_bus(void) | |
38 | { | |
b6d7c7a9 | 39 | mace->perif.ctrl.misc; |
1da177e4 LT |
40 | } |
41 | ||
42 | #undef DEBUG_IRQ | |
43 | #ifdef DEBUG_IRQ | |
44 | #define DBG(x...) printk(x) | |
45 | #else | |
46 | #define DBG(x...) | |
47 | #endif | |
48 | ||
49 | /* O2 irq map | |
50 | * | |
51 | * IP0 -> software (ignored) | |
52 | * IP1 -> software (ignored) | |
53 | * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? | |
54 | * IP3 -> (irq1) X unknown | |
55 | * IP4 -> (irq2) X unknown | |
56 | * IP5 -> (irq3) X unknown | |
57 | * IP6 -> (irq4) X unknown | |
58 | * IP7 -> (irq5) 0 CPU count/compare timer (system timer) | |
59 | * | |
60 | * crime: (C) | |
61 | * | |
62 | * CRIME_INT_STAT 31:0: | |
63 | * | |
64 | * 0 -> 1 Video in 1 | |
65 | * 1 -> 2 Video in 2 | |
66 | * 2 -> 3 Video out | |
67 | * 3 -> 4 Mace ethernet | |
68 | * 4 -> S SuperIO sub-interrupt | |
69 | * 5 -> M Miscellaneous sub-interrupt | |
70 | * 6 -> A Audio sub-interrupt | |
71 | * 7 -> 8 PCI bridge errors | |
72 | * 8 -> 9 PCI SCSI aic7xxx 0 | |
73 | * 9 -> 10 PCI SCSI aic7xxx 1 | |
74 | * 10 -> 11 PCI slot 0 | |
75 | * 11 -> 12 unused (PCI slot 1) | |
76 | * 12 -> 13 unused (PCI slot 2) | |
77 | * 13 -> 14 unused (PCI shared 0) | |
78 | * 14 -> 15 unused (PCI shared 1) | |
79 | * 15 -> 16 unused (PCI shared 2) | |
80 | * 16 -> 17 GBE0 (E) | |
81 | * 17 -> 18 GBE1 (E) | |
82 | * 18 -> 19 GBE2 (E) | |
83 | * 19 -> 20 GBE3 (E) | |
84 | * 20 -> 21 CPU errors | |
85 | * 21 -> 22 Memory errors | |
86 | * 22 -> 23 RE empty edge (E) | |
87 | * 23 -> 24 RE full edge (E) | |
88 | * 24 -> 25 RE idle edge (E) | |
89 | * 25 -> 26 RE empty level | |
90 | * 26 -> 27 RE full level | |
91 | * 27 -> 28 RE idle level | |
92 | * 28 -> 29 unused (software 0) (E) | |
93 | * 29 -> 30 unused (software 1) (E) | |
94 | * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E) | |
95 | * 31 -> 32 VICE | |
96 | * | |
97 | * S, M, A: Use the MACE ISA interrupt register | |
98 | * MACE_ISA_INT_STAT 31:0 | |
99 | * | |
100 | * 0-7 -> 33-40 Audio | |
101 | * 8 -> 41 RTC | |
102 | * 9 -> 42 Keyboard | |
103 | * 10 -> X Keyboard polled | |
104 | * 11 -> 44 Mouse | |
105 | * 12 -> X Mouse polled | |
106 | * 13-15 -> 46-48 Count/compare timers | |
107 | * 16-19 -> 49-52 Parallel (16 E) | |
108 | * 20-25 -> 53-58 Serial 1 (22 E) | |
109 | * 26-31 -> 59-64 Serial 2 (28 E) | |
110 | * | |
111 | * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a | |
112 | * different IRQ map than IRIX uses, but that's OK as Linux irq handling | |
113 | * is quite different anyway. | |
114 | */ | |
115 | ||
116 | /* | |
117 | * IRQ spinlock - Ralf says not to disable CPU interrupts, | |
118 | * and I think he knows better. | |
119 | */ | |
120 | static DEFINE_SPINLOCK(ip32_irq_lock); | |
121 | ||
122 | /* Some initial interrupts to set up */ | |
937a8015 RB |
123 | extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); |
124 | extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); | |
1da177e4 | 125 | |
f40298fd | 126 | struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED, |
1da177e4 | 127 | CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; |
f40298fd | 128 | struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED, |
1da177e4 LT |
129 | CPU_MASK_NONE, "CRIME CPU error", NULL, NULL }; |
130 | ||
1da177e4 LT |
131 | /* |
132 | * For interrupts wired from a single device to the CPU. Only the clock | |
133 | * uses this it seems, which is IRQ 0 and IP7. | |
134 | */ | |
135 | ||
136 | static void enable_cpu_irq(unsigned int irq) | |
137 | { | |
138 | set_c0_status(STATUSF_IP7); | |
139 | } | |
140 | ||
141 | static unsigned int startup_cpu_irq(unsigned int irq) | |
142 | { | |
143 | enable_cpu_irq(irq); | |
144 | return 0; | |
145 | } | |
146 | ||
147 | static void disable_cpu_irq(unsigned int irq) | |
148 | { | |
149 | clear_c0_status(STATUSF_IP7); | |
150 | } | |
151 | ||
152 | static void end_cpu_irq(unsigned int irq) | |
153 | { | |
154 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | |
155 | enable_cpu_irq (irq); | |
156 | } | |
157 | ||
158 | #define shutdown_cpu_irq disable_cpu_irq | |
159 | #define mask_and_ack_cpu_irq disable_cpu_irq | |
160 | ||
94dee171 | 161 | static struct irq_chip ip32_cpu_interrupt = { |
8ab00b9a RB |
162 | .typename = "IP32 CPU", |
163 | .startup = startup_cpu_irq, | |
164 | .shutdown = shutdown_cpu_irq, | |
165 | .enable = enable_cpu_irq, | |
166 | .disable = disable_cpu_irq, | |
167 | .ack = mask_and_ack_cpu_irq, | |
168 | .end = end_cpu_irq, | |
1da177e4 LT |
169 | }; |
170 | ||
171 | /* | |
172 | * This is for pure CRIME interrupts - ie not MACE. The advantage? | |
173 | * We get to split the register in half and do faster lookups. | |
174 | */ | |
175 | ||
176 | static uint64_t crime_mask; | |
177 | ||
178 | static void enable_crime_irq(unsigned int irq) | |
179 | { | |
180 | unsigned long flags; | |
181 | ||
182 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
183 | crime_mask |= 1 << (irq - 1); | |
184 | crime->imask = crime_mask; | |
185 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
186 | } | |
187 | ||
188 | static unsigned int startup_crime_irq(unsigned int irq) | |
189 | { | |
190 | enable_crime_irq(irq); | |
191 | return 0; /* This is probably not right; we could have pending irqs */ | |
192 | } | |
193 | ||
194 | static void disable_crime_irq(unsigned int irq) | |
195 | { | |
196 | unsigned long flags; | |
197 | ||
198 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
199 | crime_mask &= ~(1 << (irq - 1)); | |
200 | crime->imask = crime_mask; | |
201 | flush_crime_bus(); | |
202 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
203 | } | |
204 | ||
205 | static void mask_and_ack_crime_irq(unsigned int irq) | |
206 | { | |
207 | unsigned long flags; | |
208 | ||
209 | /* Edge triggered interrupts must be cleared. */ | |
210 | if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) | |
211 | || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) | |
212 | || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { | |
213 | uint64_t crime_int; | |
214 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
215 | crime_int = crime->hard_int; | |
216 | crime_int &= ~(1 << (irq - 1)); | |
217 | crime->hard_int = crime_int; | |
218 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
219 | } | |
220 | disable_crime_irq(irq); | |
221 | } | |
222 | ||
223 | static void end_crime_irq(unsigned int irq) | |
224 | { | |
225 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | |
226 | enable_crime_irq(irq); | |
227 | } | |
228 | ||
229 | #define shutdown_crime_irq disable_crime_irq | |
230 | ||
94dee171 | 231 | static struct irq_chip ip32_crime_interrupt = { |
8ab00b9a RB |
232 | .typename = "IP32 CRIME", |
233 | .startup = startup_crime_irq, | |
234 | .shutdown = shutdown_crime_irq, | |
235 | .enable = enable_crime_irq, | |
236 | .disable = disable_crime_irq, | |
237 | .ack = mask_and_ack_crime_irq, | |
238 | .end = end_crime_irq, | |
1da177e4 LT |
239 | }; |
240 | ||
241 | /* | |
242 | * This is for MACE PCI interrupts. We can decrease bus traffic by masking | |
243 | * as close to the source as possible. This also means we can take the | |
244 | * next chunk of the CRIME register in one piece. | |
245 | */ | |
246 | ||
247 | static unsigned long macepci_mask; | |
248 | ||
249 | static void enable_macepci_irq(unsigned int irq) | |
250 | { | |
251 | unsigned long flags; | |
252 | ||
253 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
254 | macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); | |
255 | mace->pci.control = macepci_mask; | |
256 | crime_mask |= 1 << (irq - 1); | |
257 | crime->imask = crime_mask; | |
258 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
259 | } | |
260 | ||
261 | static unsigned int startup_macepci_irq(unsigned int irq) | |
262 | { | |
263 | enable_macepci_irq (irq); | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static void disable_macepci_irq(unsigned int irq) | |
268 | { | |
269 | unsigned long flags; | |
270 | ||
271 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
272 | crime_mask &= ~(1 << (irq - 1)); | |
273 | crime->imask = crime_mask; | |
274 | flush_crime_bus(); | |
275 | macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); | |
276 | mace->pci.control = macepci_mask; | |
277 | flush_mace_bus(); | |
278 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
279 | } | |
280 | ||
281 | static void end_macepci_irq(unsigned int irq) | |
282 | { | |
283 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
284 | enable_macepci_irq(irq); | |
285 | } | |
286 | ||
287 | #define shutdown_macepci_irq disable_macepci_irq | |
288 | #define mask_and_ack_macepci_irq disable_macepci_irq | |
289 | ||
94dee171 | 290 | static struct irq_chip ip32_macepci_interrupt = { |
8ab00b9a RB |
291 | .typename = "IP32 MACE PCI", |
292 | .startup = startup_macepci_irq, | |
293 | .shutdown = shutdown_macepci_irq, | |
294 | .enable = enable_macepci_irq, | |
295 | .disable = disable_macepci_irq, | |
296 | .ack = mask_and_ack_macepci_irq, | |
297 | .end = end_macepci_irq, | |
1da177e4 LT |
298 | }; |
299 | ||
300 | /* This is used for MACE ISA interrupts. That means bits 4-6 in the | |
301 | * CRIME register. | |
302 | */ | |
303 | ||
304 | #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \ | |
305 | MACEISA_AUDIO_SC_INT | \ | |
306 | MACEISA_AUDIO1_DMAT_INT | \ | |
307 | MACEISA_AUDIO1_OF_INT | \ | |
308 | MACEISA_AUDIO2_DMAT_INT | \ | |
309 | MACEISA_AUDIO2_MERR_INT | \ | |
310 | MACEISA_AUDIO3_DMAT_INT | \ | |
311 | MACEISA_AUDIO3_MERR_INT) | |
312 | #define MACEISA_MISC_INT (MACEISA_RTC_INT | \ | |
313 | MACEISA_KEYB_INT | \ | |
314 | MACEISA_KEYB_POLL_INT | \ | |
315 | MACEISA_MOUSE_INT | \ | |
316 | MACEISA_MOUSE_POLL_INT | \ | |
cfbae5d3 TS |
317 | MACEISA_TIMER0_INT | \ |
318 | MACEISA_TIMER1_INT | \ | |
319 | MACEISA_TIMER2_INT) | |
1da177e4 LT |
320 | #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \ |
321 | MACEISA_PAR_CTXA_INT | \ | |
322 | MACEISA_PAR_CTXB_INT | \ | |
323 | MACEISA_PAR_MERR_INT | \ | |
324 | MACEISA_SERIAL1_INT | \ | |
325 | MACEISA_SERIAL1_TDMAT_INT | \ | |
326 | MACEISA_SERIAL1_TDMAPR_INT | \ | |
327 | MACEISA_SERIAL1_TDMAME_INT | \ | |
328 | MACEISA_SERIAL1_RDMAT_INT | \ | |
329 | MACEISA_SERIAL1_RDMAOR_INT | \ | |
330 | MACEISA_SERIAL2_INT | \ | |
331 | MACEISA_SERIAL2_TDMAT_INT | \ | |
332 | MACEISA_SERIAL2_TDMAPR_INT | \ | |
333 | MACEISA_SERIAL2_TDMAME_INT | \ | |
334 | MACEISA_SERIAL2_RDMAT_INT | \ | |
335 | MACEISA_SERIAL2_RDMAOR_INT) | |
336 | ||
337 | static unsigned long maceisa_mask; | |
338 | ||
339 | static void enable_maceisa_irq (unsigned int irq) | |
340 | { | |
341 | unsigned int crime_int = 0; | |
342 | unsigned long flags; | |
343 | ||
344 | DBG ("maceisa enable: %u\n", irq); | |
345 | ||
346 | switch (irq) { | |
347 | case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: | |
348 | crime_int = MACE_AUDIO_INT; | |
349 | break; | |
cfbae5d3 | 350 | case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: |
1da177e4 LT |
351 | crime_int = MACE_MISC_INT; |
352 | break; | |
353 | case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: | |
354 | crime_int = MACE_SUPERIO_INT; | |
355 | break; | |
356 | } | |
357 | DBG ("crime_int %08x enabled\n", crime_int); | |
358 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
359 | crime_mask |= crime_int; | |
360 | crime->imask = crime_mask; | |
361 | maceisa_mask |= 1 << (irq - 33); | |
362 | mace->perif.ctrl.imask = maceisa_mask; | |
363 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
364 | } | |
365 | ||
366 | static unsigned int startup_maceisa_irq(unsigned int irq) | |
367 | { | |
368 | enable_maceisa_irq(irq); | |
369 | return 0; | |
370 | } | |
371 | ||
372 | static void disable_maceisa_irq(unsigned int irq) | |
373 | { | |
374 | unsigned int crime_int = 0; | |
375 | unsigned long flags; | |
376 | ||
377 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
378 | maceisa_mask &= ~(1 << (irq - 33)); | |
379 | if(!(maceisa_mask & MACEISA_AUDIO_INT)) | |
380 | crime_int |= MACE_AUDIO_INT; | |
381 | if(!(maceisa_mask & MACEISA_MISC_INT)) | |
382 | crime_int |= MACE_MISC_INT; | |
383 | if(!(maceisa_mask & MACEISA_SUPERIO_INT)) | |
384 | crime_int |= MACE_SUPERIO_INT; | |
385 | crime_mask &= ~crime_int; | |
386 | crime->imask = crime_mask; | |
387 | flush_crime_bus(); | |
388 | mace->perif.ctrl.imask = maceisa_mask; | |
389 | flush_mace_bus(); | |
390 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
391 | } | |
392 | ||
393 | static void mask_and_ack_maceisa_irq(unsigned int irq) | |
394 | { | |
395 | unsigned long mace_int, flags; | |
396 | ||
397 | switch (irq) { | |
398 | case MACEISA_PARALLEL_IRQ: | |
399 | case MACEISA_SERIAL1_TDMAPR_IRQ: | |
400 | case MACEISA_SERIAL2_TDMAPR_IRQ: | |
401 | /* edge triggered */ | |
402 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
403 | mace_int = mace->perif.ctrl.istat; | |
404 | mace_int &= ~(1 << (irq - 33)); | |
405 | mace->perif.ctrl.istat = mace_int; | |
406 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
407 | break; | |
408 | } | |
409 | disable_maceisa_irq(irq); | |
410 | } | |
411 | ||
412 | static void end_maceisa_irq(unsigned irq) | |
413 | { | |
414 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | |
415 | enable_maceisa_irq(irq); | |
416 | } | |
417 | ||
418 | #define shutdown_maceisa_irq disable_maceisa_irq | |
419 | ||
94dee171 | 420 | static struct irq_chip ip32_maceisa_interrupt = { |
8ab00b9a RB |
421 | .typename = "IP32 MACE ISA", |
422 | .startup = startup_maceisa_irq, | |
423 | .shutdown = shutdown_maceisa_irq, | |
424 | .enable = enable_maceisa_irq, | |
425 | .disable = disable_maceisa_irq, | |
426 | .ack = mask_and_ack_maceisa_irq, | |
427 | .end = end_maceisa_irq, | |
1da177e4 LT |
428 | }; |
429 | ||
430 | /* This is used for regular non-ISA, non-PCI MACE interrupts. That means | |
431 | * bits 0-3 and 7 in the CRIME register. | |
432 | */ | |
433 | ||
434 | static void enable_mace_irq(unsigned int irq) | |
435 | { | |
436 | unsigned long flags; | |
437 | ||
438 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
439 | crime_mask |= 1 << (irq - 1); | |
440 | crime->imask = crime_mask; | |
441 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
442 | } | |
443 | ||
444 | static unsigned int startup_mace_irq(unsigned int irq) | |
445 | { | |
446 | enable_mace_irq(irq); | |
447 | return 0; | |
448 | } | |
449 | ||
450 | static void disable_mace_irq(unsigned int irq) | |
451 | { | |
452 | unsigned long flags; | |
453 | ||
454 | spin_lock_irqsave(&ip32_irq_lock, flags); | |
455 | crime_mask &= ~(1 << (irq - 1)); | |
456 | crime->imask = crime_mask; | |
457 | flush_crime_bus(); | |
458 | spin_unlock_irqrestore(&ip32_irq_lock, flags); | |
459 | } | |
460 | ||
461 | static void end_mace_irq(unsigned int irq) | |
462 | { | |
463 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
464 | enable_mace_irq(irq); | |
465 | } | |
466 | ||
467 | #define shutdown_mace_irq disable_mace_irq | |
468 | #define mask_and_ack_mace_irq disable_mace_irq | |
469 | ||
94dee171 | 470 | static struct irq_chip ip32_mace_interrupt = { |
8ab00b9a RB |
471 | .typename = "IP32 MACE", |
472 | .startup = startup_mace_irq, | |
473 | .shutdown = shutdown_mace_irq, | |
474 | .enable = enable_mace_irq, | |
475 | .disable = disable_mace_irq, | |
476 | .ack = mask_and_ack_mace_irq, | |
477 | .end = end_mace_irq, | |
1da177e4 LT |
478 | }; |
479 | ||
937a8015 | 480 | static void ip32_unknown_interrupt(void) |
1da177e4 LT |
481 | { |
482 | printk ("Unknown interrupt occurred!\n"); | |
483 | printk ("cp0_status: %08x\n", read_c0_status()); | |
484 | printk ("cp0_cause: %08x\n", read_c0_cause()); | |
485 | printk ("CRIME intr mask: %016lx\n", crime->imask); | |
486 | printk ("CRIME intr status: %016lx\n", crime->istat); | |
487 | printk ("CRIME hardware intr register: %016lx\n", crime->hard_int); | |
488 | printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); | |
489 | printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); | |
490 | printk ("MACE PCI control register: %08x\n", mace->pci.control); | |
491 | ||
492 | printk("Register dump:\n"); | |
937a8015 | 493 | show_regs(get_irq_regs()); |
1da177e4 LT |
494 | |
495 | printk("Please mail this report to linux-mips@linux-mips.org\n"); | |
496 | printk("Spinning..."); | |
497 | while(1) ; | |
498 | } | |
499 | ||
500 | /* CRIME 1.1 appears to deliver all interrupts to this one pin. */ | |
501 | /* change this to loop over all edge-triggered irqs, exception masked out ones */ | |
937a8015 | 502 | static void ip32_irq0(void) |
1da177e4 LT |
503 | { |
504 | uint64_t crime_int; | |
505 | int irq = 0; | |
506 | ||
507 | crime_int = crime->istat & crime_mask; | |
6f8782c4 AN |
508 | irq = __ffs(crime_int); |
509 | crime_int = 1 << irq; | |
1da177e4 LT |
510 | |
511 | if (crime_int & CRIME_MACEISA_INT_MASK) { | |
512 | unsigned long mace_int = mace->perif.ctrl.istat; | |
6f8782c4 | 513 | irq = __ffs(mace_int & maceisa_mask) + 32; |
1da177e4 | 514 | } |
6f8782c4 | 515 | irq++; |
1da177e4 | 516 | DBG("*irq %u*\n", irq); |
937a8015 | 517 | do_IRQ(irq); |
1da177e4 LT |
518 | } |
519 | ||
937a8015 | 520 | static void ip32_irq1(void) |
1da177e4 | 521 | { |
937a8015 | 522 | ip32_unknown_interrupt(); |
1da177e4 LT |
523 | } |
524 | ||
937a8015 | 525 | static void ip32_irq2(void) |
1da177e4 | 526 | { |
937a8015 | 527 | ip32_unknown_interrupt(); |
1da177e4 LT |
528 | } |
529 | ||
937a8015 | 530 | static void ip32_irq3(void) |
1da177e4 | 531 | { |
937a8015 | 532 | ip32_unknown_interrupt(); |
1da177e4 LT |
533 | } |
534 | ||
937a8015 | 535 | static void ip32_irq4(void) |
1da177e4 | 536 | { |
937a8015 | 537 | ip32_unknown_interrupt(); |
1da177e4 LT |
538 | } |
539 | ||
937a8015 | 540 | static void ip32_irq5(void) |
1da177e4 | 541 | { |
937a8015 | 542 | ll_timer_interrupt(IP32_R4K_TIMER_IRQ); |
1da177e4 LT |
543 | } |
544 | ||
937a8015 | 545 | asmlinkage void plat_irq_dispatch(void) |
e4ac58af RB |
546 | { |
547 | unsigned int pending = read_c0_cause(); | |
548 | ||
549 | if (likely(pending & IE_IRQ0)) | |
937a8015 | 550 | ip32_irq0(); |
e4ac58af | 551 | else if (unlikely(pending & IE_IRQ1)) |
937a8015 | 552 | ip32_irq1(); |
e4ac58af | 553 | else if (unlikely(pending & IE_IRQ2)) |
937a8015 | 554 | ip32_irq2(); |
e4ac58af | 555 | else if (unlikely(pending & IE_IRQ3)) |
937a8015 | 556 | ip32_irq3(); |
e4ac58af | 557 | else if (unlikely(pending & IE_IRQ4)) |
937a8015 | 558 | ip32_irq4(); |
e4ac58af | 559 | else if (likely(pending & IE_IRQ5)) |
937a8015 | 560 | ip32_irq5(); |
e4ac58af RB |
561 | } |
562 | ||
1da177e4 LT |
563 | void __init arch_init_irq(void) |
564 | { | |
565 | unsigned int irq; | |
566 | ||
567 | /* Install our interrupt handler, then clear and disable all | |
568 | * CRIME and MACE interrupts. */ | |
569 | crime->imask = 0; | |
570 | crime->hard_int = 0; | |
571 | crime->soft_int = 0; | |
572 | mace->perif.ctrl.istat = 0; | |
573 | mace->perif.ctrl.imask = 0; | |
1da177e4 LT |
574 | |
575 | for (irq = 0; irq <= IP32_IRQ_MAX; irq++) { | |
94dee171 | 576 | struct irq_chip *controller; |
1da177e4 LT |
577 | |
578 | if (irq == IP32_R4K_TIMER_IRQ) | |
579 | controller = &ip32_cpu_interrupt; | |
580 | else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ) | |
581 | controller = &ip32_mace_interrupt; | |
582 | else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ) | |
583 | controller = &ip32_macepci_interrupt; | |
584 | else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ) | |
585 | controller = &ip32_crime_interrupt; | |
586 | else | |
587 | controller = &ip32_maceisa_interrupt; | |
588 | ||
589 | irq_desc[irq].status = IRQ_DISABLED; | |
590 | irq_desc[irq].action = 0; | |
591 | irq_desc[irq].depth = 0; | |
d1bef4ed | 592 | irq_desc[irq].chip = controller; |
1da177e4 LT |
593 | } |
594 | setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); | |
595 | setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); | |
596 | ||
597 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) | |
598 | change_c0_status(ST0_IM, ALLINTS); | |
599 | } |