[deliverable/linux.git] / arch / mips / sibyte / Kconfig

config SIBYTE_SB1250
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_ENABLE_LDT_IF_PCI
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC
	select SYS_SUPPORTS_SMP

config SIBYTE_BCM1120
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select IRQ_MIPS_CPU
	select SIBYTE_BCM112X
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM1125
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_BCM112X
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM1125H
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_BCM112X
	select SIBYTE_ENABLE_LDT_IF_PCI
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM112X
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select IRQ_MIPS_CPU
	select SIBYTE_SB1xxx_SOC
	select SIBYTE_HAS_ZBUS_PROFILING

config SIBYTE_BCM1x80
	bool
	select CEVT_BCM1480
	select CSRC_BCM1480
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC
	select SYS_SUPPORTS_SMP

config SIBYTE_BCM1x55
	bool
	select CEVT_BCM1480
	select CSRC_BCM1480
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_SB1xxx_SOC
	select SIBYTE_HAS_ZBUS_PROFILING
	select SYS_SUPPORTS_SMP

config SIBYTE_SB1xxx_SOC
	bool
	select DMA_COHERENT
	select IRQ_MIPS_CPU
	select SWAP_IO_SPACE
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select FW_CFE
	select SYS_HAS_EARLY_PRINTK

choice
	prompt "SiByte SOC Stepping"
	depends on SIBYTE_SB1xxx_SOC

config CPU_SB1_PASS_2_1250
	bool "1250 An"
	depends on SIBYTE_SB1250
	select CPU_SB1_PASS_2
	help
	  Also called BCM1250 Pass 2

config CPU_SB1_PASS_2_2
	bool "1250 Bn"
	depends on SIBYTE_SB1250
	select CPU_HAS_PREFETCH
	help
	  Also called BCM1250 Pass 2.2

config CPU_SB1_PASS_4
	bool "1250 Cn"
	depends on SIBYTE_SB1250
	select CPU_HAS_PREFETCH
	help
	  Also called BCM1250 Pass 3

config CPU_SB1_PASS_2_112x
	bool "112x Hybrid"
	depends on SIBYTE_BCM112X
	select CPU_SB1_PASS_2

config CPU_SB1_PASS_3
	bool "112x An"
	depends on SIBYTE_BCM112X
	select CPU_HAS_PREFETCH

endchoice

config CPU_SB1_PASS_2
	bool

config SIBYTE_HAS_LDT
	bool

config SIBYTE_ENABLE_LDT_IF_PCI
	bool
	select SIBYTE_HAS_LDT if PCI

config SB1_CEX_ALWAYS_FATAL
	bool "All cache exceptions considered fatal (no recovery attempted)"
	depends on SIBYTE_SB1xxx_SOC

config SB1_CERR_STALL
	bool "Stall (rather than panic) on fatal cache error"
	depends on SIBYTE_SB1xxx_SOC

config SIBYTE_CFE_CONSOLE
	bool "Use firmware console"
	depends on SIBYTE_SB1xxx_SOC
	help
	  Use the CFE API's console write routines during boot.  Other console
	  options (VT console, sb1250 duart console, etc.) should not be
	  configured.

config SIBYTE_BUS_WATCHER
	bool "Support for Bus Watcher statistics"
	depends on SIBYTE_SB1xxx_SOC && \
		(SIBYTE_BCM112X || SIBYTE_SB1250 || \
		 SIBYTE_BCM1x55 || SIBYTE_BCM1x80)
	help
	  Handle and keep statistics on the bus error interrupts (COR_ECC,
	  BAD_ECC, IO_BUS).

config SIBYTE_BW_TRACE
	bool "Capture bus trace before bus error"
	depends on SIBYTE_BUS_WATCHER
	help
	  Run a continuous bus trace, dumping the raw data as soon as
	  a ZBbus error is detected.  Cannot work if ZBbus profiling
	  is turned on, and also will interfere with JTAG-based trace
	  buffer activity.  Raw buffer data is dumped to console, and
	  must be processed off-line.

config SIBYTE_TBPROF
	tristate "Support for ZBbus profiling"
	depends on SIBYTE_HAS_ZBUS_PROFILING

config SIBYTE_HAS_ZBUS_PROFILING
	bool
Commit	Line	Data
38b18f72 RB	1	config SIBYTE_SB1250
38b18f72 RB	2	bool
217dd11e RB	3	select CEVT_SB1250
217dd11e RB	4	select CSRC_SB1250
38b18f72	5	select HW_HAS_PCI
67e38cf2	6	select IRQ_MIPS_CPU
ca6f5494	7	select SIBYTE_ENABLE_LDT_IF_PCI
d619f38f	8	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72	9	select SIBYTE_SB1xxx_SOC
e73ea273	10	select SYS_SUPPORTS_SMP
38b18f72 RB	11
	12	config SIBYTE_BCM1120
	13	bool
217dd11e RB	14	select CEVT_SB1250
217dd11e RB	15	select CSRC_SB1250
67e38cf2	16	select IRQ_MIPS_CPU
38b18f72	17	select SIBYTE_BCM112X
bb9b813b	18	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	19	select SIBYTE_SB1xxx_SOC
	20
	21	config SIBYTE_BCM1125
	22	bool
217dd11e RB	23	select CEVT_SB1250
217dd11e RB	24	select CSRC_SB1250
38b18f72	25	select HW_HAS_PCI
67e38cf2	26	select IRQ_MIPS_CPU
38b18f72	27	select SIBYTE_BCM112X
bb9b813b	28	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	29	select SIBYTE_SB1xxx_SOC
	30
	31	config SIBYTE_BCM1125H
	32	bool
217dd11e RB	33	select CEVT_SB1250
217dd11e RB	34	select CSRC_SB1250
38b18f72	35	select HW_HAS_PCI
67e38cf2	36	select IRQ_MIPS_CPU
38b18f72	37	select SIBYTE_BCM112X
ca6f5494	38	select SIBYTE_ENABLE_LDT_IF_PCI
bb9b813b	39	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	40	select SIBYTE_SB1xxx_SOC
	41
	42	config SIBYTE_BCM112X
	43	bool
217dd11e RB	44	select CEVT_SB1250
217dd11e RB	45	select CSRC_SB1250
67e38cf2	46	select IRQ_MIPS_CPU
38b18f72	47	select SIBYTE_SB1xxx_SOC
bb9b813b	48	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72	49
f137e463 AI	50	config SIBYTE_BCM1x80
f137e463 AI	51	bool
217dd11e RB	52	select CEVT_BCM1480
217dd11e RB	53	select CSRC_BCM1480
f137e463	54	select HW_HAS_PCI
67e38cf2	55	select IRQ_MIPS_CPU
d619f38f	56	select SIBYTE_HAS_ZBUS_PROFILING
f137e463	57	select SIBYTE_SB1xxx_SOC
e73ea273	58	select SYS_SUPPORTS_SMP
f137e463 AI	59
	60	config SIBYTE_BCM1x55
	61	bool
217dd11e RB	62	select CEVT_BCM1480
217dd11e RB	63	select CSRC_BCM1480
f137e463	64	select HW_HAS_PCI
67e38cf2	65	select IRQ_MIPS_CPU
f137e463	66	select SIBYTE_SB1xxx_SOC
bb9b813b	67	select SIBYTE_HAS_ZBUS_PROFILING
e73ea273	68	select SYS_SUPPORTS_SMP
f137e463	69
38b18f72 RB	70	config SIBYTE_SB1xxx_SOC
38b18f72 RB	71	bool
38b18f72	72	select DMA_COHERENT
67e38cf2	73	select IRQ_MIPS_CPU
38b18f72 RB	74	select SWAP_IO_SPACE
	75	select SYS_SUPPORTS_32BIT_KERNEL
	76	select SYS_SUPPORTS_64BIT_KERNEL
0e2794b0	77	select FW_CFE
05f94eeb	78	select SYS_HAS_EARLY_PRINTK
38b18f72 RB	79
	80	choice
	81	prompt "SiByte SOC Stepping"
	82	depends on SIBYTE_SB1xxx_SOC
	83
38b18f72 RB	84	config CPU_SB1_PASS_2_1250
	85	bool "1250 An"
	86	depends on SIBYTE_SB1250
	87	select CPU_SB1_PASS_2
	88	help
	89	Also called BCM1250 Pass 2
	90
	91	config CPU_SB1_PASS_2_2
	92	bool "1250 Bn"
	93	depends on SIBYTE_SB1250
	94	select CPU_HAS_PREFETCH
	95	help
	96	Also called BCM1250 Pass 2.2
	97
	98	config CPU_SB1_PASS_4
	99	bool "1250 Cn"
	100	depends on SIBYTE_SB1250
	101	select CPU_HAS_PREFETCH
	102	help
	103	Also called BCM1250 Pass 3
	104
	105	config CPU_SB1_PASS_2_112x
	106	bool "112x Hybrid"
	107	depends on SIBYTE_BCM112X
	108	select CPU_SB1_PASS_2
	109
	110	config CPU_SB1_PASS_3
	111	bool "112x An"
	112	depends on SIBYTE_BCM112X
	113	select CPU_HAS_PREFETCH
	114
	115	endchoice
	116
	117	config CPU_SB1_PASS_2
	118	bool
	119
	120	config SIBYTE_HAS_LDT
	121	bool
ca6f5494 RB	122
	123	config SIBYTE_ENABLE_LDT_IF_PCI
	124	bool
	125	select SIBYTE_HAS_LDT if PCI
38b18f72	126
77607635	127	config SB1_CEX_ALWAYS_FATAL
a4b5bd9a AI	128	bool "All cache exceptions considered fatal (no recovery attempted)"
	129	depends on SIBYTE_SB1xxx_SOC
	130
77607635	131	config SB1_CERR_STALL
a4b5bd9a AI	132	bool "Stall (rather than panic) on fatal cache error"
	133	depends on SIBYTE_SB1xxx_SOC
	134
38b18f72 RB	135	config SIBYTE_CFE_CONSOLE
38b18f72 RB	136	bool "Use firmware console"
05f94eeb	137	depends on SIBYTE_SB1xxx_SOC
38b18f72 RB	138	help
	139	Use the CFE API's console write routines during boot. Other console
	140	options (VT console, sb1250 duart console, etc.) should not be
	141	configured.
	142
38b18f72 RB	143	config SIBYTE_BUS_WATCHER
38b18f72 RB	144	bool "Support for Bus Watcher statistics"
6793f55c	145	depends on SIBYTE_SB1xxx_SOC && \
54292850 AR	146	(SIBYTE_BCM112X \|\| SIBYTE_SB1250 \|\| \
54292850 AR	147	SIBYTE_BCM1x55 \|\| SIBYTE_BCM1x80)
38b18f72 RB	148	help
	149	Handle and keep statistics on the bus error interrupts (COR_ECC,
	150	BAD_ECC, IO_BUS).
	151
	152	config SIBYTE_BW_TRACE
	153	bool "Capture bus trace before bus error"
	154	depends on SIBYTE_BUS_WATCHER
	155	help
	156	Run a continuous bus trace, dumping the raw data as soon as
	157	a ZBbus error is detected. Cannot work if ZBbus profiling
	158	is turned on, and also will interfere with JTAG-based trace
	159	buffer activity. Raw buffer data is dumped to console, and
	160	must be processed off-line.
	161
38b18f72	162	config SIBYTE_TBPROF
bb9b813b RB	163	tristate "Support for ZBbus profiling"
	164	depends on SIBYTE_HAS_ZBUS_PROFILING
	165
	166	config SIBYTE_HAS_ZBUS_PROFILING
	167	bool