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f137e463 AI |
1 | /* |
2 | * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
f137e463 AI |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/linkage.h> | |
21 | #include <linux/interrupt.h> | |
631330f5 | 22 | #include <linux/smp.h> |
f137e463 AI |
23 | #include <linux/spinlock.h> |
24 | #include <linux/mm.h> | |
f137e463 AI |
25 | #include <linux/kernel_stat.h> |
26 | ||
27 | #include <asm/errno.h> | |
937a8015 | 28 | #include <asm/irq_regs.h> |
f137e463 | 29 | #include <asm/signal.h> |
f137e463 AI |
30 | #include <asm/io.h> |
31 | ||
32 | #include <asm/sibyte/bcm1480_regs.h> | |
33 | #include <asm/sibyte/bcm1480_int.h> | |
34 | #include <asm/sibyte/bcm1480_scd.h> | |
35 | ||
36 | #include <asm/sibyte/sb1250_uart.h> | |
37 | #include <asm/sibyte/sb1250.h> | |
38 | ||
39 | /* | |
40 | * These are the routines that handle all the low level interrupt stuff. | |
41 | * Actions handled here are: initialization of the interrupt map, requesting of | |
42 | * interrupt lines by handlers, dispatching if interrupts to handlers, probing | |
43 | * for interrupt lines | |
44 | */ | |
45 | ||
f137e463 AI |
46 | #ifdef CONFIG_PCI |
47 | extern unsigned long ht_eoi_space; | |
48 | #endif | |
49 | ||
f137e463 AI |
50 | /* Store the CPU id (not the logical number) */ |
51 | int bcm1480_irq_owner[BCM1480_NR_IRQS]; | |
52 | ||
ed14bbb2 | 53 | static DEFINE_RAW_SPINLOCK(bcm1480_imr_lock); |
f137e463 AI |
54 | |
55 | void bcm1480_mask_irq(int cpu, int irq) | |
56 | { | |
fbd0ed37 RB |
57 | unsigned long flags, hl_spacing; |
58 | u64 cur_ints; | |
f137e463 | 59 | |
ed14bbb2 | 60 | raw_spin_lock_irqsave(&bcm1480_imr_lock, flags); |
f137e463 AI |
61 | hl_spacing = 0; |
62 | if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { | |
63 | hl_spacing = BCM1480_IMR_HL_SPACING; | |
64 | irq -= BCM1480_NR_IRQS_HALF; | |
65 | } | |
66 | cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); | |
67 | cur_ints |= (((u64) 1) << irq); | |
68 | ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); | |
ed14bbb2 | 69 | raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags); |
f137e463 AI |
70 | } |
71 | ||
72 | void bcm1480_unmask_irq(int cpu, int irq) | |
73 | { | |
fbd0ed37 RB |
74 | unsigned long flags, hl_spacing; |
75 | u64 cur_ints; | |
f137e463 | 76 | |
ed14bbb2 | 77 | raw_spin_lock_irqsave(&bcm1480_imr_lock, flags); |
f137e463 AI |
78 | hl_spacing = 0; |
79 | if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { | |
80 | hl_spacing = BCM1480_IMR_HL_SPACING; | |
81 | irq -= BCM1480_NR_IRQS_HALF; | |
82 | } | |
83 | cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); | |
84 | cur_ints &= ~(((u64) 1) << irq); | |
85 | ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); | |
ed14bbb2 | 86 | raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags); |
f137e463 AI |
87 | } |
88 | ||
89 | #ifdef CONFIG_SMP | |
d6d5d5c4 TG |
90 | static int bcm1480_set_affinity(struct irq_data *d, const struct cpumask *mask, |
91 | bool force) | |
f137e463 | 92 | { |
d6d5d5c4 | 93 | unsigned int irq_dirty, irq = d->irq; |
76e1daee | 94 | int i = 0, old_cpu, cpu, int_on, k; |
f137e463 | 95 | u64 cur_ints; |
f137e463 | 96 | unsigned long flags; |
f137e463 | 97 | |
0de26520 | 98 | i = cpumask_first(mask); |
f137e463 AI |
99 | |
100 | /* Convert logical CPU to physical CPU */ | |
101 | cpu = cpu_logical_map(i); | |
102 | ||
103 | /* Protect against other affinity changers and IMR manipulation */ | |
ed14bbb2 | 104 | raw_spin_lock_irqsave(&bcm1480_imr_lock, flags); |
f137e463 AI |
105 | |
106 | /* Swizzle each CPU's IMR (but leave the IP selection alone) */ | |
107 | old_cpu = bcm1480_irq_owner[irq]; | |
108 | irq_dirty = irq; | |
109 | if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { | |
110 | irq_dirty -= BCM1480_NR_IRQS_HALF; | |
111 | } | |
112 | ||
f137e463 AI |
113 | for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */ |
114 | cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); | |
115 | int_on = !(cur_ints & (((u64) 1) << irq_dirty)); | |
116 | if (int_on) { | |
117 | /* If it was on, mask it */ | |
118 | cur_ints |= (((u64) 1) << irq_dirty); | |
119 | ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); | |
120 | } | |
121 | bcm1480_irq_owner[irq] = cpu; | |
122 | if (int_on) { | |
123 | /* unmask for the new CPU */ | |
124 | cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); | |
125 | cur_ints &= ~(((u64) 1) << irq_dirty); | |
126 | ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); | |
127 | } | |
128 | } | |
ed14bbb2 | 129 | raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags); |
d5dedd45 YL |
130 | |
131 | return 0; | |
f137e463 AI |
132 | } |
133 | #endif | |
134 | ||
135 | ||
f137e463 AI |
136 | /*****************************************************************************/ |
137 | ||
d6d5d5c4 | 138 | static void disable_bcm1480_irq(struct irq_data *d) |
f137e463 | 139 | { |
d6d5d5c4 TG |
140 | unsigned int irq = d->irq; |
141 | ||
f137e463 AI |
142 | bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); |
143 | } | |
144 | ||
d6d5d5c4 | 145 | static void enable_bcm1480_irq(struct irq_data *d) |
f137e463 | 146 | { |
d6d5d5c4 TG |
147 | unsigned int irq = d->irq; |
148 | ||
f137e463 AI |
149 | bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); |
150 | } | |
151 | ||
152 | ||
d6d5d5c4 | 153 | static void ack_bcm1480_irq(struct irq_data *d) |
f137e463 | 154 | { |
d6d5d5c4 | 155 | unsigned int irq_dirty, irq = d->irq; |
f137e463 | 156 | u64 pending; |
76e1daee | 157 | int k; |
f137e463 AI |
158 | |
159 | /* | |
160 | * If the interrupt was an HT interrupt, now is the time to | |
161 | * clear it. NOTE: we assume the HT bridge was set up to | |
162 | * deliver the interrupts to all CPUs (which makes affinity | |
163 | * changing easier for us) | |
164 | */ | |
165 | irq_dirty = irq; | |
166 | if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { | |
167 | irq_dirty -= BCM1480_NR_IRQS_HALF; | |
168 | } | |
f137e463 AI |
169 | for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ |
170 | pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], | |
171 | R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); | |
172 | pending &= ((u64)1 << (irq_dirty)); | |
173 | if (pending) { | |
174 | #ifdef CONFIG_SMP | |
175 | int i; | |
176 | for (i=0; i<NR_CPUS; i++) { | |
177 | /* | |
178 | * Clear for all CPUs so an affinity switch | |
179 | * doesn't find an old status | |
180 | */ | |
181 | __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), | |
182 | R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); | |
183 | } | |
184 | #else | |
185 | __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); | |
186 | #endif | |
187 | ||
188 | /* | |
189 | * Generate EOI. For Pass 1 parts, EOI is a nop. For | |
190 | * Pass 2, the LDT world may be edge-triggered, but | |
191 | * this EOI shouldn't hurt. If they are | |
192 | * level-sensitive, the EOI is required. | |
193 | */ | |
194 | #ifdef CONFIG_PCI | |
195 | if (ht_eoi_space) | |
196 | *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; | |
197 | #endif | |
198 | } | |
199 | } | |
200 | bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); | |
201 | } | |
202 | ||
d6d5d5c4 TG |
203 | static struct irq_chip bcm1480_irq_type = { |
204 | .name = "BCM1480-IMR", | |
205 | .irq_mask_ack = ack_bcm1480_irq, | |
206 | .irq_mask = disable_bcm1480_irq, | |
207 | .irq_unmask = enable_bcm1480_irq, | |
208 | #ifdef CONFIG_SMP | |
209 | .irq_set_affinity = bcm1480_set_affinity | |
210 | #endif | |
211 | }; | |
f137e463 AI |
212 | |
213 | void __init init_bcm1480_irqs(void) | |
214 | { | |
215 | int i; | |
216 | ||
1603b5ac | 217 | for (i = 0; i < BCM1480_NR_IRQS; i++) { |
e4ec7989 TG |
218 | irq_set_chip_and_handler(i, &bcm1480_irq_type, |
219 | handle_level_irq); | |
1603b5ac | 220 | bcm1480_irq_owner[i] = 0; |
f137e463 AI |
221 | } |
222 | } | |
223 | ||
f137e463 AI |
224 | /* |
225 | * init_IRQ is called early in the boot sequence from init/main.c. It | |
226 | * is responsible for setting up the interrupt mapper and installing the | |
227 | * handler that will be responsible for dispatching interrupts to the | |
228 | * "right" place. | |
229 | */ | |
230 | /* | |
231 | * For now, map all interrupts to IP[2]. We could save | |
232 | * some cycles by parceling out system interrupts to different | |
233 | * IP lines, but keep it simple for bringup. We'll also direct | |
234 | * all interrupts to a single CPU; we should probably route | |
235 | * PCI and LDT to one cpu and everything else to the other | |
236 | * to balance the load a bit. | |
237 | * | |
238 | * On the second cpu, everything is set to IP5, which is | |
239 | * ignored, EXCEPT the mailbox interrupt. That one is | |
240 | * set to IP[2] so it is handled. This is needed so we | |
f77f13e2 | 241 | * can do cross-cpu function calls, as required by SMP |
f137e463 AI |
242 | */ |
243 | ||
244 | #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 | |
245 | #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 | |
246 | #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 | |
247 | #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3 | |
248 | #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4 | |
249 | ||
250 | void __init arch_init_irq(void) | |
251 | { | |
f137e463 AI |
252 | unsigned int i, cpu; |
253 | u64 tmp; | |
254 | unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | | |
255 | STATUSF_IP1 | STATUSF_IP0; | |
256 | ||
257 | /* Default everything to IP2 */ | |
258 | /* Start with _high registers which has no bit 0 interrupt source */ | |
259 | for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */ | |
260 | for (cpu = 0; cpu < 4; cpu++) { | |
261 | __raw_writeq(IMR_IP2_VAL, | |
262 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, | |
263 | R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3))); | |
264 | } | |
265 | } | |
266 | ||
267 | /* Now do _low registers */ | |
268 | for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) { | |
269 | for (cpu = 0; cpu < 4; cpu++) { | |
270 | __raw_writeq(IMR_IP2_VAL, | |
271 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, | |
272 | R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3))); | |
273 | } | |
274 | } | |
275 | ||
276 | init_bcm1480_irqs(); | |
277 | ||
278 | /* | |
279 | * Map the high 16 bits of mailbox_0 registers to IP[3], for | |
280 | * inter-cpu messages | |
281 | */ | |
282 | /* Was I1 */ | |
283 | for (cpu = 0; cpu < 4; cpu++) { | |
284 | __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + | |
285 | (K_BCM1480_INT_MBOX_0_0 << 3))); | |
70342287 | 286 | } |
f137e463 AI |
287 | |
288 | ||
70342287 | 289 | /* Clear the mailboxes. The firmware may leave them dirty */ |
f137e463 AI |
290 | for (cpu = 0; cpu < 4; cpu++) { |
291 | __raw_writeq(0xffffffffffffffffULL, | |
292 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); | |
293 | __raw_writeq(0xffffffffffffffffULL, | |
294 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); | |
295 | } | |
296 | ||
297 | ||
298 | /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */ | |
299 | tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0)); | |
300 | for (cpu = 0; cpu < 4; cpu++) { | |
301 | __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); | |
302 | } | |
303 | tmp = ~((u64) 0); | |
304 | for (cpu = 0; cpu < 4; cpu++) { | |
305 | __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); | |
306 | } | |
307 | ||
f137e463 AI |
308 | /* |
309 | * Note that the timer interrupts are also mapped, but this is | |
70342287 | 310 | * done in bcm1480_time_init(). Also, the profiling driver |
f137e463 AI |
311 | * does its own management of IP7. |
312 | */ | |
313 | ||
f137e463 AI |
314 | /* Enable necessary IPs, disable the rest */ |
315 | change_c0_status(ST0_IM, imask); | |
f137e463 AI |
316 | } |
317 | ||
937a8015 | 318 | extern void bcm1480_mailbox_interrupt(void); |
e4ac58af | 319 | |
d0453365 RB |
320 | static inline void dispatch_ip2(void) |
321 | { | |
322 | unsigned long long mask_h, mask_l; | |
323 | unsigned int cpu = smp_processor_id(); | |
324 | unsigned long base; | |
325 | ||
326 | /* | |
327 | * Default...we've hit an IP[2] interrupt, which means we've got to | |
70342287 | 328 | * check the 1480 interrupt registers to figure out what to do. Need |
d0453365 RB |
329 | * to detect which CPU we're on, now that smp_affinity is supported. |
330 | */ | |
331 | base = A_BCM1480_IMR_MAPPER(cpu); | |
332 | mask_h = __raw_readq( | |
333 | IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H)); | |
334 | mask_l = __raw_readq( | |
335 | IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L)); | |
336 | ||
337 | if (mask_h) { | |
338 | if (mask_h ^ 1) | |
339 | do_IRQ(fls64(mask_h) - 1); | |
340 | else if (mask_l) | |
341 | do_IRQ(63 + fls64(mask_l)); | |
342 | } | |
343 | } | |
344 | ||
937a8015 | 345 | asmlinkage void plat_irq_dispatch(void) |
e4ac58af | 346 | { |
a8401fa5 | 347 | unsigned int cpu = smp_processor_id(); |
e4ac58af RB |
348 | unsigned int pending; |
349 | ||
350 | #ifdef CONFIG_SIBYTE_BCM1480_PROF | |
351 | /* Set compare to count to silence count/compare timer interrupts */ | |
352 | write_c0_compare(read_c0_count()); | |
353 | #endif | |
354 | ||
34c2dd01 | 355 | pending = read_c0_cause() & read_c0_status(); |
e4ac58af RB |
356 | |
357 | #ifdef CONFIG_SIBYTE_BCM1480_PROF | |
358 | if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ | |
937a8015 | 359 | sbprof_cpu_intr(); |
6e61e85b | 360 | else |
e4ac58af RB |
361 | #endif |
362 | ||
d0453365 | 363 | if (pending & CAUSEF_IP4) |
a8401fa5 | 364 | do_IRQ(K_BCM1480_INT_TIMER_0 + cpu); |
e4ac58af | 365 | #ifdef CONFIG_SMP |
6e61e85b | 366 | else if (pending & CAUSEF_IP3) |
937a8015 | 367 | bcm1480_mailbox_interrupt(); |
e4ac58af RB |
368 | #endif |
369 | ||
d0453365 RB |
370 | else if (pending & CAUSEF_IP2) |
371 | dispatch_ip2(); | |
e4ac58af | 372 | } |