[deliverable/linux.git] / arch / mips / sni / pcimt.c

/*
 * PCIMT specific code
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>

#include <asm/mc146818-time.h>
#include <asm/sni.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/irq_cpu.h>

#define cacheconf (*(volatile unsigned int *)PCIMT_CACHECONF)
#define invspace (*(volatile unsigned int *)PCIMT_INVSPACE)

static void __init sni_pcimt_sc_init(void)
{
	unsigned int scsiz, sc_size;

	scsiz = cacheconf & 7;
	if (scsiz == 0) {
		printk("Second level cache is deactived.\n");
		return;
	}
	if (scsiz >= 6) {
		printk("Invalid second level cache size configured, "
		       "deactivating second level cache.\n");
		cacheconf = 0;
		return;
	}

	sc_size = 128 << scsiz;
	printk("%dkb second level cache detected, deactivating.\n", sc_size);
	cacheconf = 0;
}


/*
 * A bit more gossip about the iron we're running on ...
 */
static inline void sni_pcimt_detect(void)
{
	char boardtype[80];
	unsigned char csmsr;
	char *p = boardtype;
	unsigned int asic;

	csmsr = *(volatile unsigned char *)PCIMT_CSMSR;

	p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
	if ((csmsr & 0x80) == 0)
		p += sprintf(p, ", board revision %s",
		             (csmsr & 0x20) ? "D" : "C");
	asic = csmsr & 0x80;
	asic = (csmsr & 0x08) ? asic : !asic;
	p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
	printk("%s.\n", boardtype);
}

#define PORT(_base,_irq)				\
	{						\
		.iobase		= _base,		\
		.irq		= _irq,			\
		.uartclk	= 1843200,		\
		.iotype		= UPIO_PORT,		\
		.flags		= UPF_BOOT_AUTOCONF,	\
	}

static struct plat_serial8250_port pcimt_data[] = {
	PORT(0x3f8, 4),
	PORT(0x2f8, 3),
	{ },
};

static struct platform_device pcimt_serial8250_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= pcimt_data,
	},
};

static struct resource sni_io_resource = {
	.start	= 0x00000000UL,
	.end	= 0x03bfffffUL,
	.name	= "PCIMT IO MEM",
	.flags	= IORESOURCE_IO,
};

static struct resource pcimt_io_resources[] = {
	{
		.start	= 0x00,
		.end	= 0x1f,
		.name	= "dma1",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x40,
		.end	= 0x5f,
		.name	= "timer",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x60,
		.end	= 0x6f,
		.name	= "keyboard",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x80,
		.end	= 0x8f,
		.name	= "dma page reg",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0xc0,
		.end	= 0xdf,
		.name	= "dma2",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0xcfc,
		.end	= 0xcff,
		.name	= "PCI config data",
		.flags	= IORESOURCE_BUSY
	}
};

static struct resource sni_mem_resource = {
	.start	= 0x18000000UL,
	.end	= 0x1fbfffffUL,
	.name	= "PCIMT PCI MEM",
	.flags	= IORESOURCE_MEM
};

static void __init sni_pcimt_resource_init(void)
{
	int i;

	/* request I/O space for devices used on all i[345]86 PCs */
	for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
		request_resource(&sni_io_resource, pcimt_io_resources + i);
}

extern struct pci_ops sni_pcimt_ops;

static struct pci_controller sni_controller = {
	.pci_ops	= &sni_pcimt_ops,
	.mem_resource	= &sni_mem_resource,
	.mem_offset	= 0x00000000UL,
	.io_resource	= &sni_io_resource,
	.io_offset	= 0x00000000UL,
	.io_map_base    = SNI_PORT_BASE
};

static void enable_pcimt_irq(unsigned int irq)
{
	unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);

	*(volatile u8 *) PCIMT_IRQSEL |= mask;
}

void disable_pcimt_irq(unsigned int irq)
{
	unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));

	*(volatile u8 *) PCIMT_IRQSEL &= mask;
}

static void end_pcimt_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_pcimt_irq(irq);
}

static struct irq_chip pcimt_irq_type = {
	.typename = "PCIMT",
	.ack = disable_pcimt_irq,
	.mask = disable_pcimt_irq,
	.mask_ack = disable_pcimt_irq,
	.unmask = enable_pcimt_irq,
	.end = end_pcimt_irq,
};

/*
 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
 * button interrupts.  Later ...
 */
static void pcimt_hwint0(void)
{
	panic("Received int0 but no handler yet ...");
}

/*
 * hwint 1 deals with EISA and SCSI interrupts,
 *
 * The EISA_INT bit in CSITPEND is high active, all others are low active.
 */
static void pcimt_hwint1(void)
{
	u8 pend = *(volatile char *)PCIMT_CSITPEND;
	unsigned long flags;

	if (pend & IT_EISA) {
		int irq;
		/*
		 * Note: ASIC PCI's builtin interrupt achknowledge feature is
		 * broken.  Using it may result in loss of some or all i8259
		 * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
		 */
		irq = i8259_irq();
		if (unlikely(irq < 0))
			return;

		do_IRQ(irq);
	}

	if (!(pend & IT_SCSI)) {
		flags = read_c0_status();
		clear_c0_status(ST0_IM);
		do_IRQ(PCIMT_IRQ_SCSI);
		write_c0_status(flags);
	}
}

/*
 * hwint 3 should deal with the PCI A - D interrupts,
 */
static void pcimt_hwint3(void)
{
	u8 pend = *(volatile char *)PCIMT_CSITPEND;
	int irq;

	pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
	pend ^= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
	clear_c0_status(IE_IRQ3);
	irq = PCIMT_IRQ_INT2 + ffs(pend) - 1;
	do_IRQ(irq);
	set_c0_status(IE_IRQ3);
}

static void sni_pcimt_hwint(void)
{
	u32 pending = read_c0_cause() & read_c0_status();

	if (pending & C_IRQ5)
		do_IRQ (MIPS_CPU_IRQ_BASE + 7);
	else if (pending & C_IRQ4)
		do_IRQ (MIPS_CPU_IRQ_BASE + 6);
	else if (pending & C_IRQ3)
		pcimt_hwint3();
	else if (pending & C_IRQ1)
		pcimt_hwint1();
	else if (pending & C_IRQ0) {
		pcimt_hwint0();
	}
}

void __init sni_pcimt_irq_init(void)
{
	int i;

	*(volatile u8 *) PCIMT_IRQSEL = IT_ETH | IT_EISA;
	mips_cpu_irq_init();
	/* Actually we've got more interrupts to handle ...  */
	for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
		set_irq_chip(i, &pcimt_irq_type);
	sni_hwint = sni_pcimt_hwint;
	change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
}

void sni_pcimt_init(void)
{
	sni_pcimt_detect();
	sni_pcimt_sc_init();
	rtc_mips_get_time = mc146818_get_cmos_time;
	rtc_mips_set_time = mc146818_set_rtc_mmss;
	board_time_init = sni_cpu_time_init;
	ioport_resource.end = sni_io_resource.end;
#ifdef CONFIG_PCI
	PCIBIOS_MIN_IO = 0x9000;
	register_pci_controller(&sni_controller);
#endif
	sni_pcimt_resource_init();
}

static int __init snirm_pcimt_setup_devinit(void)
{
	switch (sni_brd_type) {
	case SNI_BRD_PCI_MTOWER:
	case SNI_BRD_PCI_DESKTOP:
	case SNI_BRD_PCI_MTOWER_CPLUS:
	        platform_device_register(&pcimt_serial8250_device);
	        break;
	}

	return 0;
}

device_initcall(snirm_pcimt_setup_devinit);
Commit	Line	Data
c066a32a TB	1	/*
	2	* PCIMT specific code
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org)
	9	* Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/pci.h>
	15	#include <linux/serial_8250.h>
	16
	17	#include <asm/mc146818-time.h>
	18	#include <asm/sni.h>
	19	#include <asm/time.h>
	20	#include <asm/i8259.h>
	21	#include <asm/irq_cpu.h>
	22
	23	#define cacheconf ((volatile unsigned int )PCIMT_CACHECONF)
	24	#define invspace ((volatile unsigned int )PCIMT_INVSPACE)
	25
	26	static void __init sni_pcimt_sc_init(void)
	27	{
	28	unsigned int scsiz, sc_size;
	29
	30	scsiz = cacheconf & 7;
	31	if (scsiz == 0) {
	32	printk("Second level cache is deactived.\n");
	33	return;
	34	}
	35	if (scsiz >= 6) {
	36	printk("Invalid second level cache size configured, "
	37	"deactivating second level cache.\n");
	38	cacheconf = 0;
	39	return;
	40	}
	41
	42	sc_size = 128 << scsiz;
	43	printk("%dkb second level cache detected, deactivating.\n", sc_size);
	44	cacheconf = 0;
	45	}
	46
	47
	48	/*
	49	* A bit more gossip about the iron we're running on ...
	50	*/
	51	static inline void sni_pcimt_detect(void)
	52	{
	53	char boardtype[80];
	54	unsigned char csmsr;
	55	char *p = boardtype;
	56	unsigned int asic;
	57
	58	csmsr = (volatile unsigned char )PCIMT_CSMSR;
	59
	60	p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
	61	if ((csmsr & 0x80) == 0)
	62	p += sprintf(p, ", board revision %s",
	63	(csmsr & 0x20) ? "D" : "C");
	64	asic = csmsr & 0x80;
65	asic = (csmsr & 0x08) ? asic : !asic;
66	p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
67	printk("%s.\n", boardtype);
68	}
69
70	#define PORT(_base,_irq) \
71	{ \
72	.iobase = _base, \
73	.irq = _irq, \
74	.uartclk = 1843200, \
75	.iotype = UPIO_PORT, \
76	.flags = UPF_BOOT_AUTOCONF, \
77	}
78
79	static struct plat_serial8250_port pcimt_data[] = {
80	PORT(0x3f8, 4),
81	PORT(0x2f8, 3),
82	{ },
83	};
84
85	static struct platform_device pcimt_serial8250_device = {
86	.name = "serial8250",
87	.id = PLAT8250_DEV_PLATFORM,
88	.dev = {
89	.platform_data = pcimt_data,
90	},
91	};
92
93	static struct resource sni_io_resource = {
bea77175	94	.start = 0x00000000UL,
c066a32a TB	95	.end = 0x03bfffffUL,
	96	.name = "PCIMT IO MEM",
	97	.flags = IORESOURCE_IO,
	98	};
	99
	100	static struct resource pcimt_io_resources[] = {
	101	{
	102	.start = 0x00,
	103	.end = 0x1f,
	104	.name = "dma1",
	105	.flags = IORESOURCE_BUSY
	106	}, {
	107	.start = 0x40,
	108	.end = 0x5f,
	109	.name = "timer",
	110	.flags = IORESOURCE_BUSY
	111	}, {
	112	.start = 0x60,
	113	.end = 0x6f,
	114	.name = "keyboard",
	115	.flags = IORESOURCE_BUSY
	116	}, {
	117	.start = 0x80,
	118	.end = 0x8f,
	119	.name = "dma page reg",
	120	.flags = IORESOURCE_BUSY
	121	}, {
	122	.start = 0xc0,
	123	.end = 0xdf,
	124	.name = "dma2",
	125	.flags = IORESOURCE_BUSY
	126	}, {
	127	.start = 0xcfc,
	128	.end = 0xcff,
	129	.name = "PCI config data",
	130	.flags = IORESOURCE_BUSY
	131	}
	132	};
	133
	134	static struct resource sni_mem_resource = {
bea77175 TB	135	.start = 0x18000000UL,
bea77175 TB	136	.end = 0x1fbfffffUL,
c066a32a TB	137	.name = "PCIMT PCI MEM",
	138	.flags = IORESOURCE_MEM
	139	};
	140
c066a32a TB	141	static void __init sni_pcimt_resource_init(void)
	142	{
	143	int i;
	144
	145	/* request I/O space for devices used on all i[345]86 PCs */
	146	for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
bea77175	147	request_resource(&sni_io_resource, pcimt_io_resources + i);
c066a32a TB	148	}
	149
	150	extern struct pci_ops sni_pcimt_ops;
	151
	152	static struct pci_controller sni_controller = {
	153	.pci_ops = &sni_pcimt_ops,
	154	.mem_resource = &sni_mem_resource,
bea77175	155	.mem_offset = 0x00000000UL,
c066a32a	156	.io_resource = &sni_io_resource,
bea77175 TB	157	.io_offset = 0x00000000UL,
bea77175 TB	158	.io_map_base = SNI_PORT_BASE
c066a32a TB	159	};
	160
	161	static void enable_pcimt_irq(unsigned int irq)
	162	{
	163	unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
	164
	165	(volatile u8 ) PCIMT_IRQSEL \|= mask;
	166	}
	167
	168	void disable_pcimt_irq(unsigned int irq)
	169	{
	170	unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
	171
	172	(volatile u8 ) PCIMT_IRQSEL &= mask;
	173	}
	174
	175	static void end_pcimt_irq(unsigned int irq)
	176	{
	177	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	178	enable_pcimt_irq(irq);
	179	}
	180
	181	static struct irq_chip pcimt_irq_type = {
	182	.typename = "PCIMT",
	183	.ack = disable_pcimt_irq,
	184	.mask = disable_pcimt_irq,
	185	.mask_ack = disable_pcimt_irq,
	186	.unmask = enable_pcimt_irq,
	187	.end = end_pcimt_irq,
	188	};
	189
	190	/*
	191	* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
	192	* button interrupts. Later ...
	193	*/
	194	static void pcimt_hwint0(void)
	195	{
	196	panic("Received int0 but no handler yet ...");
	197	}
	198
	199	/*
	200	* hwint 1 deals with EISA and SCSI interrupts,
	201	*
	202	* The EISA_INT bit in CSITPEND is high active, all others are low active.
	203	*/
	204	static void pcimt_hwint1(void)
	205	{
	206	u8 pend = (volatile char )PCIMT_CSITPEND;
	207	unsigned long flags;
	208
	209	if (pend & IT_EISA) {
	210	int irq;
	211	/*
	212	* Note: ASIC PCI's builtin interrupt achknowledge feature is
	213	* broken. Using it may result in loss of some or all i8259
	214	* interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
	215	*/
	216	irq = i8259_irq();
	217	if (unlikely(irq < 0))
	218	return;
	219
	220	do_IRQ(irq);
	221	}
	222
223	if (!(pend & IT_SCSI)) {
224	flags = read_c0_status();
225	clear_c0_status(ST0_IM);
226	do_IRQ(PCIMT_IRQ_SCSI);
227	write_c0_status(flags);
228	}
229	}
230
231	/*
232	* hwint 3 should deal with the PCI A - D interrupts,
233	*/
234	static void pcimt_hwint3(void)
235	{
236	u8 pend = (volatile char )PCIMT_CSITPEND;
237	int irq;
238
239	pend &= (IT_INTA \| IT_INTB \| IT_INTC \| IT_INTD);
240	pend ^= (IT_INTA \| IT_INTB \| IT_INTC \| IT_INTD);
241	clear_c0_status(IE_IRQ3);
242	irq = PCIMT_IRQ_INT2 + ffs(pend) - 1;
243	do_IRQ(irq);
244	set_c0_status(IE_IRQ3);
245	}
246
247	static void sni_pcimt_hwint(void)
248	{
119537c0	249	u32 pending = read_c0_cause() & read_c0_status();
c066a32a TB	250
c066a32a TB	251	if (pending & C_IRQ5)
f13cc01d	252	do_IRQ (MIPS_CPU_IRQ_BASE + 7);
c066a32a	253	else if (pending & C_IRQ4)
f13cc01d	254	do_IRQ (MIPS_CPU_IRQ_BASE + 6);
c066a32a TB	255	else if (pending & C_IRQ3)
	256	pcimt_hwint3();
	257	else if (pending & C_IRQ1)
	258	pcimt_hwint1();
	259	else if (pending & C_IRQ0) {
	260	pcimt_hwint0();
	261	}
	262	}
	263
	264	void __init sni_pcimt_irq_init(void)
	265	{
	266	int i;
	267
	268	(volatile u8 ) PCIMT_IRQSEL = IT_ETH \| IT_EISA;
	269	mips_cpu_irq_init();
	270	/* Actually we've got more interrupts to handle ... */
	271	for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
	272	set_irq_chip(i, &pcimt_irq_type);
	273	sni_hwint = sni_pcimt_hwint;
	274	change_c0_status(ST0_IM, IE_IRQ1\|IE_IRQ3);
	275	}
	276
	277	void sni_pcimt_init(void)
	278	{
c066a32a TB	279	sni_pcimt_detect();
	280	sni_pcimt_sc_init();
	281	rtc_mips_get_time = mc146818_get_cmos_time;
	282	rtc_mips_set_time = mc146818_set_rtc_mmss;
	283	board_time_init = sni_cpu_time_init;
bea77175	284	ioport_resource.end = sni_io_resource.end;
c066a32a	285	#ifdef CONFIG_PCI
bea77175	286	PCIBIOS_MIN_IO = 0x9000;
c066a32a TB	287	register_pci_controller(&sni_controller);
c066a32a TB	288	#endif
bea77175	289	sni_pcimt_resource_init();
c066a32a TB	290	}
	291
	292	static int __init snirm_pcimt_setup_devinit(void)
	293	{
	294	switch (sni_brd_type) {
	295	case SNI_BRD_PCI_MTOWER:
	296	case SNI_BRD_PCI_DESKTOP:
	297	case SNI_BRD_PCI_MTOWER_CPLUS:
	298	platform_device_register(&pcimt_serial8250_device);
	299	break;
	300	}
	301
	302	return 0;
	303	}
	304
	305	device_initcall(snirm_pcimt_setup_devinit);