[deliverable/linux.git] / arch / mips / sni / time.c

#include <linux/types.h>
#include <linux/i8253.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/smp.h>
#include <linux/time.h>
#include <linux/clockchips.h>

#include <asm/sni.h>
#include <asm/time.h>
#include <asm-generic/rtc.h>

#define SNI_CLOCK_TICK_RATE     3686400
#define SNI_COUNTER2_DIV        64
#define SNI_COUNTER0_DIV        ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)

static void a20r_set_mode(enum clock_event_mode mode,
                          struct clock_event_device *evt)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		*(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34;
		wmb();
		*(volatile u8 *)(A20R_PT_CLOCK_BASE +  0) = SNI_COUNTER0_DIV;
		wmb();
		*(volatile u8 *)(A20R_PT_CLOCK_BASE +  0) = SNI_COUNTER0_DIV >> 8;
		wmb();

		*(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4;
		wmb();
		*(volatile u8 *)(A20R_PT_CLOCK_BASE +  8) = SNI_COUNTER2_DIV;
		wmb();
		*(volatile u8 *)(A20R_PT_CLOCK_BASE +  8) = SNI_COUNTER2_DIV >> 8;
		wmb();

                break;
        case CLOCK_EVT_MODE_ONESHOT:
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
                break;
        case CLOCK_EVT_MODE_RESUME:
                break;
        }
}

static struct clock_event_device a20r_clockevent_device = {
	.name		= "a20r-timer",
	.features	= CLOCK_EVT_FEAT_PERIODIC,

	/* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */

	.rating		= 300,
	.irq		= SNI_A20R_IRQ_TIMER,
	.set_mode	= a20r_set_mode,
};

static irqreturn_t a20r_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *cd = dev_id;

	*(volatile u8 *)A20R_PT_TIM0_ACK = 0;
	wmb();

	cd->event_handler(cd);

	return IRQ_HANDLED;
}

static struct irqaction a20r_irqaction = {
	.handler	= a20r_interrupt,
	.flags		= IRQF_PERCPU | IRQF_TIMER,
	.name		= "a20r-timer",
};

/*
 * a20r platform uses 2 counters to divide the input frequency.
 * Counter 2 output is connected to Counter 0 & 1 input.
 */
static void __init sni_a20r_timer_setup(void)
{
	struct clock_event_device *cd = &a20r_clockevent_device;
	struct irqaction *action = &a20r_irqaction;
	unsigned int cpu = smp_processor_id();

	cd->cpumask             = cpumask_of(cpu);
	clockevents_register_device(cd);
	action->dev_id = cd;
	setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
}

#define SNI_8254_TICK_RATE        1193182UL

#define SNI_8254_TCSAMP_COUNTER   ((SNI_8254_TICK_RATE / HZ) + 255)

static __init unsigned long dosample(void)
{
	u32 ct0, ct1;
	volatile u8 msb;

	/* Start the counter. */
	outb_p(0x34, 0x43);
	outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
	outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);

	/* Get initial counter invariant */
	ct0 = read_c0_count();

	/* Latch and spin until top byte of counter0 is zero */
	do {
		outb(0x00, 0x43);
		(void) inb(0x40);
		msb = inb(0x40);
		ct1 = read_c0_count();
	} while (msb);

	/* Stop the counter. */
	outb(0x38, 0x43);
	/*
	 * Return the difference, this is how far the r4k counter increments
	 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
	 * clock (= 1000000 / HZ / 2).
	 */
	/*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
	return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
}

/*
 * Here we need to calibrate the cycle counter to at least be close.
 */
void __init plat_time_init(void)
{
	unsigned long r4k_ticks[3];
	unsigned long r4k_tick;

	/*
	 * Figure out the r4k offset, the algorithm is very simple and works in
	 * _all_ cases as long as the 8254 counter register itself works ok (as
	 * an interrupt driving timer it does not because of bug, this is why
	 * we are using the onchip r4k counter/compare register to serve this
	 * purpose, but for r4k_offset calculation it will work ok for us).
	 * There are other very complicated ways of performing this calculation
	 * but this one works just fine so I am not going to futz around. ;-)
	 */
	printk(KERN_INFO "Calibrating system timer... ");
	dosample();	/* Prime cache. */
	dosample();	/* Prime cache. */
	/* Zero is NOT an option. */
	do {
		r4k_ticks[0] = dosample();
	} while (!r4k_ticks[0]);
	do {
		r4k_ticks[1] = dosample();
	} while (!r4k_ticks[1]);

	if (r4k_ticks[0] != r4k_ticks[1]) {
		printk("warning: timer counts differ, retrying... ");
		r4k_ticks[2] = dosample();
		if (r4k_ticks[2] == r4k_ticks[0]
		    || r4k_ticks[2] == r4k_ticks[1])
			r4k_tick = r4k_ticks[2];
		else {
			printk("disagreement, using average... ");
			r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
				   + r4k_ticks[2]) / 3;
		}
	} else
		r4k_tick = r4k_ticks[0];

	printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
		(int) (r4k_tick / (500000 / HZ)),
		(int) (r4k_tick % (500000 / HZ)));

	mips_hpt_frequency = r4k_tick * HZ;

	switch (sni_brd_type) {
	case SNI_BRD_10:
	case SNI_BRD_10NEW:
	case SNI_BRD_TOWER_OASIC:
	case SNI_BRD_MINITOWER:
		sni_a20r_timer_setup();
		break;
	}
	setup_pit_timer();
}

void read_persistent_clock(struct timespec *ts)
{
	ts->tv_sec = -1;
	ts->tv_nsec = 0;
}
Commit	Line	Data
c066a32a	1	#include <linux/types.h>
334955ef	2	#include <linux/i8253.h>
c066a32a	3	#include <linux/interrupt.h>
ca4d3e67	4	#include <linux/irq.h>
631330f5	5	#include <linux/smp.h>
c066a32a	6	#include <linux/time.h>
c9294022	7	#include <linux/clockchips.h>
c066a32a TB	8
	9	#include <asm/sni.h>
	10	#include <asm/time.h>
4b550488	11	#include <asm-generic/rtc.h>
c066a32a TB	12
	13	#define SNI_CLOCK_TICK_RATE 3686400
	14	#define SNI_COUNTER2_DIV 64
	15	#define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
	16
84953b39 RB	17	static void a20r_set_mode(enum clock_event_mode mode,
84953b39 RB	18	struct clock_event_device *evt)
c066a32a	19	{
84953b39 RB	20	switch (mode) {
	21	case CLOCK_EVT_MODE_PERIODIC:
	22	(volatile u8 )(A20R_PT_CLOCK_BASE + 12) = 0x34;
	23	wmb();
	24	(volatile u8 )(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV;
	25	wmb();
	26	(volatile u8 )(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8;
	27	wmb();
	28
	29	(volatile u8 )(A20R_PT_CLOCK_BASE + 12) = 0xb4;
	30	wmb();
	31	(volatile u8 )(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV;
	32	wmb();
	33	(volatile u8 )(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8;
	34	wmb();
	35
	36	break;
	37	case CLOCK_EVT_MODE_ONESHOT:
	38	case CLOCK_EVT_MODE_UNUSED:
	39	case CLOCK_EVT_MODE_SHUTDOWN:
	40	break;
	41	case CLOCK_EVT_MODE_RESUME:
	42	break;
	43	}
c066a32a TB	44	}
c066a32a TB	45
84953b39 RB	46	static struct clock_event_device a20r_clockevent_device = {
	47	.name = "a20r-timer",
	48	.features = CLOCK_EVT_FEAT_PERIODIC,
	49
	50	/* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
	51
	52	.rating = 300,
	53	.irq = SNI_A20R_IRQ_TIMER,
	54	.set_mode = a20r_set_mode,
	55	};
	56
	57	static irqreturn_t a20r_interrupt(int irq, void *dev_id)
	58	{
	59	struct clock_event_device *cd = dev_id;
	60
	61	(volatile u8 )A20R_PT_TIM0_ACK = 0;
	62	wmb();
	63
	64	cd->event_handler(cd);
	65
	66	return IRQ_HANDLED;
	67	}
	68
	69	static struct irqaction a20r_irqaction = {
	70	.handler = a20r_interrupt,
8b5690f8	71	.flags = IRQF_PERCPU \| IRQF_TIMER,
84953b39 RB	72	.name = "a20r-timer",
	73	};
	74
c066a32a TB	75	/*
	76	* a20r platform uses 2 counters to divide the input frequency.
	77	* Counter 2 output is connected to Counter 0 & 1 input.
	78	*/
84953b39	79	static void __init sni_a20r_timer_setup(void)
c066a32a	80	{
84953b39 RB	81	struct clock_event_device *cd = &a20r_clockevent_device;
	82	struct irqaction *action = &a20r_irqaction;
	83	unsigned int cpu = smp_processor_id();
c066a32a	84
320ab2b0	85	cd->cpumask = cpumask_of(cpu);
c9294022	86	clockevents_register_device(cd);
84953b39 RB	87	action->dev_id = cd;
84953b39 RB	88	setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
c066a32a TB	89	}
	90
	91	#define SNI_8254_TICK_RATE 1193182UL
	92
	93	#define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255)
	94
	95	static __init unsigned long dosample(void)
	96	{
	97	u32 ct0, ct1;
11b9d0ec	98	volatile u8 msb;
c066a32a TB	99
c066a32a TB	100	/* Start the counter. */
49a89efb	101	outb_p(0x34, 0x43);
c066a32a	102	outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
49a89efb	103	outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
c066a32a TB	104
	105	/* Get initial counter invariant */
	106	ct0 = read_c0_count();
	107
	108	/* Latch and spin until top byte of counter0 is zero */
	109	do {
49a89efb	110	outb(0x00, 0x43);
11b9d0ec	111	(void) inb(0x40);
49a89efb	112	msb = inb(0x40);
c066a32a TB	113	ct1 = read_c0_count();
	114	} while (msb);
	115
	116	/* Stop the counter. */
49a89efb	117	outb(0x38, 0x43);
c066a32a TB	118	/*
	119	* Return the difference, this is how far the r4k counter increments
	120	* for every 1/HZ seconds. We round off the nearest 1 MHz of master
	121	* clock (= 1000000 / HZ / 2).
	122	*/
	123	/return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) (500000/HZ);*/
	124	return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
	125	}
	126
	127	/*
	128	* Here we need to calibrate the cycle counter to at least be close.
	129	*/
4b550488	130	void __init plat_time_init(void)
c066a32a TB	131	{
	132	unsigned long r4k_ticks[3];
	133	unsigned long r4k_tick;
	134
	135	/*
	136	* Figure out the r4k offset, the algorithm is very simple and works in
	137	* _all_ cases as long as the 8254 counter register itself works ok (as
	138	* an interrupt driving timer it does not because of bug, this is why
	139	* we are using the onchip r4k counter/compare register to serve this
	140	* purpose, but for r4k_offset calculation it will work ok for us).
	141	* There are other very complicated ways of performing this calculation
	142	* but this one works just fine so I am not going to futz around. ;-)
	143	*/
	144	printk(KERN_INFO "Calibrating system timer... ");
	145	dosample(); /* Prime cache. */
	146	dosample(); /* Prime cache. */
	147	/* Zero is NOT an option. */
	148	do {
	149	r4k_ticks[0] = dosample();
	150	} while (!r4k_ticks[0]);
	151	do {
	152	r4k_ticks[1] = dosample();
	153	} while (!r4k_ticks[1]);
	154
	155	if (r4k_ticks[0] != r4k_ticks[1]) {
	156	printk("warning: timer counts differ, retrying... ");
	157	r4k_ticks[2] = dosample();
	158	if (r4k_ticks[2] == r4k_ticks[0]
	159	\|\| r4k_ticks[2] == r4k_ticks[1])
	160	r4k_tick = r4k_ticks[2];
	161	else {
	162	printk("disagreement, using average... ");
	163	r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
	164	+ r4k_ticks[2]) / 3;
	165	}
	166	} else
	167	r4k_tick = r4k_ticks[0];
	168
	169	printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
	170	(int) (r4k_tick / (500000 / HZ)),
	171	(int) (r4k_tick % (500000 / HZ)));
	172
	173	mips_hpt_frequency = r4k_tick * HZ;
d865bea4	174
c066a32a TB	175	switch (sni_brd_type) {
	176	case SNI_BRD_10:
	177	case SNI_BRD_10NEW:
	178	case SNI_BRD_TOWER_OASIC:
	179	case SNI_BRD_MINITOWER:
84953b39 RB	180	sni_a20r_timer_setup();
84953b39 RB	181	break;
c066a32a	182	}
231a35d3	183	setup_pit_timer();
c066a32a	184	}
4b550488	185
d4f587c6	186	void read_persistent_clock(struct timespec *ts)
4b550488	187	{
d4f587c6 MS	188	ts->tv_sec = -1;
d4f587c6 MS	189	ts->tv_nsec = 0;
4b550488	190	}