[deliverable/linux.git] / arch / parisc / kernel / cache.c

/* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1999 Helge Deller (07-13-1999)
 * Copyright (C) 1999 SuSE GmbH Nuernberg
 * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
 *
 * Cache and TLB management
 *
 */
 
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/pagemap.h>

#include <asm/pdc.h>
#include <asm/cache.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/system.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/sections.h>

int split_tlb __read_mostly;
int dcache_stride __read_mostly;
int icache_stride __read_mostly;
EXPORT_SYMBOL(dcache_stride);


#if defined(CONFIG_SMP)
/* On some machines (e.g. ones with the Merced bus), there can be
 * only a single PxTLB broadcast at a time; this must be guaranteed
 * by software.  We put a spinlock around all TLB flushes  to
 * ensure this.
 */
DEFINE_SPINLOCK(pa_tlb_lock);
EXPORT_SYMBOL(pa_tlb_lock);
#endif

struct pdc_cache_info cache_info __read_mostly;
#ifndef CONFIG_PA20
static struct pdc_btlb_info btlb_info __read_mostly;
#endif

#ifdef CONFIG_SMP
void
flush_data_cache(void)
{
	on_each_cpu(flush_data_cache_local, NULL, 1, 1);
}
void 
flush_instruction_cache(void)
{
	on_each_cpu(flush_instruction_cache_local, NULL, 1, 1);
}
#endif

void
flush_cache_all_local(void)
{
	flush_instruction_cache_local(NULL);
	flush_data_cache_local(NULL);
}
EXPORT_SYMBOL(flush_cache_all_local);

/* flushes EVERYTHING (tlb & cache) */

void
flush_all_caches(void)
{
	flush_cache_all();
	flush_tlb_all();
}
EXPORT_SYMBOL(flush_all_caches);

void
update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
	struct page *page = pte_page(pte);

	if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
	    test_bit(PG_dcache_dirty, &page->flags)) {

		flush_kernel_dcache_page(page);
		clear_bit(PG_dcache_dirty, &page->flags);
	}
}

void
show_cache_info(struct seq_file *m)
{
	seq_printf(m, "I-cache\t\t: %ld KB\n", 
		cache_info.ic_size/1024 );
	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %d-way associative)\n", 
		cache_info.dc_size/1024,
		(cache_info.dc_conf.cc_wt ? "WT":"WB"),
		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
		(cache_info.dc_conf.cc_assoc)
	);

	seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
		cache_info.it_size,
		cache_info.dt_size,
		cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
	);
		
#ifndef CONFIG_PA20
	/* BTLB - Block TLB */
	if (btlb_info.max_size==0) {
		seq_printf(m, "BTLB\t\t: not supported\n" );
	} else {
		seq_printf(m, 
		"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
		"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
		"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
		btlb_info.max_size, (int)4096,
		btlb_info.max_size>>8,
		btlb_info.fixed_range_info.num_i,
		btlb_info.fixed_range_info.num_d,
		btlb_info.fixed_range_info.num_comb, 
		btlb_info.variable_range_info.num_i,
		btlb_info.variable_range_info.num_d,
		btlb_info.variable_range_info.num_comb
		);
	}
#endif
}

void __init 
parisc_cache_init(void)
{
	if (pdc_cache_info(&cache_info) < 0)
		panic("parisc_cache_init: pdc_cache_info failed");

#if 0
	printk("ic_size %lx dc_size %lx it_size %lx\n",
		cache_info.ic_size,
		cache_info.dc_size,
		cache_info.it_size);

	printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
		cache_info.dc_base,
		cache_info.dc_stride,
		cache_info.dc_count,
		cache_info.dc_loop);

	printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
		*(unsigned long *) (&cache_info.dc_conf),
		cache_info.dc_conf.cc_alias,
		cache_info.dc_conf.cc_block,
		cache_info.dc_conf.cc_line,
		cache_info.dc_conf.cc_shift);
	printk("	wt %d sh %d cst %d assoc %d\n",
		cache_info.dc_conf.cc_wt,
		cache_info.dc_conf.cc_sh,
		cache_info.dc_conf.cc_cst,
		cache_info.dc_conf.cc_assoc);

	printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
		cache_info.ic_base,
		cache_info.ic_stride,
		cache_info.ic_count,
		cache_info.ic_loop);

	printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
		*(unsigned long *) (&cache_info.ic_conf),
		cache_info.ic_conf.cc_alias,
		cache_info.ic_conf.cc_block,
		cache_info.ic_conf.cc_line,
		cache_info.ic_conf.cc_shift);
	printk("	wt %d sh %d cst %d assoc %d\n",
		cache_info.ic_conf.cc_wt,
		cache_info.ic_conf.cc_sh,
		cache_info.ic_conf.cc_cst,
		cache_info.ic_conf.cc_assoc);

	printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
		cache_info.dt_conf.tc_sh,
		cache_info.dt_conf.tc_page,
		cache_info.dt_conf.tc_cst,
		cache_info.dt_conf.tc_aid,
		cache_info.dt_conf.tc_pad1);

	printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
		cache_info.it_conf.tc_sh,
		cache_info.it_conf.tc_page,
		cache_info.it_conf.tc_cst,
		cache_info.it_conf.tc_aid,
		cache_info.it_conf.tc_pad1);
#endif

	split_tlb = 0;
	if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
		if (cache_info.dt_conf.tc_sh == 2)
			printk(KERN_WARNING "Unexpected TLB configuration. "
			"Will flush I/D separately (could be optimized).\n");

		split_tlb = 1;
	}

	/* "New and Improved" version from Jim Hull 
	 *	(1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
	 * The following CAFL_STRIDE is an optimized version, see
	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
	 */
#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
	dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
	icache_stride = CAFL_STRIDE(cache_info.ic_conf);
#undef CAFL_STRIDE

#ifndef CONFIG_PA20
	if (pdc_btlb_info(&btlb_info) < 0) {
		memset(&btlb_info, 0, sizeof btlb_info);
	}
#endif

	if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
						PDC_MODEL_NVA_UNSUPPORTED) {
		printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
#if 0
		panic("SMP kernel required to avoid non-equivalent aliasing");
#endif
	}
}

void disable_sr_hashing(void)
{
	int srhash_type;

	switch (boot_cpu_data.cpu_type) {
	case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
		BUG();
		return;

	case pcxs:
	case pcxt:
	case pcxt_:
		srhash_type = SRHASH_PCXST;
		break;

	case pcxl:
		srhash_type = SRHASH_PCXL;
		break;

	case pcxl2: /* pcxl2 doesn't support space register hashing */
		return;

	default: /* Currently all PA2.0 machines use the same ins. sequence */
		srhash_type = SRHASH_PA20;
		break;
	}

	disable_sr_hashing_asm(srhash_type);
}

void flush_dcache_page(struct page *page)
{
	struct address_space *mapping = page_mapping(page);
	struct vm_area_struct *mpnt;
	struct prio_tree_iter iter;
	unsigned long offset;
	unsigned long addr;
	pgoff_t pgoff;
	unsigned long pfn = page_to_pfn(page);


	if (mapping && !mapping_mapped(mapping)) {
		set_bit(PG_dcache_dirty, &page->flags);
		return;
	}

	flush_kernel_dcache_page(page);

	if (!mapping)
		return;

	pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);

	/* We have carefully arranged in arch_get_unmapped_area() that
	 * *any* mappings of a file are always congruently mapped (whether
	 * declared as MAP_PRIVATE or MAP_SHARED), so we only need
	 * to flush one address here for them all to become coherent */

	flush_dcache_mmap_lock(mapping);
	vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
		addr = mpnt->vm_start + offset;

		/* Flush instructions produce non access tlb misses.
		 * On PA, we nullify these instructions rather than
		 * taking a page fault if the pte doesn't exist.
		 * This is just for speed.  If the page translation
		 * isn't there, there's no point exciting the
		 * nadtlb handler into a nullification frenzy.
		 *
		 * Make sure we really have this page: the private
		 * mappings may cover this area but have COW'd this
		 * particular page.
		 */
  		if (translation_exists(mpnt, addr, pfn)) {
			__flush_cache_page(mpnt, addr);
			break;
		}
	}
	flush_dcache_mmap_unlock(mapping);
}
EXPORT_SYMBOL(flush_dcache_page);

/* Defined in arch/parisc/kernel/pacache.S */
EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
EXPORT_SYMBOL(flush_data_cache_local);
EXPORT_SYMBOL(flush_kernel_icache_range_asm);

void clear_user_page_asm(void *page, unsigned long vaddr)
{
	/* This function is implemented in assembly in pacache.S */
	extern void __clear_user_page_asm(void *page, unsigned long vaddr);

	purge_tlb_start();
	__clear_user_page_asm(page, vaddr);
	purge_tlb_end();
}

#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;

void parisc_setup_cache_timing(void)
{
	unsigned long rangetime, alltime;
	unsigned long size;

	alltime = mfctl(16);
	flush_data_cache();
	alltime = mfctl(16) - alltime;

	size = (unsigned long)(_end - _text);
	rangetime = mfctl(16);
	flush_kernel_dcache_range((unsigned long)_text, size);
	rangetime = mfctl(16) - rangetime;

	printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
		alltime, size, rangetime);

	/* Racy, but if we see an intermediate value, it's ok too... */
	parisc_cache_flush_threshold = size * alltime / rangetime;

	parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1); 
	if (!parisc_cache_flush_threshold)
		parisc_cache_flush_threshold = FLUSH_THRESHOLD;

	printk("Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
}
Commit	Line	Data
1da177e4 LT	1	/* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
	2	*
	3	* This file is subject to the terms and conditions of the GNU General Public
	4	* License. See the file "COPYING" in the main directory of this archive
	5	* for more details.
	6	*
	7	* Copyright (C) 1999 Helge Deller (07-13-1999)
	8	* Copyright (C) 1999 SuSE GmbH Nuernberg
	9	* Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
	10	*
	11	* Cache and TLB management
	12	*
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/kernel.h>
	17	#include <linux/mm.h>
	18	#include <linux/module.h>
	19	#include <linux/seq_file.h>
	20	#include <linux/pagemap.h>
	21
	22	#include <asm/pdc.h>
	23	#include <asm/cache.h>
	24	#include <asm/cacheflush.h>
	25	#include <asm/tlbflush.h>
	26	#include <asm/system.h>
	27	#include <asm/page.h>
	28	#include <asm/pgalloc.h>
	29	#include <asm/processor.h>
2464212f	30	#include <asm/sections.h>
1da177e4	31
8039de10 HD	32	int split_tlb __read_mostly;
	33	int dcache_stride __read_mostly;
	34	int icache_stride __read_mostly;
1da177e4 LT	35	EXPORT_SYMBOL(dcache_stride);
	36
	37
	38	#if defined(CONFIG_SMP)
	39	/* On some machines (e.g. ones with the Merced bus), there can be
	40	* only a single PxTLB broadcast at a time; this must be guaranteed
	41	* by software. We put a spinlock around all TLB flushes to
	42	* ensure this.
	43	*/
	44	DEFINE_SPINLOCK(pa_tlb_lock);
	45	EXPORT_SYMBOL(pa_tlb_lock);
	46	#endif
	47
8039de10	48	struct pdc_cache_info cache_info __read_mostly;
1da177e4	49	#ifndef CONFIG_PA20
8039de10	50	static struct pdc_btlb_info btlb_info __read_mostly;
1da177e4 LT	51	#endif
	52
	53	#ifdef CONFIG_SMP
	54	void
	55	flush_data_cache(void)
	56	{
1b2425e3	57	on_each_cpu(flush_data_cache_local, NULL, 1, 1);
1da177e4 LT	58	}
	59	void
	60	flush_instruction_cache(void)
	61	{
1b2425e3	62	on_each_cpu(flush_instruction_cache_local, NULL, 1, 1);
1da177e4 LT	63	}
	64	#endif
	65
	66	void
	67	flush_cache_all_local(void)
	68	{
1b2425e3 MW	69	flush_instruction_cache_local(NULL);
1b2425e3 MW	70	flush_data_cache_local(NULL);
1da177e4 LT	71	}
	72	EXPORT_SYMBOL(flush_cache_all_local);
	73
	74	/* flushes EVERYTHING (tlb & cache) */
	75
	76	void
	77	flush_all_caches(void)
	78	{
	79	flush_cache_all();
	80	flush_tlb_all();
	81	}
	82	EXPORT_SYMBOL(flush_all_caches);
	83
	84	void
	85	update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
	86	{
	87	struct page *page = pte_page(pte);
	88
	89	if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
	90	test_bit(PG_dcache_dirty, &page->flags)) {
	91
ba575833	92	flush_kernel_dcache_page(page);
1da177e4 LT	93	clear_bit(PG_dcache_dirty, &page->flags);
	94	}
	95	}
	96
	97	void
	98	show_cache_info(struct seq_file *m)
	99	{
	100	seq_printf(m, "I-cache\t\t: %ld KB\n",
	101	cache_info.ic_size/1024 );
	102	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %d-way associative)\n",
	103	cache_info.dc_size/1024,
	104	(cache_info.dc_conf.cc_wt ? "WT":"WB"),
	105	(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
	106	(cache_info.dc_conf.cc_assoc)
	107	);
	108
	109	seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
	110	cache_info.it_size,
	111	cache_info.dt_size,
	112	cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
	113	);
	114
	115	#ifndef CONFIG_PA20
	116	/* BTLB - Block TLB */
	117	if (btlb_info.max_size==0) {
	118	seq_printf(m, "BTLB\t\t: not supported\n" );
	119	} else {
	120	seq_printf(m,
	121	"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
	122	"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
	123	"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
	124	btlb_info.max_size, (int)4096,
	125	btlb_info.max_size>>8,
	126	btlb_info.fixed_range_info.num_i,
	127	btlb_info.fixed_range_info.num_d,
	128	btlb_info.fixed_range_info.num_comb,
	129	btlb_info.variable_range_info.num_i,
	130	btlb_info.variable_range_info.num_d,
	131	btlb_info.variable_range_info.num_comb
	132	);
	133	}
	134	#endif
	135	}
	136
	137	void __init
	138	parisc_cache_init(void)
	139	{
	140	if (pdc_cache_info(&cache_info) < 0)
	141	panic("parisc_cache_init: pdc_cache_info failed");
	142
	143	#if 0
	144	printk("ic_size %lx dc_size %lx it_size %lx\n",
	145	cache_info.ic_size,
	146	cache_info.dc_size,
	147	cache_info.it_size);
	148
	149	printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
	150	cache_info.dc_base,
	151	cache_info.dc_stride,
	152	cache_info.dc_count,
	153	cache_info.dc_loop);
	154
	155	printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
	156	(unsigned long ) (&cache_info.dc_conf),
157	cache_info.dc_conf.cc_alias,
158	cache_info.dc_conf.cc_block,
159	cache_info.dc_conf.cc_line,
160	cache_info.dc_conf.cc_shift);
161	printk(" wt %d sh %d cst %d assoc %d\n",
162	cache_info.dc_conf.cc_wt,
163	cache_info.dc_conf.cc_sh,
164	cache_info.dc_conf.cc_cst,
165	cache_info.dc_conf.cc_assoc);
166
167	printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
168	cache_info.ic_base,
169	cache_info.ic_stride,
170	cache_info.ic_count,
171	cache_info.ic_loop);
172
173	printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
174	(unsigned long ) (&cache_info.ic_conf),
175	cache_info.ic_conf.cc_alias,
176	cache_info.ic_conf.cc_block,
177	cache_info.ic_conf.cc_line,
178	cache_info.ic_conf.cc_shift);
179	printk(" wt %d sh %d cst %d assoc %d\n",
180	cache_info.ic_conf.cc_wt,
181	cache_info.ic_conf.cc_sh,
182	cache_info.ic_conf.cc_cst,
183	cache_info.ic_conf.cc_assoc);
184
185	printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
186	cache_info.dt_conf.tc_sh,
187	cache_info.dt_conf.tc_page,
188	cache_info.dt_conf.tc_cst,
189	cache_info.dt_conf.tc_aid,
190	cache_info.dt_conf.tc_pad1);
191
192	printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
193	cache_info.it_conf.tc_sh,
194	cache_info.it_conf.tc_page,
195	cache_info.it_conf.tc_cst,
196	cache_info.it_conf.tc_aid,
197	cache_info.it_conf.tc_pad1);
198	#endif
199
200	split_tlb = 0;
201	if (cache_info.dt_conf.tc_sh == 0 \|\| cache_info.dt_conf.tc_sh == 2) {
202	if (cache_info.dt_conf.tc_sh == 2)
203	printk(KERN_WARNING "Unexpected TLB configuration. "
204	"Will flush I/D separately (could be optimized).\n");
205
206	split_tlb = 1;
207	}
208
209	/* "New and Improved" version from Jim Hull
210	* (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
2464212f SB	211	* The following CAFL_STRIDE is an optimized version, see
	212	* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
	213	* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
1da177e4 LT	214	*/
	215	#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
	216	dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
	217	icache_stride = CAFL_STRIDE(cache_info.ic_conf);
	218	#undef CAFL_STRIDE
	219
	220	#ifndef CONFIG_PA20
	221	if (pdc_btlb_info(&btlb_info) < 0) {
	222	memset(&btlb_info, 0, sizeof btlb_info);
	223	}
	224	#endif
	225
	226	if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
	227	PDC_MODEL_NVA_UNSUPPORTED) {
	228	printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
	229	#if 0
	230	panic("SMP kernel required to avoid non-equivalent aliasing");
	231	#endif
	232	}
	233	}
	234
	235	void disable_sr_hashing(void)
	236	{
	237	int srhash_type;
	238
	239	switch (boot_cpu_data.cpu_type) {
	240	case pcx: /* We shouldn't get this far. setup.c should prevent it. */
	241	BUG();
	242	return;
	243
	244	case pcxs:
	245	case pcxt:
	246	case pcxt_:
	247	srhash_type = SRHASH_PCXST;
	248	break;
	249
	250	case pcxl:
	251	srhash_type = SRHASH_PCXL;
	252	break;
	253
	254	case pcxl2: /* pcxl2 doesn't support space register hashing */
	255	return;
	256
	257	default: /* Currently all PA2.0 machines use the same ins. sequence */
	258	srhash_type = SRHASH_PA20;
	259	break;
	260	}
	261
	262	disable_sr_hashing_asm(srhash_type);
	263	}
	264
	265	void flush_dcache_page(struct page *page)
	266	{
	267	struct address_space *mapping = page_mapping(page);
	268	struct vm_area_struct *mpnt;
	269	struct prio_tree_iter iter;
	270	unsigned long offset;
	271	unsigned long addr;
	272	pgoff_t pgoff;
1da177e4 LT	273	unsigned long pfn = page_to_pfn(page);
	274
	275
	276	if (mapping && !mapping_mapped(mapping)) {
	277	set_bit(PG_dcache_dirty, &page->flags);
	278	return;
	279	}
	280
ba575833	281	flush_kernel_dcache_page(page);
1da177e4 LT	282
	283	if (!mapping)
	284	return;
	285
	286	pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
	287
	288	/* We have carefully arranged in arch_get_unmapped_area() that
	289	* any mappings of a file are always congruently mapped (whether
	290	* declared as MAP_PRIVATE or MAP_SHARED), so we only need
	291	* to flush one address here for them all to become coherent */
	292
	293	flush_dcache_mmap_lock(mapping);
	294	vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
	295	offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
	296	addr = mpnt->vm_start + offset;
	297
	298	/* Flush instructions produce non access tlb misses.
	299	* On PA, we nullify these instructions rather than
	300	* taking a page fault if the pte doesn't exist.
	301	* This is just for speed. If the page translation
	302	* isn't there, there's no point exciting the
92dc6fcc HD	303	* nadtlb handler into a nullification frenzy.
	304	*
	305	* Make sure we really have this page: the private
1da177e4	306	* mappings may cover this area but have COW'd this
92dc6fcc HD	307	* particular page.
	308	*/
	309	if (translation_exists(mpnt, addr, pfn)) {
	310	__flush_cache_page(mpnt, addr);
	311	break;
	312	}
1da177e4 LT	313	}
	314	flush_dcache_mmap_unlock(mapping);
	315	}
	316	EXPORT_SYMBOL(flush_dcache_page);
	317
	318	/* Defined in arch/parisc/kernel/pacache.S */
	319	EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
ba575833	320	EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
1da177e4 LT	321	EXPORT_SYMBOL(flush_data_cache_local);
	322	EXPORT_SYMBOL(flush_kernel_icache_range_asm);
	323
	324	void clear_user_page_asm(void *page, unsigned long vaddr)
	325	{
	326	/* This function is implemented in assembly in pacache.S */
	327	extern void __clear_user_page_asm(void *page, unsigned long vaddr);
	328
	329	purge_tlb_start();
	330	__clear_user_page_asm(page, vaddr);
	331	purge_tlb_end();
	332	}
	333
	334	#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
8039de10	335	int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
1da177e4 LT	336
	337	void parisc_setup_cache_timing(void)
	338	{
	339	unsigned long rangetime, alltime;
1da177e4 LT	340	unsigned long size;
	341
	342	alltime = mfctl(16);
	343	flush_data_cache();
	344	alltime = mfctl(16) - alltime;
	345
2464212f	346	size = (unsigned long)(_end - _text);
1da177e4	347	rangetime = mfctl(16);
2464212f	348	flush_kernel_dcache_range((unsigned long)_text, size);
1da177e4 LT	349	rangetime = mfctl(16) - rangetime;
	350
	351	printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
	352	alltime, size, rangetime);
	353
	354	/* Racy, but if we see an intermediate value, it's ok too... */
	355	parisc_cache_flush_threshold = size * alltime / rangetime;
	356
	357	parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
	358	if (!parisc_cache_flush_threshold)
	359	parisc_cache_flush_threshold = FLUSH_THRESHOLD;
	360
	361	printk("Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
	362	}