[deliverable/linux.git] / arch / parisc / kernel / head.S

/* This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1999-2007 by Helge Deller <deller@gmx.de>
 * Copyright 1999 SuSE GmbH (Philipp Rumpf)
 * Copyright 1999 Philipp Rumpf (prumpf@tux.org)
 * Copyright 2000 Hewlett Packard (Paul Bame, bame@puffin.external.hp.com)
 * Copyright (C) 2001 Grant Grundler (Hewlett Packard)
 * Copyright (C) 2004 Kyle McMartin <kyle@debian.org>
 *
 * Initial Version 04-23-1999 by Helge Deller <deller@gmx.de>
 */

#include <asm/asm-offsets.h>
#include <asm/psw.h>
#include <asm/pdc.h>
	
#include <asm/assembly.h>
#include <asm/pgtable.h>

#include <linux/linkage.h>
#include <linux/init.h>

	.level	LEVEL

	__INITDATA
ENTRY(boot_args)
	.word 0 /* arg0 */
	.word 0 /* arg1 */
	.word 0 /* arg2 */
	.word 0 /* arg3 */
END(boot_args)

	__HEAD

	.align	4
	.import init_thread_union,data
	.import fault_vector_20,code    /* IVA parisc 2.0 32 bit */
#ifndef CONFIG_64BIT
        .import fault_vector_11,code    /* IVA parisc 1.1 32 bit */
	.import	$global$		/* forward declaration */
#endif /*!CONFIG_64BIT*/
	.export _stext,data		/* Kernel want it this way! */
_stext:
ENTRY(stext)
	.proc
	.callinfo

	/* Make sure sr4-sr7 are set to zero for the kernel address space */
	mtsp	%r0,%sr4
	mtsp	%r0,%sr5
	mtsp	%r0,%sr6
	mtsp	%r0,%sr7

	/* Clear BSS (shouldn't the boot loader do this?) */

	.import __bss_start,data
	.import __bss_stop,data

	load32		PA(__bss_start),%r3
	load32		PA(__bss_stop),%r4
$bss_loop:
	cmpb,<<,n       %r3,%r4,$bss_loop
	stw,ma          %r0,4(%r3)

	/* Save away the arguments the boot loader passed in (32 bit args) */
	load32		PA(boot_args),%r1
	stw,ma          %arg0,4(%r1)
	stw,ma          %arg1,4(%r1)
	stw,ma          %arg2,4(%r1)
	stw,ma          %arg3,4(%r1)

	/* Initialize startup VM. Just map first 8/16 MB of memory */
	load32		PA(swapper_pg_dir),%r4
	mtctl		%r4,%cr24	/* Initialize kernel root pointer */
	mtctl		%r4,%cr25	/* Initialize user root pointer */

#if PT_NLEVELS == 3
	/* Set pmd in pgd */
	load32		PA(pmd0),%r5
	shrd            %r5,PxD_VALUE_SHIFT,%r3	
	ldo		(PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
	stw		%r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4)
	ldo		ASM_PMD_ENTRY*ASM_PMD_ENTRY_SIZE(%r5),%r4
#else
	/* 2-level page table, so pmd == pgd */
	ldo		ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4),%r4
#endif

	/* Fill in pmd with enough pte directories */
	load32		PA(pg0),%r1
	SHRREG		%r1,PxD_VALUE_SHIFT,%r3
	ldo		(PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3

	ldi		ASM_PT_INITIAL,%r1

1:
	stw		%r3,0(%r4)
	ldo		(PAGE_SIZE >> PxD_VALUE_SHIFT)(%r3),%r3
	addib,>		-1,%r1,1b
#if PT_NLEVELS == 3
	ldo             ASM_PMD_ENTRY_SIZE(%r4),%r4
#else
	ldo             ASM_PGD_ENTRY_SIZE(%r4),%r4
#endif


	/* Now initialize the PTEs themselves.  We use RWX for
	 * everything ... it will get remapped correctly later */
	ldo		0+_PAGE_KERNEL_RWX(%r0),%r3 /* Hardwired 0 phys addr start */
	ldi		(1<<(KERNEL_INITIAL_ORDER-PAGE_SHIFT)),%r11 /* PFN count */
	load32		PA(pg0),%r1

$pgt_fill_loop:
	STREGM          %r3,ASM_PTE_ENTRY_SIZE(%r1)
	ldo		(1<<PFN_PTE_SHIFT)(%r3),%r3 /* add one PFN */
	addib,>		-1,%r11,$pgt_fill_loop
	nop

	/* Load the return address...er...crash 'n burn */
	copy		%r0,%r2

	/* And the RFI Target address too */
	load32		start_parisc,%r11

	/* And the initial task pointer */
	load32		init_thread_union,%r6
	mtctl           %r6,%cr30

	/* And the stack pointer too */
	ldo             THREAD_SZ_ALGN(%r6),%sp

#ifdef CONFIG_SMP
	/* Set the smp rendezvous address into page zero.
	** It would be safer to do this in init_smp_config() but
	** it's just way easier to deal with here because
	** of 64-bit function ptrs and the address is local to this file.
	*/
	load32		PA(smp_slave_stext),%r10
	stw		%r10,0x10(%r0)	/* MEM_RENDEZ */
	stw		%r0,0x28(%r0)	/* MEM_RENDEZ_HI - assume addr < 4GB */

	/* FALLTHROUGH */
	.procend

	/*
	** Code Common to both Monarch and Slave processors.
	** Entry:
	**
	**  1.1:	
	**    %r11 must contain RFI target address.
	**    %r25/%r26 args to pass to target function
	**    %r2  in case rfi target decides it didn't like something
	**
	**  2.0w:
	**    %r3  PDCE_PROC address
	**    %r11 RFI target address
	**
	** Caller must init: SR4-7, %sp, %r10, %cr24/25, 
	*/
common_stext:
	.proc
	.callinfo
#else
	/* Clear PDC entry point - we won't use it */
	stw		%r0,0x10(%r0)	/* MEM_RENDEZ */
	stw		%r0,0x28(%r0)	/* MEM_RENDEZ_HI */
#endif /*CONFIG_SMP*/

#ifdef CONFIG_64BIT
	tophys_r1	%sp

	/* Save the rfi target address */
	ldd             TI_TASK-THREAD_SZ_ALGN(%sp), %r10
	tophys_r1       %r10
	std             %r11,  TASK_PT_GR11(%r10)
	/* Switch to wide mode Superdome doesn't support narrow PDC
	** calls.
	*/
1:	mfia            %rp             /* clear upper part of pcoq */
	ldo             2f-1b(%rp),%rp
	depdi           0,31,32,%rp
	bv              (%rp)
	ssm             PSW_SM_W,%r0

        /* Set Wide mode as the "Default" (eg for traps)
        ** First trap occurs *right* after (or part of) rfi for slave CPUs.
        ** Someday, palo might not do this for the Monarch either.
        */
2:
#define MEM_PDC_LO 0x388
#define MEM_PDC_HI 0x35C
	ldw             MEM_PDC_LO(%r0),%r3
	ldw             MEM_PDC_HI(%r0),%r6
	depd            %r6, 31, 32, %r3        /* move to upper word */

	mfctl		%cr30,%r6		/* PCX-W2 firmware bug */

	ldo             PDC_PSW(%r0),%arg0              /* 21 */
	ldo             PDC_PSW_SET_DEFAULTS(%r0),%arg1 /* 2 */
	ldo             PDC_PSW_WIDE_BIT(%r0),%arg2     /* 2 */
	load32          PA(stext_pdc_ret), %rp
	bv              (%r3)
	copy            %r0,%arg3

stext_pdc_ret:
	mtctl		%r6,%cr30		/* restore task thread info */

	/* restore rfi target address*/
	ldd             TI_TASK-THREAD_SZ_ALGN(%sp), %r10
	tophys_r1       %r10
	ldd             TASK_PT_GR11(%r10), %r11
	tovirt_r1       %sp
#endif
	
	/* PARANOID: clear user scratch/user space SR's */
	mtsp	%r0,%sr0
	mtsp	%r0,%sr1
	mtsp	%r0,%sr2
	mtsp	%r0,%sr3

	/* Initialize Protection Registers */
	mtctl	%r0,%cr8
	mtctl	%r0,%cr9
	mtctl	%r0,%cr12
	mtctl	%r0,%cr13

	/* Initialize the global data pointer */
	loadgp

	/* Set up our interrupt table.  HPMCs might not work after this! 
	 *
	 * We need to install the correct iva for PA1.1 or PA2.0. The
	 * following short sequence of instructions can determine this
	 * (without being illegal on a PA1.1 machine).
	 */
#ifndef CONFIG_64BIT
	ldi		32,%r10
	mtctl		%r10,%cr11
	.level 2.0
	mfctl,w		%cr11,%r10
	.level 1.1
	comib,<>,n	0,%r10,$is_pa20
	ldil		L%PA(fault_vector_11),%r10
	b		$install_iva
	ldo		R%PA(fault_vector_11)(%r10),%r10

$is_pa20:
	.level		LEVEL /* restore 1.1 || 2.0w */
#endif /*!CONFIG_64BIT*/
	load32		PA(fault_vector_20),%r10

$install_iva:
	mtctl		%r10,%cr14

	b		aligned_rfi  /* Prepare to RFI! Man all the cannons! */
	nop

	.align 128
aligned_rfi:
	pcxt_ssm_bug

	rsm		PSW_SM_QUIET,%r0	/* off troublesome PSW bits */
	/* Don't need NOPs, have 8 compliant insn before rfi */

	mtctl		%r0,%cr17	/* Clear IIASQ tail */
	mtctl		%r0,%cr17	/* Clear IIASQ head */

	/* Load RFI target into PC queue */
	mtctl		%r11,%cr18	/* IIAOQ head */
	ldo		4(%r11),%r11
	mtctl		%r11,%cr18	/* IIAOQ tail */

	load32		KERNEL_PSW,%r10
	mtctl		%r10,%ipsw
	
	/* Jump through hyperspace to Virt Mode */
	rfi
	nop

	.procend

#ifdef CONFIG_SMP

	.import smp_init_current_idle_task,data
	.import	smp_callin,code

#ifndef CONFIG_64BIT
smp_callin_rtn:
        .proc
	.callinfo
	break	1,1		/*  Break if returned from start_secondary */
	nop
	nop
        .procend
#endif /*!CONFIG_64BIT*/

/***************************************************************************
* smp_slave_stext is executed by all non-monarch Processors when the Monarch
* pokes the slave CPUs in smp.c:smp_boot_cpus().
*
* Once here, registers values are initialized in order to branch to virtual
* mode. Once all available/eligible CPUs are in virtual mode, all are
* released and start out by executing their own idle task.
*****************************************************************************/
smp_slave_stext:
        .proc
	.callinfo

	/*
	** Initialize Space registers
	*/
	mtsp	   %r0,%sr4
	mtsp	   %r0,%sr5
	mtsp	   %r0,%sr6
	mtsp	   %r0,%sr7

	/*  Initialize the SP - monarch sets up smp_init_current_idle_task */
	load32		PA(smp_init_current_idle_task),%sp
	LDREG		0(%sp),%sp	/* load task address */
	tophys_r1	%sp
	LDREG		TASK_THREAD_INFO(%sp),%sp
	mtctl           %sp,%cr30       /* store in cr30 */
	ldo             THREAD_SZ_ALGN(%sp),%sp

	/* point CPU to kernel page tables */
	load32		PA(swapper_pg_dir),%r4
	mtctl		%r4,%cr24	/* Initialize kernel root pointer */
	mtctl		%r4,%cr25	/* Initialize user root pointer */

#ifdef CONFIG_64BIT
	/* Setup PDCE_PROC entry */
	copy            %arg0,%r3
#else
	/* Load RFI *return* address in case smp_callin bails */
	load32		smp_callin_rtn,%r2
#endif
	
	/* Load RFI target address.  */
	load32		smp_callin,%r11
	
	/* ok...common code can handle the rest */
	b		common_stext
	nop

	.procend
#endif /* CONFIG_SMP */

ENDPROC(stext)

#ifndef CONFIG_64BIT
	.section .data..read_mostly

	.align	4
	.export	$global$,data

	.type	$global$,@object
	.size	$global$,4
$global$:	
	.word 0
#endif /*!CONFIG_64BIT*/
Commit	Line	Data
1da177e4 LT	1	/* This file is subject to the terms and conditions of the GNU General Public
	2	* License. See the file "COPYING" in the main directory of this archive
	3	* for more details.
	4	*
8e9e9844	5	* Copyright (C) 1999-2007 by Helge Deller <deller@gmx.de>
1da177e4 LT	6	* Copyright 1999 SuSE GmbH (Philipp Rumpf)
	7	* Copyright 1999 Philipp Rumpf (prumpf@tux.org)
	8	* Copyright 2000 Hewlett Packard (Paul Bame, bame@puffin.external.hp.com)
	9	* Copyright (C) 2001 Grant Grundler (Hewlett Packard)
	10	* Copyright (C) 2004 Kyle McMartin <kyle@debian.org>
	11	*
	12	* Initial Version 04-23-1999 by Helge Deller <deller@gmx.de>
	13	*/
	14
0013a854	15	#include <asm/asm-offsets.h>
1da177e4 LT	16	#include <asm/psw.h>
	17	#include <asm/pdc.h>
	18
	19	#include <asm/assembly.h>
	20	#include <asm/pgtable.h>
	21
8e9e9844	22	#include <linux/linkage.h>
0c634cc6	23	#include <linux/init.h>
8e9e9844	24
1da177e4 LT	25	.level LEVEL
1da177e4 LT	26
0c634cc6	27	__INITDATA
8e9e9844	28	ENTRY(boot_args)
1da177e4 LT	29	.word 0 /* arg0 */
	30	.word 0 /* arg1 */
	31	.word 0 /* arg2 */
	32	.word 0 /* arg3 */
8e9e9844	33	END(boot_args)
1da177e4	34
1138a72c KM	35	__HEAD
1138a72c KM	36
1da177e4 LT	37	.align 4
	38	.import init_thread_union,data
	39	.import fault_vector_20,code /* IVA parisc 2.0 32 bit */
413059f2	40	#ifndef CONFIG_64BIT
1da177e4 LT	41	.import fault_vector_11,code /* IVA parisc 1.1 32 bit */
1da177e4 LT	42	.import $global$ /* forward declaration */
413059f2	43	#endif /!CONFIG_64BIT/
1da177e4 LT	44	.export _stext,data /* Kernel want it this way! */
1da177e4 LT	45	_stext:
8e9e9844	46	ENTRY(stext)
1da177e4 LT	47	.proc
	48	.callinfo
	49
	50	/* Make sure sr4-sr7 are set to zero for the kernel address space */
	51	mtsp %r0,%sr4
	52	mtsp %r0,%sr5
	53	mtsp %r0,%sr6
	54	mtsp %r0,%sr7
	55
	56	/* Clear BSS (shouldn't the boot loader do this?) */
	57
	58	.import __bss_start,data
	59	.import __bss_stop,data
	60
	61	load32 PA(__bss_start),%r3
	62	load32 PA(__bss_stop),%r4
	63	$bss_loop:
	64	cmpb,<<,n %r3,%r4,$bss_loop
	65	stw,ma %r0,4(%r3)
	66
	67	/* Save away the arguments the boot loader passed in (32 bit args) */
	68	load32 PA(boot_args),%r1
	69	stw,ma %arg0,4(%r1)
	70	stw,ma %arg1,4(%r1)
	71	stw,ma %arg2,4(%r1)
	72	stw,ma %arg3,4(%r1)
	73
	74	/* Initialize startup VM. Just map first 8/16 MB of memory */
	75	load32 PA(swapper_pg_dir),%r4
	76	mtctl %r4,%cr24 /* Initialize kernel root pointer */
	77	mtctl %r4,%cr25 /* Initialize user root pointer */
	78
2fd83038	79	#if PT_NLEVELS == 3
1da177e4 LT	80	/* Set pmd in pgd */
	81	load32 PA(pmd0),%r5
	82	shrd %r5,PxD_VALUE_SHIFT,%r3
2fd83038	83	ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
1da177e4 LT	84	stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4)
	85	ldo ASM_PMD_ENTRY*ASM_PMD_ENTRY_SIZE(%r5),%r4
	86	#else
	87	/* 2-level page table, so pmd == pgd */
2fd83038	88	ldo ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4),%r4
1da177e4 LT	89	#endif
	90
	91	/* Fill in pmd with enough pte directories */
	92	load32 PA(pg0),%r1
	93	SHRREG %r1,PxD_VALUE_SHIFT,%r3
	94	ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
	95
	96	ldi ASM_PT_INITIAL,%r1
	97
	98	1:
	99	stw %r3,0(%r4)
80af0876	100	ldo (PAGE_SIZE >> PxD_VALUE_SHIFT)(%r3),%r3
1da177e4	101	addib,> -1,%r1,1b
2fd83038	102	#if PT_NLEVELS == 3
1da177e4 LT	103	ldo ASM_PMD_ENTRY_SIZE(%r4),%r4
	104	#else
	105	ldo ASM_PGD_ENTRY_SIZE(%r4),%r4
	106	#endif
	107
	108
d7dd2ff1 JB	109	/* Now initialize the PTEs themselves. We use RWX for
	110	* everything ... it will get remapped correctly later */
	111	ldo 0+_PAGE_KERNEL_RWX(%r0),%r3 /* Hardwired 0 phys addr start */
2fd83038	112	ldi (1<<(KERNEL_INITIAL_ORDER-PAGE_SHIFT)),%r11 /* PFN count */
1da177e4 LT	113	load32 PA(pg0),%r1
	114
	115	$pgt_fill_loop:
	116	STREGM %r3,ASM_PTE_ENTRY_SIZE(%r1)
2fd83038 HD	117	ldo (1<<PFN_PTE_SHIFT)(%r3),%r3 /* add one PFN */
2fd83038 HD	118	addib,> -1,%r11,$pgt_fill_loop
1da177e4 LT	119	nop
	120
	121	/* Load the return address...er...crash 'n burn */
	122	copy %r0,%r2
	123
	124	/* And the RFI Target address too */
089d5528	125	load32 start_parisc,%r11
1da177e4 LT	126
	127	/* And the initial task pointer */
	128	load32 init_thread_union,%r6
	129	mtctl %r6,%cr30
	130
	131	/* And the stack pointer too */
	132	ldo THREAD_SZ_ALGN(%r6),%sp
	133
1da177e4	134	#ifdef CONFIG_SMP
25985edc	135	/* Set the smp rendezvous address into page zero.
1da177e4 LT	136	** It would be safer to do this in init_smp_config() but
	137	** it's just way easier to deal with here because
	138	** of 64-bit function ptrs and the address is local to this file.
	139	*/
	140	load32 PA(smp_slave_stext),%r10
	141	stw %r10,0x10(%r0) /* MEM_RENDEZ */
	142	stw %r0,0x28(%r0) /* MEM_RENDEZ_HI - assume addr < 4GB */
	143
	144	/* FALLTHROUGH */
	145	.procend
	146
	147	/*
	148	** Code Common to both Monarch and Slave processors.
	149	** Entry:
	150	**
	151	** 1.1:
	152	** %r11 must contain RFI target address.
	153	** %r25/%r26 args to pass to target function
	154	** %r2 in case rfi target decides it didn't like something
	155	**
	156	** 2.0w:
	157	** %r3 PDCE_PROC address
	158	** %r11 RFI target address
	159	**
	160	** Caller must init: SR4-7, %sp, %r10, %cr24/25,
	161	*/
	162	common_stext:
	163	.proc
	164	.callinfo
	165	#else
	166	/* Clear PDC entry point - we won't use it */
	167	stw %r0,0x10(%r0) /* MEM_RENDEZ */
	168	stw %r0,0x28(%r0) /* MEM_RENDEZ_HI */
	169	#endif /CONFIG_SMP/
	170
413059f2	171	#ifdef CONFIG_64BIT
1da177e4 LT	172	tophys_r1 %sp
	173
	174	/* Save the rfi target address */
	175	ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
	176	tophys_r1 %r10
	177	std %r11, TASK_PT_GR11(%r10)
	178	/* Switch to wide mode Superdome doesn't support narrow PDC
	179	** calls.
	180	*/
	181	1: mfia %rp /* clear upper part of pcoq */
	182	ldo 2f-1b(%rp),%rp
	183	depdi 0,31,32,%rp
	184	bv (%rp)
	185	ssm PSW_SM_W,%r0
	186
	187	/* Set Wide mode as the "Default" (eg for traps)
	188	** First trap occurs right after (or part of) rfi for slave CPUs.
	189	** Someday, palo might not do this for the Monarch either.
	190	*/
	191	2:
	192	#define MEM_PDC_LO 0x388
	193	#define MEM_PDC_HI 0x35C
	194	ldw MEM_PDC_LO(%r0),%r3
	195	ldw MEM_PDC_HI(%r0),%r6
	196	depd %r6, 31, 32, %r3 /* move to upper word */
	197
54e181e0 HD	198	mfctl %cr30,%r6 /* PCX-W2 firmware bug */
54e181e0 HD	199
1da177e4 LT	200	ldo PDC_PSW(%r0),%arg0 /* 21 */
	201	ldo PDC_PSW_SET_DEFAULTS(%r0),%arg1 /* 2 */
	202	ldo PDC_PSW_WIDE_BIT(%r0),%arg2 /* 2 */
	203	load32 PA(stext_pdc_ret), %rp
	204	bv (%r3)
	205	copy %r0,%arg3
	206
	207	stext_pdc_ret:
54e181e0 HD	208	mtctl %r6,%cr30 /* restore task thread info */
54e181e0 HD	209
1da177e4 LT	210	/* restore rfi target address*/
	211	ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
	212	tophys_r1 %r10
	213	ldd TASK_PT_GR11(%r10), %r11
	214	tovirt_r1 %sp
	215	#endif
	216
	217	/* PARANOID: clear user scratch/user space SR's */
	218	mtsp %r0,%sr0
	219	mtsp %r0,%sr1
	220	mtsp %r0,%sr2
	221	mtsp %r0,%sr3
	222
	223	/* Initialize Protection Registers */
	224	mtctl %r0,%cr8
	225	mtctl %r0,%cr9
	226	mtctl %r0,%cr12
	227	mtctl %r0,%cr13
	228
1da177e4 LT	229	/* Initialize the global data pointer */
	230	loadgp
	231
	232	/* Set up our interrupt table. HPMCs might not work after this!
	233	*
	234	* We need to install the correct iva for PA1.1 or PA2.0. The
	235	* following short sequence of instructions can determine this
	236	* (without being illegal on a PA1.1 machine).
	237	*/
413059f2	238	#ifndef CONFIG_64BIT
1da177e4 LT	239	ldi 32,%r10
	240	mtctl %r10,%cr11
	241	.level 2.0
	242	mfctl,w %cr11,%r10
	243	.level 1.1
	244	comib,<>,n 0,%r10,$is_pa20
	245	ldil L%PA(fault_vector_11),%r10
	246	b $install_iva
	247	ldo R%PA(fault_vector_11)(%r10),%r10
	248
	249	$is_pa20:
	250	.level LEVEL /* restore 1.1 \|\| 2.0w */
413059f2	251	#endif /!CONFIG_64BIT/
1da177e4 LT	252	load32 PA(fault_vector_20),%r10
	253
	254	$install_iva:
	255	mtctl %r10,%cr14
	256
896a3756	257	b aligned_rfi /* Prepare to RFI! Man all the cannons! */
1da177e4 LT	258	nop
1da177e4 LT	259
896a3756	260	.align 128
1da177e4	261	aligned_rfi:
896a3756	262	pcxt_ssm_bug
1da177e4	263
896a3756 GG	264	rsm PSW_SM_QUIET,%r0 /* off troublesome PSW bits */
896a3756 GG	265	/* Don't need NOPs, have 8 compliant insn before rfi */
1da177e4	266
1da177e4 LT	267	mtctl %r0,%cr17 /* Clear IIASQ tail */
	268	mtctl %r0,%cr17 /* Clear IIASQ head */
	269
	270	/* Load RFI target into PC queue */
	271	mtctl %r11,%cr18 /* IIAOQ head */
	272	ldo 4(%r11),%r11
	273	mtctl %r11,%cr18 /* IIAOQ tail */
896a3756 GG	274
	275	load32 KERNEL_PSW,%r10
	276	mtctl %r10,%ipsw
1da177e4	277
896a3756	278	/* Jump through hyperspace to Virt Mode */
1da177e4 LT	279	rfi
	280	nop
	281
	282	.procend
	283
	284	#ifdef CONFIG_SMP
	285
	286	.import smp_init_current_idle_task,data
	287	.import smp_callin,code
	288
413059f2	289	#ifndef CONFIG_64BIT
1da177e4 LT	290	smp_callin_rtn:
	291	.proc
	292	.callinfo
	293	break 1,1 /* Break if returned from start_secondary */
	294	nop
	295	nop
	296	.procend
413059f2	297	#endif /!CONFIG_64BIT/
1da177e4 LT	298
	299	/***************************************************************************
	300	* smp_slave_stext is executed by all non-monarch Processors when the Monarch
	301	* pokes the slave CPUs in smp.c:smp_boot_cpus().
	302	*
	303	* Once here, registers values are initialized in order to branch to virtual
	304	* mode. Once all available/eligible CPUs are in virtual mode, all are
	305	* released and start out by executing their own idle task.
	306	*****************************************************************************/
	307	smp_slave_stext:
	308	.proc
	309	.callinfo
	310
	311	/*
	312	** Initialize Space registers
	313	*/
	314	mtsp %r0,%sr4
	315	mtsp %r0,%sr5
	316	mtsp %r0,%sr6
	317	mtsp %r0,%sr7
	318
	319	/* Initialize the SP - monarch sets up smp_init_current_idle_task */
	320	load32 PA(smp_init_current_idle_task),%sp
	321	LDREG 0(%sp),%sp /* load task address */
	322	tophys_r1 %sp
	323	LDREG TASK_THREAD_INFO(%sp),%sp
	324	mtctl %sp,%cr30 /* store in cr30 */
	325	ldo THREAD_SZ_ALGN(%sp),%sp
	326
	327	/* point CPU to kernel page tables */
	328	load32 PA(swapper_pg_dir),%r4
	329	mtctl %r4,%cr24 /* Initialize kernel root pointer */
	330	mtctl %r4,%cr25 /* Initialize user root pointer */
	331
413059f2	332	#ifdef CONFIG_64BIT
1da177e4 LT	333	/* Setup PDCE_PROC entry */
	334	copy %arg0,%r3
	335	#else
	336	/* Load RFI return address in case smp_callin bails */
	337	load32 smp_callin_rtn,%r2
	338	#endif
	339
	340	/* Load RFI target address. */
	341	load32 smp_callin,%r11
	342
	343	/* ok...common code can handle the rest */
	344	b common_stext
	345	nop
	346
	347	.procend
	348	#endif /* CONFIG_SMP */
8e9e9844 HD	349
	350	ENDPROC(stext)
	351
413059f2	352	#ifndef CONFIG_64BIT
54cb27a7	353	.section .data..read_mostly
1da177e4 LT	354
	355	.align 4
	356	.export $global$,data
	357
	358	.type $global$,@object
	359	.size $global$,4
	360	$global$:
	361	.word 0
413059f2	362	#endif /!CONFIG_64BIT/