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1da177e4 LT |
1 | /* |
2 | * linux/arch/parisc/kernel/time.c | |
3 | * | |
4 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
5 | * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King | |
6 | * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org) | |
7 | * | |
8 | * 1994-07-02 Alan Modra | |
9 | * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime | |
10 | * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 | |
11 | * "A Kernel Model for Precision Timekeeping" by Dave Mills | |
12 | */ | |
1da177e4 LT |
13 | #include <linux/errno.h> |
14 | #include <linux/module.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/param.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/time.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/smp.h> | |
24 | #include <linux/profile.h> | |
12df29b6 | 25 | #include <linux/clocksource.h> |
1da177e4 LT |
26 | |
27 | #include <asm/uaccess.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/irq.h> | |
30 | #include <asm/param.h> | |
31 | #include <asm/pdc.h> | |
32 | #include <asm/led.h> | |
33 | ||
34 | #include <linux/timex.h> | |
35 | ||
bed583f7 | 36 | static unsigned long clocktick __read_mostly; /* timer cycles per tick */ |
1da177e4 | 37 | |
1604f318 MW |
38 | /* |
39 | * We keep time on PA-RISC Linux by using the Interval Timer which is | |
40 | * a pair of registers; one is read-only and one is write-only; both | |
41 | * accessed through CR16. The read-only register is 32 or 64 bits wide, | |
42 | * and increments by 1 every CPU clock tick. The architecture only | |
43 | * guarantees us a rate between 0.5 and 2, but all implementations use a | |
44 | * rate of 1. The write-only register is 32-bits wide. When the lowest | |
45 | * 32 bits of the read-only register compare equal to the write-only | |
46 | * register, it raises a maskable external interrupt. Each processor has | |
47 | * an Interval Timer of its own and they are not synchronised. | |
48 | * | |
49 | * We want to generate an interrupt every 1/HZ seconds. So we program | |
50 | * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data | |
51 | * is programmed with the intended time of the next tick. We can be | |
52 | * held off for an arbitrarily long period of time by interrupts being | |
53 | * disabled, so we may miss one or more ticks. | |
54 | */ | |
c7753f18 | 55 | irqreturn_t timer_interrupt(int irq, void *dev_id) |
1da177e4 | 56 | { |
bed583f7 GG |
57 | unsigned long now; |
58 | unsigned long next_tick; | |
1604f318 | 59 | unsigned long cycles_elapsed, ticks_elapsed; |
6e5dc42b GG |
60 | unsigned long cycles_remainder; |
61 | unsigned int cpu = smp_processor_id(); | |
c7753f18 | 62 | struct cpuinfo_parisc *cpuinfo = &cpu_data[cpu]; |
1da177e4 | 63 | |
6b799d92 | 64 | /* gcc can optimize for "read-only" case with a local clocktick */ |
6e5dc42b | 65 | unsigned long cpt = clocktick; |
6b799d92 | 66 | |
be577a52 | 67 | profile_tick(CPU_PROFILING); |
1da177e4 | 68 | |
bed583f7 | 69 | /* Initialize next_tick to the expected tick time. */ |
c7753f18 | 70 | next_tick = cpuinfo->it_value; |
1da177e4 | 71 | |
bed583f7 GG |
72 | /* Get current interval timer. |
73 | * CR16 reads as 64 bits in CPU wide mode. | |
74 | * CR16 reads as 32 bits in CPU narrow mode. | |
1da177e4 | 75 | */ |
bed583f7 | 76 | now = mfctl(16); |
1da177e4 | 77 | |
bed583f7 GG |
78 | cycles_elapsed = now - next_tick; |
79 | ||
6e5dc42b GG |
80 | if ((cycles_elapsed >> 5) < cpt) { |
81 | /* use "cheap" math (add/subtract) instead | |
82 | * of the more expensive div/mul method | |
bed583f7 | 83 | */ |
6b799d92 | 84 | cycles_remainder = cycles_elapsed; |
1604f318 | 85 | ticks_elapsed = 1; |
6e5dc42b GG |
86 | while (cycles_remainder > cpt) { |
87 | cycles_remainder -= cpt; | |
1604f318 | 88 | ticks_elapsed++; |
6e5dc42b | 89 | } |
6b799d92 | 90 | } else { |
6e5dc42b | 91 | cycles_remainder = cycles_elapsed % cpt; |
1604f318 | 92 | ticks_elapsed = 1 + cycles_elapsed / cpt; |
6b799d92 | 93 | } |
bed583f7 GG |
94 | |
95 | /* Can we differentiate between "early CR16" (aka Scenario 1) and | |
96 | * "long delay" (aka Scenario 3)? I don't think so. | |
97 | * | |
98 | * We expected timer_interrupt to be delivered at least a few hundred | |
99 | * cycles after the IT fires. But it's arbitrary how much time passes | |
100 | * before we call it "late". I've picked one second. | |
101 | */ | |
1604f318 | 102 | if (ticks_elapsed > HZ) { |
bed583f7 | 103 | /* Scenario 3: very long delay? bad in any case */ |
6b799d92 | 104 | printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!" |
6e5dc42b | 105 | " cycles %lX rem %lX " |
bed583f7 GG |
106 | " next/now %lX/%lX\n", |
107 | cpu, | |
6e5dc42b | 108 | cycles_elapsed, cycles_remainder, |
bed583f7 | 109 | next_tick, now ); |
bed583f7 GG |
110 | } |
111 | ||
6e5dc42b GG |
112 | /* convert from "division remainder" to "remainder of clock tick" */ |
113 | cycles_remainder = cpt - cycles_remainder; | |
bed583f7 GG |
114 | |
115 | /* Determine when (in CR16 cycles) next IT interrupt will fire. | |
116 | * We want IT to fire modulo clocktick even if we miss/skip some. | |
117 | * But those interrupts don't in fact get delivered that regularly. | |
118 | */ | |
6e5dc42b GG |
119 | next_tick = now + cycles_remainder; |
120 | ||
c7753f18 | 121 | cpuinfo->it_value = next_tick; |
6b799d92 GG |
122 | |
123 | /* Skip one clocktick on purpose if we are likely to miss next_tick. | |
6e5dc42b GG |
124 | * We want to avoid the new next_tick being less than CR16. |
125 | * If that happened, itimer wouldn't fire until CR16 wrapped. | |
126 | * We'll catch the tick we missed on the tick after that. | |
127 | */ | |
128 | if (!(cycles_remainder >> 13)) | |
129 | next_tick += cpt; | |
bed583f7 GG |
130 | |
131 | /* Program the IT when to deliver the next interrupt. */ | |
c7753f18 | 132 | /* Only bottom 32-bits of next_tick are written to cr16. */ |
6b799d92 | 133 | mtctl(next_tick, 16); |
1da177e4 | 134 | |
6e5dc42b GG |
135 | |
136 | /* Done mucking with unreliable delivery of interrupts. | |
137 | * Go do system house keeping. | |
bed583f7 | 138 | */ |
c7753f18 MW |
139 | |
140 | if (!--cpuinfo->prof_counter) { | |
141 | cpuinfo->prof_counter = cpuinfo->prof_multiplier; | |
142 | update_process_times(user_mode(get_irq_regs())); | |
143 | } | |
144 | ||
6e5dc42b GG |
145 | if (cpu == 0) { |
146 | write_seqlock(&xtime_lock); | |
1604f318 | 147 | do_timer(ticks_elapsed); |
6e5dc42b | 148 | write_sequnlock(&xtime_lock); |
1da177e4 | 149 | } |
6e5dc42b | 150 | |
1da177e4 LT |
151 | /* check soft power switch status */ |
152 | if (cpu == 0 && !atomic_read(&power_tasklet.count)) | |
153 | tasklet_schedule(&power_tasklet); | |
154 | ||
155 | return IRQ_HANDLED; | |
156 | } | |
157 | ||
5cd55b0e RC |
158 | |
159 | unsigned long profile_pc(struct pt_regs *regs) | |
160 | { | |
161 | unsigned long pc = instruction_pointer(regs); | |
162 | ||
163 | if (regs->gr[0] & PSW_N) | |
164 | pc -= 4; | |
165 | ||
166 | #ifdef CONFIG_SMP | |
167 | if (in_lock_functions(pc)) | |
168 | pc = regs->gr[2]; | |
169 | #endif | |
170 | ||
171 | return pc; | |
172 | } | |
173 | EXPORT_SYMBOL(profile_pc); | |
174 | ||
175 | ||
12df29b6 | 176 | /* clock source code */ |
1da177e4 | 177 | |
12df29b6 | 178 | static cycle_t read_cr16(void) |
1da177e4 | 179 | { |
12df29b6 | 180 | return get_cycles(); |
1da177e4 LT |
181 | } |
182 | ||
12df29b6 HD |
183 | static struct clocksource clocksource_cr16 = { |
184 | .name = "cr16", | |
185 | .rating = 300, | |
186 | .read = read_cr16, | |
187 | .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), | |
188 | .mult = 0, /* to be set */ | |
189 | .shift = 22, | |
190 | .is_continuous = 1, | |
191 | }; | |
1da177e4 | 192 | |
1da177e4 LT |
193 | |
194 | /* | |
195 | * XXX: We can do better than this. | |
196 | * Returns nanoseconds | |
197 | */ | |
198 | ||
199 | unsigned long long sched_clock(void) | |
200 | { | |
201 | return (unsigned long long)jiffies * (1000000000 / HZ); | |
202 | } | |
203 | ||
204 | ||
56f335c8 GG |
205 | void __init start_cpu_itimer(void) |
206 | { | |
207 | unsigned int cpu = smp_processor_id(); | |
208 | unsigned long next_tick = mfctl(16) + clocktick; | |
209 | ||
210 | mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ | |
211 | ||
212 | cpu_data[cpu].it_value = next_tick; | |
213 | } | |
214 | ||
1da177e4 LT |
215 | void __init time_init(void) |
216 | { | |
1da177e4 | 217 | static struct pdc_tod tod_data; |
12df29b6 | 218 | unsigned long current_cr16_khz; |
1da177e4 LT |
219 | |
220 | clocktick = (100 * PAGE0->mem_10msec) / HZ; | |
1da177e4 | 221 | |
56f335c8 | 222 | start_cpu_itimer(); /* get CPU 0 started */ |
1da177e4 | 223 | |
12df29b6 HD |
224 | /* register at clocksource framework */ |
225 | current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */ | |
226 | clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz, | |
227 | clocksource_cr16.shift); | |
228 | /* lower the rating if we already know its unstable: */ | |
229 | if (num_online_cpus()>1) | |
230 | clocksource_cr16.rating = 200; | |
231 | ||
232 | clocksource_register(&clocksource_cr16); | |
233 | ||
09690b18 KM |
234 | if (pdc_tod_read(&tod_data) == 0) { |
235 | unsigned long flags; | |
236 | ||
237 | write_seqlock_irqsave(&xtime_lock, flags); | |
1da177e4 LT |
238 | xtime.tv_sec = tod_data.tod_sec; |
239 | xtime.tv_nsec = tod_data.tod_usec * 1000; | |
240 | set_normalized_timespec(&wall_to_monotonic, | |
241 | -xtime.tv_sec, -xtime.tv_nsec); | |
09690b18 | 242 | write_sequnlock_irqrestore(&xtime_lock, flags); |
1da177e4 LT |
243 | } else { |
244 | printk(KERN_ERR "Error reading tod clock\n"); | |
245 | xtime.tv_sec = 0; | |
246 | xtime.tv_nsec = 0; | |
247 | } | |
248 | } | |
249 |