projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b4e8c8dd TS |
1 | /* |
| 2 | * Device Tree Source for IBM Embedded PPC 476 Platform | |
| 3 | * | |
| 4 | * Copyright 2010 Torez Smith, IBM Corporation. | |
| 5 | * | |
| 6 | * Based on earlier code: | |
| 7 | * Copyright (c) 2006, 2007 IBM Corp. | |
| 8 | * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> | |
| 9 | * | |
| 10 | * This file is licensed under the terms of the GNU General Public | |
| 11 | * License version 2. This program is licensed "as is" without | |
| 12 | * any warranty of any kind, whether express or implied. | |
| 13 | */ | |
| 14 | ||
| 15 | /dts-v1/; | |
| 16 | ||
| 17 | /memreserve/ 0x01f00000 0x00100000; | |
| 18 | ||
| 19 | / { | |
| 20 | #address-cells = <2>; | |
| 21 | #size-cells = <1>; | |
| 22 | model = "ibm,iss-4xx"; | |
| 23 | compatible = "ibm,iss-4xx"; | |
| 24 | dcr-parent = <&{/cpus/cpu@0}>; | |
| 25 | ||
| 26 | aliases { | |
| 27 | serial0 = &UART0; | |
| 28 | }; | |
| 29 | ||
| 30 | cpus { | |
| 31 | #address-cells = <1>; | |
| 32 | #size-cells = <0>; | |
| 33 | ||
| 34 | cpu@0 { | |
| 35 | device_type = "cpu"; | |
| 36 | model = "PowerPC,4xx"; // real CPU changed in sim | |
| 37 | reg = <0>; | |
| 38 | clock-frequency = <100000000>; // 100Mhz :-) | |
| 39 | timebase-frequency = <100000000>; | |
| 40 | i-cache-line-size = <32>; | |
| 41 | d-cache-line-size = <32>; | |
| 42 | i-cache-size = <32768>; | |
| 43 | d-cache-size = <32768>; | |
| 44 | dcr-controller; | |
| 45 | dcr-access-method = "native"; | |
| 46 | status = "ok"; | |
| 47 | }; | |
| 48 | cpu@1 { | |
| 49 | device_type = "cpu"; | |
| 50 | model = "PowerPC,4xx"; // real CPU changed in sim | |
| 51 | reg = <1>; | |
| 52 | clock-frequency = <100000000>; // 100Mhz :-) | |
| 53 | timebase-frequency = <100000000>; | |
| 54 | i-cache-line-size = <32>; | |
| 55 | d-cache-line-size = <32>; | |
| 56 | i-cache-size = <32768>; | |
| 57 | d-cache-size = <32768>; | |
| 58 | dcr-controller; | |
| 59 | dcr-access-method = "native"; | |
| 60 | status = "disabled"; | |
| 61 | enable-method = "spin-table"; | |
| 62 | cpu-release-addr = <0 0x01f00100>; | |
| 63 | }; | |
| 64 | cpu@2 { | |
| 65 | device_type = "cpu"; | |
| 66 | model = "PowerPC,4xx"; // real CPU changed in sim | |
| 67 | reg = <2>; | |
| 68 | clock-frequency = <100000000>; // 100Mhz :-) | |
| 69 | timebase-frequency = <100000000>; | |
| 70 | i-cache-line-size = <32>; | |
| 71 | d-cache-line-size = <32>; | |
| 72 | i-cache-size = <32768>; | |
| 73 | d-cache-size = <32768>; | |
| 74 | dcr-controller; | |
| 75 | dcr-access-method = "native"; | |
| 76 | status = "disabled"; | |
| 77 | enable-method = "spin-table"; | |
| 78 | cpu-release-addr = <0 0x01f00200>; | |
| 79 | }; | |
| 80 | cpu@3 { | |
| 81 | device_type = "cpu"; | |
| 82 | model = "PowerPC,4xx"; // real CPU changed in sim | |
| 83 | reg = <3>; | |
| 84 | clock-frequency = <100000000>; // 100Mhz :-) | |
| 85 | timebase-frequency = <100000000>; | |
| 86 | i-cache-line-size = <32>; | |
| 87 | d-cache-line-size = <32>; | |
| 88 | i-cache-size = <32768>; | |
| 89 | d-cache-size = <32768>; | |
| 90 | dcr-controller; | |
| 91 | dcr-access-method = "native"; | |
| 92 | status = "disabled"; | |
| 93 | enable-method = "spin-table"; | |
| 94 | cpu-release-addr = <0 0x01f00300>; | |
| 95 | }; | |
| 96 | }; | |
| 97 | ||
| 98 | memory { | |
| 99 | device_type = "memory"; | |
| 100 | reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage | |
| 101 | ||
| 102 | }; | |
| 103 | ||
| 104 | MPIC: interrupt-controller { | |
| 105 | compatible = "chrp,open-pic"; | |
| 106 | interrupt-controller; | |
| 107 | dcr-reg = <0xffc00000 0x00030000>; | |
| 108 | #address-cells = <0>; | |
| 109 | #size-cells = <0>; | |
| 110 | #interrupt-cells = <2>; | |
| 111 | ||
| 112 | }; | |
| 113 | ||
| 114 | plb { | |
| 115 | compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ | |
| 116 | #address-cells = <2>; | |
| 117 | #size-cells = <1>; | |
| 118 | ranges; | |
| 119 | clock-frequency = <0>; // Filled in by zImage | |
| 120 | ||
| 121 | POB0: opb { | |
| 122 | compatible = "ibm,opb-4xx", "ibm,opb"; | |
| 123 | #address-cells = <1>; | |
| 124 | #size-cells = <1>; | |
| 125 | /* Wish there was a nicer way of specifying a full 32-bit | |
| 126 | range */ | |
| 127 | ranges = <0x00000000 0x00000001 0x00000000 0x80000000 | |
| 128 | 0x80000000 0x00000001 0x80000000 0x80000000>; | |
| 129 | clock-frequency = <0>; // Filled in by zImage | |
| 130 | UART0: serial@40000200 { | |
| 131 | device_type = "serial"; | |
| 132 | compatible = "ns16550a"; | |
| 133 | reg = <0x40000200 0x00000008>; | |
| 134 | virtual-reg = <0xe0000200>; | |
| 135 | clock-frequency = <11059200>; | |
| 136 | current-speed = <115200>; | |
| 137 | interrupt-parent = <&MPIC>; | |
| 138 | interrupts = <0x0 0x2>; | |
| 139 | }; | |
| 140 | }; | |
| 141 | }; | |
| 142 | ||
| 143 | nvrtc { | |
| 144 | compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; | |
| 145 | reg = <0 0xEF703000 0x2000>; | |
| 146 | }; | |
| 147 | iss-block { | |
| 148 | compatible = "ibm,iss-sim-block-device"; | |
| 149 | reg = <0 0xEF701000 0x1000>; | |
| 150 | }; | |
| 151 | ||
| 152 | chosen { | |
| 153 | linux,stdout-path = "/plb/opb/serial@40000200"; | |
| 154 | }; | |
| 155 | }; |