Commit | Line | Data |
---|---|---|
3de9c9cd BH |
1 | /* |
2 | * Device Tree Source for AMCC Katmai eval board | |
3 | * | |
4 | * Copyright (c) 2006, 2007 IBM Corp. | |
5 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
6 | * | |
7 | * Copyright (c) 2006, 2007 IBM Corp. | |
8 | * Josh Boyer <jwboyer@linux.vnet.ibm.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without | |
12 | * any warranty of any kind, whether express or implied. | |
13 | */ | |
14 | ||
71f34979 DG |
15 | /dts-v1/; |
16 | ||
3de9c9cd BH |
17 | / { |
18 | #address-cells = <2>; | |
59e1d495 | 19 | #size-cells = <2>; |
3de9c9cd BH |
20 | model = "amcc,katmai"; |
21 | compatible = "amcc,katmai"; | |
71f34979 | 22 | dcr-parent = <&{/cpus/cpu@0}>; |
3de9c9cd | 23 | |
8aaed98c SR |
24 | aliases { |
25 | ethernet0 = &EMAC0; | |
26 | serial0 = &UART0; | |
27 | serial1 = &UART1; | |
28 | serial2 = &UART2; | |
29 | }; | |
30 | ||
3de9c9cd BH |
31 | cpus { |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | ||
72fda114 | 35 | cpu@0 { |
3de9c9cd | 36 | device_type = "cpu"; |
72fda114 | 37 | model = "PowerPC,440SPe"; |
71f34979 | 38 | reg = <0x00000000>; |
3de9c9cd BH |
39 | clock-frequency = <0>; /* Filled in by zImage */ |
40 | timebase-frequency = <0>; /* Filled in by zImage */ | |
71f34979 DG |
41 | i-cache-line-size = <32>; |
42 | d-cache-line-size = <32>; | |
43 | i-cache-size = <32768>; | |
44 | d-cache-size = <32768>; | |
3de9c9cd BH |
45 | dcr-controller; |
46 | dcr-access-method = "native"; | |
499f4902 | 47 | reset-type = <2>; /* Use chip-reset */ |
3de9c9cd BH |
48 | }; |
49 | }; | |
50 | ||
51 | memory { | |
52 | device_type = "memory"; | |
59e1d495 | 53 | reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */ |
3de9c9cd BH |
54 | }; |
55 | ||
56 | UIC0: interrupt-controller0 { | |
57 | compatible = "ibm,uic-440spe","ibm,uic"; | |
58 | interrupt-controller; | |
59 | cell-index = <0>; | |
71f34979 | 60 | dcr-reg = <0x0c0 0x009>; |
3de9c9cd BH |
61 | #address-cells = <0>; |
62 | #size-cells = <0>; | |
63 | #interrupt-cells = <2>; | |
64 | }; | |
65 | ||
66 | UIC1: interrupt-controller1 { | |
67 | compatible = "ibm,uic-440spe","ibm,uic"; | |
68 | interrupt-controller; | |
69 | cell-index = <1>; | |
71f34979 | 70 | dcr-reg = <0x0d0 0x009>; |
3de9c9cd BH |
71 | #address-cells = <0>; |
72 | #size-cells = <0>; | |
73 | #interrupt-cells = <2>; | |
71f34979 | 74 | interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ |
3de9c9cd BH |
75 | interrupt-parent = <&UIC0>; |
76 | }; | |
77 | ||
78 | UIC2: interrupt-controller2 { | |
79 | compatible = "ibm,uic-440spe","ibm,uic"; | |
80 | interrupt-controller; | |
81 | cell-index = <2>; | |
71f34979 | 82 | dcr-reg = <0x0e0 0x009>; |
3de9c9cd BH |
83 | #address-cells = <0>; |
84 | #size-cells = <0>; | |
85 | #interrupt-cells = <2>; | |
71f34979 | 86 | interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ |
3de9c9cd BH |
87 | interrupt-parent = <&UIC0>; |
88 | }; | |
89 | ||
90 | UIC3: interrupt-controller3 { | |
91 | compatible = "ibm,uic-440spe","ibm,uic"; | |
92 | interrupt-controller; | |
93 | cell-index = <3>; | |
71f34979 | 94 | dcr-reg = <0x0f0 0x009>; |
3de9c9cd BH |
95 | #address-cells = <0>; |
96 | #size-cells = <0>; | |
97 | #interrupt-cells = <2>; | |
71f34979 | 98 | interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ |
3de9c9cd BH |
99 | interrupt-parent = <&UIC0>; |
100 | }; | |
101 | ||
102 | SDR0: sdr { | |
103 | compatible = "ibm,sdr-440spe"; | |
71f34979 | 104 | dcr-reg = <0x00e 0x002>; |
3de9c9cd BH |
105 | }; |
106 | ||
107 | CPR0: cpr { | |
108 | compatible = "ibm,cpr-440spe"; | |
71f34979 | 109 | dcr-reg = <0x00c 0x002>; |
3de9c9cd BH |
110 | }; |
111 | ||
070bae1f AG |
112 | MQ0: mq { |
113 | compatible = "ibm,mq-440spe"; | |
114 | dcr-reg = <0x040 0x020>; | |
115 | }; | |
116 | ||
3de9c9cd BH |
117 | plb { |
118 | compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; | |
119 | #address-cells = <2>; | |
120 | #size-cells = <1>; | |
59e1d495 | 121 | /* addr-child addr-parent size */ |
070bae1f AG |
122 | ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000 |
123 | 0x4 0x00200000 0x4 0x00200000 0x00000400 | |
124 | 0x4 0xe0000000 0x4 0xe0000000 0x20000000 | |
59e1d495 SR |
125 | 0xc 0x00000000 0xc 0x00000000 0x20000000 |
126 | 0xd 0x00000000 0xd 0x00000000 0x80000000 | |
127 | 0xd 0x80000000 0xd 0x80000000 0x80000000 | |
128 | 0xe 0x00000000 0xe 0x00000000 0x80000000 | |
129 | 0xe 0x80000000 0xe 0x80000000 0x80000000 | |
130 | 0xf 0x00000000 0xf 0x00000000 0x80000000 | |
131 | 0xf 0x80000000 0xf 0x80000000 0x80000000>; | |
3de9c9cd BH |
132 | clock-frequency = <0>; /* Filled in by zImage */ |
133 | ||
134 | SDRAM0: sdram { | |
135 | compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; | |
71f34979 | 136 | dcr-reg = <0x010 0x002>; |
3de9c9cd BH |
137 | }; |
138 | ||
139 | MAL0: mcmal { | |
140 | compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; | |
71f34979 | 141 | dcr-reg = <0x180 0x062>; |
3de9c9cd BH |
142 | num-tx-chans = <2>; |
143 | num-rx-chans = <1>; | |
144 | interrupt-parent = <&MAL0>; | |
71f34979 | 145 | interrupts = <0x0 0x1 0x2 0x3 0x4>; |
3de9c9cd BH |
146 | #interrupt-cells = <1>; |
147 | #address-cells = <0>; | |
148 | #size-cells = <0>; | |
71f34979 DG |
149 | interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4 |
150 | /*RXEOB*/ 0x1 &UIC1 0x7 0x4 | |
151 | /*SERR*/ 0x2 &UIC1 0x1 0x4 | |
152 | /*TXDE*/ 0x3 &UIC1 0x2 0x4 | |
153 | /*RXDE*/ 0x4 &UIC1 0x3 0x4>; | |
3de9c9cd BH |
154 | }; |
155 | ||
156 | POB0: opb { | |
3db3ba03 | 157 | compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; |
3de9c9cd BH |
158 | #address-cells = <1>; |
159 | #size-cells = <1>; | |
036f290d | 160 | ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>; |
3db3ba03 | 161 | clock-frequency = <0>; /* Filled in by zImage */ |
3de9c9cd BH |
162 | |
163 | EBC0: ebc { | |
164 | compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; | |
71f34979 | 165 | dcr-reg = <0x012 0x002>; |
3de9c9cd BH |
166 | #address-cells = <2>; |
167 | #size-cells = <1>; | |
168 | clock-frequency = <0>; /* Filled in by zImage */ | |
036f290d | 169 | /* ranges property is supplied by U-Boot */ |
71f34979 | 170 | interrupts = <0x5 0x1>; |
3de9c9cd | 171 | interrupt-parent = <&UIC1>; |
036f290d SR |
172 | |
173 | nor_flash@0,0 { | |
174 | compatible = "cfi-flash"; | |
175 | bank-width = <2>; | |
176 | reg = <0x00000000 0x00000000 0x01000000>; | |
177 | #address-cells = <1>; | |
178 | #size-cells = <1>; | |
179 | partition@0 { | |
180 | label = "kernel"; | |
181 | reg = <0x00000000 0x001e0000>; | |
182 | }; | |
183 | partition@1e0000 { | |
184 | label = "dtb"; | |
185 | reg = <0x001e0000 0x00020000>; | |
186 | }; | |
187 | partition@200000 { | |
188 | label = "root"; | |
189 | reg = <0x00200000 0x00200000>; | |
190 | }; | |
191 | partition@400000 { | |
192 | label = "user"; | |
193 | reg = <0x00400000 0x00b60000>; | |
194 | }; | |
195 | partition@f60000 { | |
196 | label = "env"; | |
197 | reg = <0x00f60000 0x00040000>; | |
198 | }; | |
199 | partition@fa0000 { | |
200 | label = "u-boot"; | |
201 | reg = <0x00fa0000 0x00060000>; | |
202 | }; | |
203 | }; | |
3de9c9cd BH |
204 | }; |
205 | ||
036f290d | 206 | UART0: serial@f0000200 { |
3db3ba03 SR |
207 | device_type = "serial"; |
208 | compatible = "ns16550"; | |
036f290d | 209 | reg = <0xf0000200 0x00000008>; |
71f34979 | 210 | virtual-reg = <0xa0000200>; |
3db3ba03 | 211 | clock-frequency = <0>; /* Filled in by zImage */ |
71f34979 | 212 | current-speed = <115200>; |
3db3ba03 | 213 | interrupt-parent = <&UIC0>; |
71f34979 | 214 | interrupts = <0x0 0x4>; |
3db3ba03 | 215 | }; |
3de9c9cd | 216 | |
036f290d | 217 | UART1: serial@f0000300 { |
3db3ba03 SR |
218 | device_type = "serial"; |
219 | compatible = "ns16550"; | |
036f290d | 220 | reg = <0xf0000300 0x00000008>; |
71f34979 | 221 | virtual-reg = <0xa0000300>; |
3db3ba03 SR |
222 | clock-frequency = <0>; |
223 | current-speed = <0>; | |
224 | interrupt-parent = <&UIC0>; | |
71f34979 | 225 | interrupts = <0x1 0x4>; |
3db3ba03 | 226 | }; |
3de9c9cd BH |
227 | |
228 | ||
036f290d | 229 | UART2: serial@f0000600 { |
3db3ba03 SR |
230 | device_type = "serial"; |
231 | compatible = "ns16550"; | |
036f290d | 232 | reg = <0xf0000600 0x00000008>; |
71f34979 | 233 | virtual-reg = <0xa0000600>; |
3db3ba03 SR |
234 | clock-frequency = <0>; |
235 | current-speed = <0>; | |
236 | interrupt-parent = <&UIC1>; | |
71f34979 | 237 | interrupts = <0x5 0x4>; |
3db3ba03 | 238 | }; |
3de9c9cd | 239 | |
036f290d | 240 | IIC0: i2c@f0000400 { |
3de9c9cd | 241 | compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; |
036f290d | 242 | reg = <0xf0000400 0x00000014>; |
3de9c9cd | 243 | interrupt-parent = <&UIC0>; |
71f34979 | 244 | interrupts = <0x2 0x4>; |
3de9c9cd BH |
245 | }; |
246 | ||
036f290d | 247 | IIC1: i2c@f0000500 { |
3de9c9cd | 248 | compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; |
036f290d | 249 | reg = <0xf0000500 0x00000014>; |
3de9c9cd | 250 | interrupt-parent = <&UIC0>; |
71f34979 | 251 | interrupts = <0x3 0x4>; |
3de9c9cd BH |
252 | }; |
253 | ||
036f290d | 254 | EMAC0: ethernet@f0000800 { |
71f34979 | 255 | linux,network-index = <0x0>; |
3de9c9cd BH |
256 | device_type = "network"; |
257 | compatible = "ibm,emac-440spe", "ibm,emac4"; | |
258 | interrupt-parent = <&UIC1>; | |
71f34979 | 259 | interrupts = <0x1c 0x4 0x1d 0x4>; |
036f290d | 260 | reg = <0xf0000800 0x00000074>; |
3de9c9cd BH |
261 | local-mac-address = [000000000000]; |
262 | mal-device = <&MAL0>; | |
263 | mal-tx-channel = <0>; | |
264 | mal-rx-channel = <0>; | |
265 | cell-index = <0>; | |
71f34979 DG |
266 | max-frame-size = <9000>; |
267 | rx-fifo-size = <4096>; | |
268 | tx-fifo-size = <2048>; | |
3de9c9cd | 269 | phy-mode = "gmii"; |
71f34979 | 270 | phy-map = <0x00000000>; |
3de9c9cd BH |
271 | has-inverted-stacr-oc; |
272 | has-new-stacr-staopc; | |
273 | }; | |
274 | }; | |
275 | ||
276 | PCIX0: pci@c0ec00000 { | |
277 | device_type = "pci"; | |
278 | #interrupt-cells = <1>; | |
279 | #size-cells = <2>; | |
280 | #address-cells = <3>; | |
281 | compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix"; | |
282 | primary; | |
283 | large-inbound-windows; | |
284 | enable-msi-hole; | |
036f290d SR |
285 | reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ |
286 | 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ | |
287 | 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ | |
288 | 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ | |
289 | 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ | |
3de9c9cd BH |
290 | |
291 | /* Outbound ranges, one memory and one IO, | |
292 | * later cannot be changed | |
293 | */ | |
71f34979 DG |
294 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 |
295 | 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; | |
3de9c9cd | 296 | |
2e991cfa | 297 | /* Inbound 4GB range starting at 0 */ |
298 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; | |
3de9c9cd BH |
299 | |
300 | /* This drives busses 0 to 0xf */ | |
71f34979 | 301 | bus-range = <0x0 0xf>; |
3de9c9cd BH |
302 | |
303 | /* | |
304 | * On Katmai, the following PCI-X interrupts signals | |
305 | * have to be enabled via jumpers (only INTA is | |
306 | * enabled per default): | |
307 | * | |
308 | * INTB: J3: 1-2 | |
309 | * INTC: J2: 1-2 | |
310 | * INTD: J1: 1-2 | |
311 | */ | |
71f34979 | 312 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
3de9c9cd BH |
313 | interrupt-map = < |
314 | /* IDSEL 1 */ | |
71f34979 DG |
315 | 0x800 0x0 0x0 0x1 &UIC1 0x14 0x8 |
316 | 0x800 0x0 0x0 0x2 &UIC1 0x13 0x8 | |
317 | 0x800 0x0 0x0 0x3 &UIC1 0x12 0x8 | |
318 | 0x800 0x0 0x0 0x4 &UIC1 0x11 0x8 | |
3de9c9cd BH |
319 | >; |
320 | }; | |
321 | ||
322 | PCIE0: pciex@d00000000 { | |
323 | device_type = "pci"; | |
324 | #interrupt-cells = <1>; | |
325 | #size-cells = <2>; | |
326 | #address-cells = <3>; | |
accf5ef2 | 327 | compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; |
3de9c9cd | 328 | primary; |
71f34979 DG |
329 | port = <0x0>; /* port number */ |
330 | reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ | |
331 | 0x0000000c 0x10000000 0x00001000>; /* Registers */ | |
332 | dcr-reg = <0x100 0x020>; | |
333 | sdr-base = <0x300>; | |
3de9c9cd BH |
334 | |
335 | /* Outbound ranges, one memory and one IO, | |
336 | * later cannot be changed | |
337 | */ | |
71f34979 DG |
338 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 |
339 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; | |
3de9c9cd | 340 | |
2e991cfa | 341 | /* Inbound 4GB range starting at 0 */ |
342 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; | |
3de9c9cd | 343 | |
2e991cfa | 344 | /* This drives busses 0x10 to 0x1f */ |
71f34979 | 345 | bus-range = <0x10 0x1f>; |
3de9c9cd BH |
346 | |
347 | /* Legacy interrupts (note the weird polarity, the bridge seems | |
348 | * to invert PCIe legacy interrupts). | |
349 | * We are de-swizzling here because the numbers are actually for | |
350 | * port of the root complex virtual P2P bridge. But I want | |
351 | * to avoid putting a node for it in the tree, so the numbers | |
352 | * below are basically de-swizzled numbers. | |
353 | * The real slot is on idsel 0, so the swizzling is 1:1 | |
354 | */ | |
71f34979 | 355 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
3de9c9cd | 356 | interrupt-map = < |
71f34979 DG |
357 | 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ |
358 | 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ | |
359 | 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ | |
360 | 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; | |
3de9c9cd BH |
361 | }; |
362 | ||
363 | PCIE1: pciex@d20000000 { | |
364 | device_type = "pci"; | |
365 | #interrupt-cells = <1>; | |
366 | #size-cells = <2>; | |
367 | #address-cells = <3>; | |
accf5ef2 | 368 | compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; |
3de9c9cd | 369 | primary; |
71f34979 DG |
370 | port = <0x1>; /* port number */ |
371 | reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ | |
372 | 0x0000000c 0x10001000 0x00001000>; /* Registers */ | |
373 | dcr-reg = <0x120 0x020>; | |
374 | sdr-base = <0x340>; | |
3de9c9cd BH |
375 | |
376 | /* Outbound ranges, one memory and one IO, | |
377 | * later cannot be changed | |
378 | */ | |
71f34979 DG |
379 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 |
380 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; | |
3de9c9cd | 381 | |
2e991cfa | 382 | /* Inbound 4GB range starting at 0 */ |
383 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; | |
3de9c9cd | 384 | |
2e991cfa | 385 | /* This drives busses 0x20 to 0x2f */ |
71f34979 | 386 | bus-range = <0x20 0x2f>; |
3de9c9cd BH |
387 | |
388 | /* Legacy interrupts (note the weird polarity, the bridge seems | |
389 | * to invert PCIe legacy interrupts). | |
390 | * We are de-swizzling here because the numbers are actually for | |
391 | * port of the root complex virtual P2P bridge. But I want | |
392 | * to avoid putting a node for it in the tree, so the numbers | |
393 | * below are basically de-swizzled numbers. | |
394 | * The real slot is on idsel 0, so the swizzling is 1:1 | |
395 | */ | |
71f34979 | 396 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
3de9c9cd | 397 | interrupt-map = < |
71f34979 DG |
398 | 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ |
399 | 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ | |
400 | 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ | |
401 | 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; | |
3de9c9cd BH |
402 | }; |
403 | ||
404 | PCIE2: pciex@d40000000 { | |
405 | device_type = "pci"; | |
406 | #interrupt-cells = <1>; | |
407 | #size-cells = <2>; | |
408 | #address-cells = <3>; | |
accf5ef2 | 409 | compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; |
3de9c9cd | 410 | primary; |
71f34979 DG |
411 | port = <0x2>; /* port number */ |
412 | reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */ | |
413 | 0x0000000c 0x10002000 0x00001000>; /* Registers */ | |
414 | dcr-reg = <0x140 0x020>; | |
415 | sdr-base = <0x370>; | |
3de9c9cd BH |
416 | |
417 | /* Outbound ranges, one memory and one IO, | |
418 | * later cannot be changed | |
419 | */ | |
71f34979 DG |
420 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000 |
421 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>; | |
3de9c9cd | 422 | |
2e991cfa | 423 | /* Inbound 4GB range starting at 0 */ |
424 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; | |
3de9c9cd | 425 | |
2e991cfa | 426 | /* This drives busses 0x30 to 0x3f */ |
71f34979 | 427 | bus-range = <0x30 0x3f>; |
3de9c9cd BH |
428 | |
429 | /* Legacy interrupts (note the weird polarity, the bridge seems | |
430 | * to invert PCIe legacy interrupts). | |
431 | * We are de-swizzling here because the numbers are actually for | |
432 | * port of the root complex virtual P2P bridge. But I want | |
433 | * to avoid putting a node for it in the tree, so the numbers | |
434 | * below are basically de-swizzled numbers. | |
435 | * The real slot is on idsel 0, so the swizzling is 1:1 | |
436 | */ | |
71f34979 | 437 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
3de9c9cd | 438 | interrupt-map = < |
71f34979 DG |
439 | 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */ |
440 | 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */ | |
441 | 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */ | |
442 | 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; | |
3de9c9cd | 443 | }; |
070bae1f | 444 | |
3fb79338 RS |
445 | MSI: ppc4xx-msi@400300000 { |
446 | compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; | |
447 | reg = < 0x4 0x00300000 0x100>; | |
448 | sdr-base = <0x3B0>; | |
449 | msi-data = <0x00000000>; | |
450 | msi-mask = <0x44440000>; | |
451 | interrupt-count = <3>; | |
452 | interrupts =<0 1 2 3>; | |
453 | interrupt-parent = <&UIC0>; | |
454 | #interrupt-cells = <1>; | |
455 | #address-cells = <0>; | |
456 | #size-cells = <0>; | |
457 | interrupt-map = <0 &UIC0 0xC 1 | |
458 | 1 &UIC0 0x0D 1 | |
459 | 2 &UIC0 0x0E 1 | |
460 | 3 &UIC0 0x0F 1>; | |
461 | }; | |
462 | ||
070bae1f AG |
463 | I2O: i2o@400100000 { |
464 | compatible = "ibm,i2o-440spe"; | |
465 | reg = <0x00000004 0x00100000 0x100>; | |
466 | dcr-reg = <0x060 0x020>; | |
467 | }; | |
468 | ||
469 | DMA0: dma0@400100100 { | |
470 | compatible = "ibm,dma-440spe"; | |
471 | cell-index = <0>; | |
472 | reg = <0x00000004 0x00100100 0x100>; | |
473 | dcr-reg = <0x060 0x020>; | |
474 | interrupt-parent = <&DMA0>; | |
475 | interrupts = <0 1>; | |
476 | #interrupt-cells = <1>; | |
477 | #address-cells = <0>; | |
478 | #size-cells = <0>; | |
479 | interrupt-map = < | |
480 | 0 &UIC0 0x14 4 | |
481 | 1 &UIC1 0x16 4>; | |
482 | }; | |
483 | ||
484 | DMA1: dma1@400100200 { | |
485 | compatible = "ibm,dma-440spe"; | |
486 | cell-index = <1>; | |
487 | reg = <0x00000004 0x00100200 0x100>; | |
488 | dcr-reg = <0x060 0x020>; | |
489 | interrupt-parent = <&DMA1>; | |
490 | interrupts = <0 1>; | |
491 | #interrupt-cells = <1>; | |
492 | #address-cells = <0>; | |
493 | #size-cells = <0>; | |
494 | interrupt-map = < | |
495 | 0 &UIC0 0x16 4 | |
496 | 1 &UIC1 0x16 4>; | |
497 | }; | |
498 | ||
499 | xor-accel@400200000 { | |
500 | compatible = "amcc,xor-accelerator"; | |
501 | reg = <0x00000004 0x00200000 0x400>; | |
502 | interrupt-parent = <&UIC1>; | |
503 | interrupts = <0x1f 4>; | |
504 | }; | |
3de9c9cd BH |
505 | }; |
506 | ||
507 | chosen { | |
036f290d | 508 | linux,stdout-path = "/plb/opb/serial@f0000200"; |
3de9c9cd BH |
509 | }; |
510 | }; |