[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8548cds.dts

/*
 * MPC8548 CDS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "MPC8548CDS";
	compatible = "MPC8548CDS", "MPC85xxCDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8548@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8548@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		bus-frequency = <0>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <10>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8548-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,8548-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8548-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			eeprom@50 {
				compatible = "atmel,24c64";
				reg = <0x50>;
			};

			eeprom@56 {
				compatible = "atmel,24c64";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c64";
				reg = <0x57>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			eeprom@50 {
				compatible = "atmel,24c64";
				reg = <0x50>;
			};
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
					device_type = "ethernet-phy";
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
					device_type = "ethernet-phy";
				};
				phy2: ethernet-phy@2 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x2>;
					device_type = "ethernet-phy";
				};
				phy3: ethernet-phy@3 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x3>;
					device_type = "ethernet-phy";
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet2: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy2>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet3: ethernet@27000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <3>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			ranges = <0x0 0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi3>;
			phy-handle = <&phy3>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi3: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities reg
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		crypto@30000 {
			compatible = "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0xfe>;
			fsl,descriptor-types-mask = <0x12b0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pci@e0008000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x4 (PCIX Slot 2) */
			0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x2000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x5 (PCIX Slot 3) */
			0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
			0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
			0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
			0x2800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x6 (PCIX Slot 4) */
			0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
			0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
			0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
			0x3000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x8 (PCIX Slot 5) */
			0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x4000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0xC (Tsi310 bridge) */
			0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x6000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x14 (Slot 2) */
			0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x15 (Slot 3) */
			0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x16 (Slot 4) */
			0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
			0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
			0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
			0xb000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x18 (Slot 5) */
			0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xc000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
			0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";

		pci_bridge@1c {
			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
			interrupt-map = <

				/* IDSEL 0x00 (PrPMC Site) */
				0000 0x0 0x0 0x1 &mpic 0x0 0x1
				0000 0x0 0x0 0x2 &mpic 0x1 0x1
				0000 0x0 0x0 0x3 &mpic 0x2 0x1
				0000 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x04 (VIA chip) */
				0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
				0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
				0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
				0x2000 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x05 (8139) */
				0x2800 0x0 0x0 0x1 &mpic 0x1 0x1

				/* IDSEL 0x06 (Slot 6) */
				0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
				0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
				0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
				0x3000 0x0 0x0 0x4 &mpic 0x1 0x1

				/* IDESL 0x07 (Slot 7) */
				0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
				0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
				0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
				0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;

			reg = <0xe000 0x0 0x0 0x0 0x0>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000
				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x80000>;
			clock-frequency = <33333333>;

			isa@4 {
				device_type = "isa";
				#interrupt-cells = <2>;
				#size-cells = <1>;
				#address-cells = <2>;
				reg = <0x2000 0x0 0x0 0x0 0x0>;
				ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
				interrupt-parent = <&i8259>;

				i8259: interrupt-controller@20 {
					interrupt-controller;
					device_type = "interrupt-controller";
					reg = <0x1 0x20 0x2
					       0x1 0xa0 0x2
					       0x1 0x4d0 0x2>;
					#address-cells = <0>;
					#interrupt-cells = <2>;
					compatible = "chrp,iic";
					interrupts = <0 1>;
					interrupt-parent = <&mpic>;
				};

				rtc@70 {
					compatible = "pnpPNP,b00";
					reg = <0x1 0x70 0x2>;
				};
			};
		};
	};

	pci1: pci@e0009000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
	};

	pci2: pcie@e000a000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x0 (PEX) */
			00000 0x0 0x0 0x1 &mpic 0x0 0x1
			00000 0x0 0x0 0x2 &mpic 0x1 0x1
			00000 0x0 0x0 0x3 &mpic 0x2 0x1
			00000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
		clock-frequency = <33333333>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};
Commit	Line	Data
2654d638	1	/*
02edff59	2	* MPC8548 CDS Device Tree Source
2654d638	3	*
32f960e9	4	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
2654d638 AF	13
	14	/ {
	15	model = "MPC8548CDS";
52094879	16	compatible = "MPC8548CDS", "MPC85xxCDS";
2654d638 AF	17	#address-cells = <1>;
2654d638 AF	18	#size-cells = <1>;
2654d638	19
ea082fa9 KG	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
ea082fa9 KG	23	ethernet2 = &enet2;
ea082fa9 KG	24	ethernet3 = &enet3;
ea082fa9 KG	25	serial0 = &serial0;
	26	serial1 = &serial1;
	27	pci0 = &pci0;
	28	pci1 = &pci1;
	29	pci2 = &pci2;
	30	};
	31
2654d638	32	cpus {
2654d638 AF	33	#address-cells = <1>;
2654d638 AF	34	#size-cells = <0>;
2654d638 AF	35
	36	PowerPC,8548@0 {
	37	device_type = "cpu";
32f960e9 KG	38	reg = <0x0>;
	39	d-cache-line-size = <32>; // 32 bytes
	40	i-cache-line-size = <32>; // 32 bytes
	41	d-cache-size = <0x8000>; // L1, 32K
	42	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	43	timebase-frequency = <0>; // 33 MHz, from uboot
	44	bus-frequency = <0>; // 166 MHz
	45	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	46	next-level-cache = <&L2>;
2654d638 AF	47	};
	48	};
	49
	50	memory {
	51	device_type = "memory";
32f960e9	52	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	53	};
	54
	55	soc8548@e0000000 {
	56	#address-cells = <1>;
	57	#size-cells = <1>;
2654d638	58	device_type = "soc";
cf0d19fb	59	compatible = "simple-bus";
32f960e9	60	ranges = <0x0 0xe0000000 0x100000>;
2654d638 AF	61	bus-frequency = <0>;
2654d638 AF	62
e1a22897 KG	63	ecm-law@0 {
	64	compatible = "fsl,ecm-law";
	65	reg = <0x0 0x1000>;
	66	fsl,num-laws = <10>;
	67	};
	68
	69	ecm@1000 {
	70	compatible = "fsl,mpc8548-ecm", "fsl,ecm";
	71	reg = <0x1000 0x1000>;
	72	interrupts = <17 2>;
	73	interrupt-parent = <&mpic>;
	74	};
	75
50cf6707 DJ	76	memory-controller@2000 {
50cf6707 DJ	77	compatible = "fsl,8548-memory-controller";
32f960e9	78	reg = <0x2000 0x1000>;
50cf6707	79	interrupt-parent = <&mpic>;
32f960e9	80	interrupts = <18 2>;
50cf6707 DJ	81	};
50cf6707 DJ	82
c054065b	83	L2: l2-cache-controller@20000 {
50cf6707	84	compatible = "fsl,8548-l2-cache-controller";
32f960e9 KG	85	reg = <0x20000 0x1000>;
	86	cache-line-size = <32>; // 32 bytes
	87	cache-size = <0x80000>; // L2, 512K
50cf6707	88	interrupt-parent = <&mpic>;
32f960e9	89	interrupts = <16 2>;
50cf6707 DJ	90	};
50cf6707 DJ	91
2654d638	92	i2c@3000 {
ec9686c4 KG	93	#address-cells = <1>;
	94	#size-cells = <0>;
	95	cell-index = <0>;
2654d638	96	compatible = "fsl-i2c";
32f960e9 KG	97	reg = <0x3000 0x100>;
32f960e9 KG	98	interrupts = <43 2>;
52094879	99	interrupt-parent = <&mpic>;
2654d638	100	dfsrr;
c69328d4 AV	101
	102	eeprom@50 {
	103	compatible = "atmel,24c64";
	104	reg = <0x50>;
	105	};
	106
	107	eeprom@56 {
	108	compatible = "atmel,24c64";
	109	reg = <0x56>;
	110	};
	111
	112	eeprom@57 {
	113	compatible = "atmel,24c64";
	114	reg = <0x57>;
	115	};
2654d638 AF	116	};
2654d638 AF	117
ec9686c4 KG	118	i2c@3100 {
	119	#address-cells = <1>;
	120	#size-cells = <0>;
	121	cell-index = <1>;
	122	compatible = "fsl-i2c";
32f960e9 KG	123	reg = <0x3100 0x100>;
32f960e9 KG	124	interrupts = <43 2>;
ec9686c4 KG	125	interrupt-parent = <&mpic>;
ec9686c4 KG	126	dfsrr;
c69328d4 AV	127
	128	eeprom@50 {
	129	compatible = "atmel,24c64";
	130	reg = <0x50>;
	131	};
ec9686c4 KG	132	};
ec9686c4 KG	133
dee80553 KG	134	dma@21300 {
	135	#address-cells = <1>;
	136	#size-cells = <1>;
	137	compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
	138	reg = <0x21300 0x4>;
	139	ranges = <0x0 0x21100 0x200>;
	140	cell-index = <0>;
	141	dma-channel@0 {
	142	compatible = "fsl,mpc8548-dma-channel",
	143	"fsl,eloplus-dma-channel";
	144	reg = <0x0 0x80>;
	145	cell-index = <0>;
	146	interrupt-parent = <&mpic>;
	147	interrupts = <20 2>;
	148	};
	149	dma-channel@80 {
	150	compatible = "fsl,mpc8548-dma-channel",
	151	"fsl,eloplus-dma-channel";
	152	reg = <0x80 0x80>;
	153	cell-index = <1>;
	154	interrupt-parent = <&mpic>;
	155	interrupts = <21 2>;
	156	};
	157	dma-channel@100 {
	158	compatible = "fsl,mpc8548-dma-channel",
	159	"fsl,eloplus-dma-channel";
	160	reg = <0x100 0x80>;
	161	cell-index = <2>;
	162	interrupt-parent = <&mpic>;
	163	interrupts = <22 2>;
	164	};
	165	dma-channel@180 {
	166	compatible = "fsl,mpc8548-dma-channel",
	167	"fsl,eloplus-dma-channel";
	168	reg = <0x180 0x80>;
	169	cell-index = <3>;
	170	interrupt-parent = <&mpic>;
	171	interrupts = <23 2>;
	172	};
	173	};
	174
e77b28eb	175	enet0: ethernet@24000 {
84ba4a58 AV	176	#address-cells = <1>;
84ba4a58 AV	177	#size-cells = <1>;
e77b28eb	178	cell-index = <0>;
2654d638 AF	179	device_type = "network";
	180	model = "eTSEC";
	181	compatible = "gianfar";
32f960e9	182	reg = <0x24000 0x1000>;
84ba4a58	183	ranges = <0x0 0x24000 0x1000>;
eae98266	184	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	185	interrupts = <29 2 30 2 34 2>;
52094879	186	interrupt-parent = <&mpic>;
b31a1d8b	187	tbi-handle = <&tbi0>;
52094879	188	phy-handle = <&phy0>;
84ba4a58 AV	189
	190	mdio@520 {
	191	#address-cells = <1>;
	192	#size-cells = <0>;
	193	compatible = "fsl,gianfar-mdio";
	194	reg = <0x520 0x20>;
	195
	196	phy0: ethernet-phy@0 {
	197	interrupt-parent = <&mpic>;
	198	interrupts = <5 1>;
	199	reg = <0x0>;
	200	device_type = "ethernet-phy";
	201	};
	202	phy1: ethernet-phy@1 {
	203	interrupt-parent = <&mpic>;
	204	interrupts = <5 1>;
	205	reg = <0x1>;
	206	device_type = "ethernet-phy";
	207	};
	208	phy2: ethernet-phy@2 {
	209	interrupt-parent = <&mpic>;
	210	interrupts = <5 1>;
	211	reg = <0x2>;
	212	device_type = "ethernet-phy";
	213	};
	214	phy3: ethernet-phy@3 {
	215	interrupt-parent = <&mpic>;
	216	interrupts = <5 1>;
	217	reg = <0x3>;
	218	device_type = "ethernet-phy";
	219	};
	220	tbi0: tbi-phy@11 {
	221	reg = <0x11>;
	222	device_type = "tbi-phy";
	223	};
	224	};
2654d638 AF	225	};
2654d638 AF	226
e77b28eb	227	enet1: ethernet@25000 {
84ba4a58 AV	228	#address-cells = <1>;
84ba4a58 AV	229	#size-cells = <1>;
e77b28eb	230	cell-index = <1>;
2654d638 AF	231	device_type = "network";
	232	model = "eTSEC";
	233	compatible = "gianfar";
32f960e9	234	reg = <0x25000 0x1000>;
84ba4a58	235	ranges = <0x0 0x25000 0x1000>;
eae98266	236	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	237	interrupts = <35 2 36 2 40 2>;
52094879	238	interrupt-parent = <&mpic>;
b31a1d8b	239	tbi-handle = <&tbi1>;
52094879	240	phy-handle = <&phy1>;
84ba4a58 AV	241
	242	mdio@520 {
	243	#address-cells = <1>;
	244	#size-cells = <0>;
	245	compatible = "fsl,gianfar-tbi";
	246	reg = <0x520 0x20>;
	247
	248	tbi1: tbi-phy@11 {
	249	reg = <0x11>;
	250	device_type = "tbi-phy";
	251	};
	252	};
2654d638 AF	253	};
2654d638 AF	254
e77b28eb	255	enet2: ethernet@26000 {
84ba4a58 AV	256	#address-cells = <1>;
84ba4a58 AV	257	#size-cells = <1>;
e77b28eb	258	cell-index = <2>;
2654d638 AF	259	device_type = "network";
	260	model = "eTSEC";
	261	compatible = "gianfar";
32f960e9	262	reg = <0x26000 0x1000>;
84ba4a58	263	ranges = <0x0 0x26000 0x1000>;
eae98266	264	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	265	interrupts = <31 2 32 2 33 2>;
52094879	266	interrupt-parent = <&mpic>;
b31a1d8b	267	tbi-handle = <&tbi2>;
52094879	268	phy-handle = <&phy2>;
84ba4a58 AV	269
	270	mdio@520 {
	271	#address-cells = <1>;
	272	#size-cells = <0>;
	273	compatible = "fsl,gianfar-tbi";
	274	reg = <0x520 0x20>;
	275
	276	tbi2: tbi-phy@11 {
	277	reg = <0x11>;
	278	device_type = "tbi-phy";
	279	};
	280	};
2654d638 AF	281	};
2654d638 AF	282
e77b28eb	283	enet3: ethernet@27000 {
84ba4a58 AV	284	#address-cells = <1>;
84ba4a58 AV	285	#size-cells = <1>;
e77b28eb	286	cell-index = <3>;
2654d638 AF	287	device_type = "network";
	288	model = "eTSEC";
	289	compatible = "gianfar";
32f960e9	290	reg = <0x27000 0x1000>;
84ba4a58	291	ranges = <0x0 0x27000 0x1000>;
eae98266	292	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	293	interrupts = <37 2 38 2 39 2>;
52094879	294	interrupt-parent = <&mpic>;
b31a1d8b	295	tbi-handle = <&tbi3>;
52094879	296	phy-handle = <&phy3>;
84ba4a58 AV	297
	298	mdio@520 {
	299	#address-cells = <1>;
	300	#size-cells = <0>;
	301	compatible = "fsl,gianfar-tbi";
	302	reg = <0x520 0x20>;
	303
	304	tbi3: tbi-phy@11 {
	305	reg = <0x11>;
	306	device_type = "tbi-phy";
	307	};
	308	};
2654d638	309	};
2654d638	310
ea082fa9 KG	311	serial0: serial@4500 {
ea082fa9 KG	312	cell-index = <0>;
2654d638 AF	313	device_type = "serial";
2654d638 AF	314	compatible = "ns16550";
32f960e9	315	reg = <0x4500 0x100>; // reg base, size
6af01257	316	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	317	interrupts = <42 2>;
52094879	318	interrupt-parent = <&mpic>;
2654d638 AF	319	};
2654d638 AF	320
ea082fa9 KG	321	serial1: serial@4600 {
ea082fa9 KG	322	cell-index = <1>;
2654d638 AF	323	device_type = "serial";
2654d638 AF	324	compatible = "ns16550";
32f960e9	325	reg = <0x4600 0x100>; // reg base, size
6af01257	326	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	327	interrupts = <42 2>;
52094879	328	interrupt-parent = <&mpic>;
2654d638 AF	329	};
2654d638 AF	330
68fb0d20 RZ	331	global-utilities@e0000 { //global utilities reg
68fb0d20 RZ	332	compatible = "fsl,mpc8548-guts";
32f960e9	333	reg = <0xe0000 0x1000>;
68fb0d20 RZ	334	fsl,has-rstcr;
	335	};
	336
3fd44736 KP	337	crypto@30000 {
	338	compatible = "fsl,sec2.1", "fsl,sec2.0";
	339	reg = <0x30000 0x10000>;
	340	interrupts = <45 2>;
	341	interrupt-parent = <&mpic>;
	342	fsl,num-channels = <4>;
	343	fsl,channel-fifo-len = <24>;
	344	fsl,exec-units-mask = <0xfe>;
	345	fsl,descriptor-types-mask = <0x12b0ebf>;
	346	};
	347
1b3c5cda	348	mpic: pic@40000 {
1b3c5cda KG	349	interrupt-controller;
	350	#address-cells = <0>;
	351	#interrupt-cells = <2>;
32f960e9	352	reg = <0x40000 0x40000>;
1b3c5cda KG	353	compatible = "chrp,open-pic";
1b3c5cda KG	354	device_type = "open-pic";
1b3c5cda KG	355	};
	356	};
	357
ea082fa9	358	pci0: pci@e0008000 {
32f960e9	359	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	360	interrupt-map = <
1b3c5cda KG	361	/* IDSEL 0x4 (PCIX Slot 2) */
32f960e9 KG	362	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
	363	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
	364	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
	365	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	366
1b3c5cda KG	367	/* IDSEL 0x5 (PCIX Slot 3) */
32f960e9 KG	368	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
	369	0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
	370	0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
	371	0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	372
1b3c5cda KG	373	/* IDSEL 0x6 (PCIX Slot 4) */
32f960e9 KG	374	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
	375	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
	376	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
	377	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	378
1b3c5cda KG	379	/* IDSEL 0x8 (PCIX Slot 5) */
32f960e9 KG	380	0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
	381	0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
	382	0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
	383	0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	384
1b3c5cda KG	385	/* IDSEL 0xC (Tsi310 bridge) */
32f960e9 KG	386	0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
	387	0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
	388	0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
	389	0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	390
1b3c5cda KG	391	/* IDSEL 0x14 (Slot 2) */
32f960e9 KG	392	0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
	393	0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
	394	0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
	395	0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	396
1b3c5cda KG	397	/* IDSEL 0x15 (Slot 3) */
32f960e9 KG	398	0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
	399	0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
	400	0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
	401	0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	402
1b3c5cda KG	403	/* IDSEL 0x16 (Slot 4) */
32f960e9 KG	404	0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
	405	0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
	406	0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
	407	0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	408
1b3c5cda KG	409	/* IDSEL 0x18 (Slot 5) */
32f960e9 KG	410	0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
	411	0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
	412	0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
	413	0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	414
1b3c5cda KG	415	/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
32f960e9 KG	416	0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
	417	0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
	418	0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
	419	0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	420
1b3c5cda KG	421	interrupt-parent = <&mpic>;
32f960e9	422	interrupts = <24 2>;
1b3c5cda	423	bus-range = <0 0>;
32f960e9 KG	424	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	425	0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
	426	clock-frequency = <66666666>;
1b3c5cda KG	427	#interrupt-cells = <1>;
	428	#size-cells = <2>;
	429	#address-cells = <3>;
32f960e9	430	reg = <0xe0008000 0x1000>;
1b3c5cda KG	431	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	432	device_type = "pci";
	433
	434	pci_bridge@1c {
32f960e9	435	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2654d638 AF	436	interrupt-map = <
2654d638 AF	437
1b3c5cda	438	/* IDSEL 0x00 (PrPMC Site) */
32f960e9 KG	439	0000 0x0 0x0 0x1 &mpic 0x0 0x1
	440	0000 0x0 0x0 0x2 &mpic 0x1 0x1
	441	0000 0x0 0x0 0x3 &mpic 0x2 0x1
	442	0000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	443
1b3c5cda KG	444	/* IDSEL 0x04 (VIA chip) */
32f960e9 KG	445	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
	446	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
	447	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
	448	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	449
1b3c5cda KG	450	/* IDSEL 0x05 (8139) */
32f960e9	451	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
1b3c5cda KG	452
1b3c5cda KG	453	/* IDSEL 0x06 (Slot 6) */
32f960e9 KG	454	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
	455	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
	456	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
	457	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	458
1b3c5cda KG	459	/* IDESL 0x07 (Slot 7) */
32f960e9 KG	460	0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
	461	0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
	462	0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
	463	0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
1b3c5cda	464
32f960e9	465	reg = <0xe000 0x0 0x0 0x0 0x0>;
2654d638 AF	466	#interrupt-cells = <1>;
	467	#size-cells = <2>;
	468	#address-cells = <3>;
32f960e9 KG	469	ranges = <0x2000000 0x0 0x80000000
	470	0x2000000 0x0 0x80000000
	471	0x0 0x20000000
	472	0x1000000 0x0 0x0
	473	0x1000000 0x0 0x0
	474	0x0 0x80000>;
	475	clock-frequency = <33333333>;
2654d638	476
1b3c5cda KG	477	isa@4 {
	478	device_type = "isa";
	479	#interrupt-cells = <2>;
	480	#size-cells = <1>;
	481	#address-cells = <2>;
32f960e9 KG	482	reg = <0x2000 0x0 0x0 0x0 0x0>;
32f960e9 KG	483	ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
1b3c5cda KG	484	interrupt-parent = <&i8259>;
	485
	486	i8259: interrupt-controller@20 {
	487	interrupt-controller;
	488	device_type = "interrupt-controller";
32f960e9 KG	489	reg = <0x1 0x20 0x2
	490	0x1 0xa0 0x2
	491	0x1 0x4d0 0x2>;
1b3c5cda	492	#address-cells = <0>;
6af01257	493	#interrupt-cells = <2>;
1b3c5cda KG	494	compatible = "chrp,iic";
	495	interrupts = <0 1>;
	496	interrupt-parent = <&mpic>;
6af01257	497	};
2654d638	498
1b3c5cda KG	499	rtc@70 {
1b3c5cda KG	500	compatible = "pnpPNP,b00";
32f960e9	501	reg = <0x1 0x70 0x2>;
1b3c5cda KG	502	};
1b3c5cda KG	503	};
02edff59	504	};
1b3c5cda	505	};
02edff59	506
ea082fa9	507	pci1: pci@e0009000 {
32f960e9	508	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	509	interrupt-map = <
	510
	511	/* IDSEL 0x15 */
32f960e9 KG	512	0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
	513	0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
	514	0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
	515	0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	516
1b3c5cda KG	517	interrupt-parent = <&mpic>;
32f960e9	518	interrupts = <25 2>;
1b3c5cda	519	bus-range = <0 0>;
32f960e9 KG	520	ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	521	0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
	522	clock-frequency = <66666666>;
1b3c5cda KG	523	#interrupt-cells = <1>;
	524	#size-cells = <2>;
	525	#address-cells = <3>;
32f960e9	526	reg = <0xe0009000 0x1000>;
1b3c5cda KG	527	compatible = "fsl,mpc8540-pci";
	528	device_type = "pci";
	529	};
02edff59	530
ea082fa9	531	pci2: pcie@e000a000 {
32f960e9	532	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	533	interrupt-map = <
	534
	535	/* IDSEL 0x0 (PEX) */
32f960e9 KG	536	00000 0x0 0x0 0x1 &mpic 0x0 0x1
	537	00000 0x0 0x0 0x2 &mpic 0x1 0x1
	538	00000 0x0 0x0 0x3 &mpic 0x2 0x1
	539	00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	540
1b3c5cda KG	541	interrupt-parent = <&mpic>;
32f960e9 KG	542	interrupts = <26 2>;
	543	bus-range = <0 255>;
	544	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
ad16880d	545	0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
32f960e9	546	clock-frequency = <33333333>;
1b3c5cda KG	547	#interrupt-cells = <1>;
	548	#size-cells = <2>;
	549	#address-cells = <3>;
32f960e9	550	reg = <0xe000a000 0x1000>;
1b3c5cda KG	551	compatible = "fsl,mpc8548-pcie";
	552	device_type = "pci";
	553	pcie@0 {
32f960e9	554	reg = <0x0 0x0 0x0 0x0 0x0>;
02edff59 RZ	555	#size-cells = <2>;
02edff59 RZ	556	#address-cells = <3>;
2654d638	557	device_type = "pci";
32f960e9 KG	558	ranges = <0x2000000 0x0 0xa0000000
	559	0x2000000 0x0 0xa0000000
	560	0x0 0x20000000
2654d638	561
32f960e9 KG	562	0x1000000 0x0 0x0
32f960e9 KG	563	0x1000000 0x0 0x0
ad16880d	564	0x0 0x100000>;
2654d638 AF	565	};
	566	};
	567	};