[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8548cds.dts

/*
 * MPC8548 CDS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "MPC8548CDS";
	compatible = "MPC8548CDS", "MPC85xxCDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
/*
		ethernet2 = &enet2;
		ethernet3 = &enet3;
*/
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8548@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8548@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xe0000000 0x100000>;
		reg = <0xe0000000 0x1000>;	// CCSRBAR
		bus-frequency = <0>;

		memory-controller@2000 {
			compatible = "fsl,8548-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		l2-cache-controller@20000 {
			compatible = "fsl,8548-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1>;
				reg = <0x0>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1>;
				reg = <0x1>;
				device_type = "ethernet-phy";
			};
			phy2: ethernet-phy@2 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1>;
				reg = <0x3>;
				device_type = "ethernet-phy";
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
		};

/* eTSEC 3/4 are currently broken
		enet2: ethernet@26000 {
			cell-index = <2>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
		};

		enet3: ethernet@27000 {
			cell-index = <3>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy3>;
		};
 */

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities reg
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		mpic: pic@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
                        big-endian;
		};
	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x4 (PCIX Slot 2) */
			0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x2000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x5 (PCIX Slot 3) */
			0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
			0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
			0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
			0x2800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x6 (PCIX Slot 4) */
			0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
			0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
			0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
			0x3000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x8 (PCIX Slot 5) */
			0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x4000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0xC (Tsi310 bridge) */
			0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x6000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x14 (Slot 2) */
			0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x15 (Slot 3) */
			0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x16 (Slot 4) */
			0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
			0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
			0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
			0xb000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x18 (Slot 5) */
			0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xc000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
			0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
			0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
			0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
			0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";

		pci_bridge@1c {
			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
			interrupt-map = <

				/* IDSEL 0x00 (PrPMC Site) */
				0000 0x0 0x0 0x1 &mpic 0x0 0x1
				0000 0x0 0x0 0x2 &mpic 0x1 0x1
				0000 0x0 0x0 0x3 &mpic 0x2 0x1
				0000 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x04 (VIA chip) */
				0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
				0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
				0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
				0x2000 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x05 (8139) */
				0x2800 0x0 0x0 0x1 &mpic 0x1 0x1

				/* IDSEL 0x06 (Slot 6) */
				0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
				0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
				0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
				0x3000 0x0 0x0 0x4 &mpic 0x1 0x1

				/* IDESL 0x07 (Slot 7) */
				0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
				0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
				0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
				0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;

			reg = <0xe000 0x0 0x0 0x0 0x0>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000
				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x80000>;
			clock-frequency = <33333333>;

			isa@4 {
				device_type = "isa";
				#interrupt-cells = <2>;
				#size-cells = <1>;
				#address-cells = <2>;
				reg = <0x2000 0x0 0x0 0x0 0x0>;
				ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
				interrupt-parent = <&i8259>;

				i8259: interrupt-controller@20 {
					interrupt-controller;
					device_type = "interrupt-controller";
					reg = <0x1 0x20 0x2
					       0x1 0xa0 0x2
					       0x1 0x4d0 0x2>;
					#address-cells = <0>;
					#interrupt-cells = <2>;
					compatible = "chrp,iic";
					interrupts = <0 1>;
					interrupt-parent = <&mpic>;
				};

				rtc@70 {
					compatible = "pnpPNP,b00";
					reg = <0x1 0x70 0x2>;
				};
			};
		};
	};

	pci1: pci@e0009000 {
		cell-index = <1>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
	};

	pci2: pcie@e000a000 {
		cell-index = <2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x0 (PEX) */
			00000 0x0 0x0 0x1 &mpic 0x0 0x1
			00000 0x0 0x0 0x2 &mpic 0x1 0x1
			00000 0x0 0x0 0x3 &mpic 0x2 0x1
			00000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
		clock-frequency = <33333333>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};
Commit	Line	Data
2654d638	1	/*
02edff59	2	* MPC8548 CDS Device Tree Source
2654d638	3	*
32f960e9	4	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
2654d638 AF	13
	14	/ {
	15	model = "MPC8548CDS";
52094879	16	compatible = "MPC8548CDS", "MPC85xxCDS";
2654d638 AF	17	#address-cells = <1>;
2654d638 AF	18	#size-cells = <1>;
2654d638	19
ea082fa9 KG	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	/*
	24	ethernet2 = &enet2;
	25	ethernet3 = &enet3;
	26	*/
	27	serial0 = &serial0;
	28	serial1 = &serial1;
	29	pci0 = &pci0;
	30	pci1 = &pci1;
	31	pci2 = &pci2;
	32	};
	33
2654d638	34	cpus {
2654d638 AF	35	#address-cells = <1>;
2654d638 AF	36	#size-cells = <0>;
2654d638 AF	37
	38	PowerPC,8548@0 {
	39	device_type = "cpu";
32f960e9 KG	40	reg = <0x0>;
	41	d-cache-line-size = <32>; // 32 bytes
	42	i-cache-line-size = <32>; // 32 bytes
	43	d-cache-size = <0x8000>; // L1, 32K
	44	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	45	timebase-frequency = <0>; // 33 MHz, from uboot
	46	bus-frequency = <0>; // 166 MHz
	47	clock-frequency = <0>; // 825 MHz, from uboot
2654d638 AF	48	};
	49	};
	50
	51	memory {
	52	device_type = "memory";
32f960e9	53	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	54	};
	55
	56	soc8548@e0000000 {
	57	#address-cells = <1>;
	58	#size-cells = <1>;
2654d638	59	device_type = "soc";
32f960e9 KG	60	ranges = <0x0 0xe0000000 0x100000>;
32f960e9 KG	61	reg = <0xe0000000 0x1000>; // CCSRBAR
2654d638 AF	62	bus-frequency = <0>;
2654d638 AF	63
50cf6707 DJ	64	memory-controller@2000 {
50cf6707 DJ	65	compatible = "fsl,8548-memory-controller";
32f960e9	66	reg = <0x2000 0x1000>;
50cf6707	67	interrupt-parent = <&mpic>;
32f960e9	68	interrupts = <18 2>;
50cf6707 DJ	69	};
	70
	71	l2-cache-controller@20000 {
	72	compatible = "fsl,8548-l2-cache-controller";
32f960e9 KG	73	reg = <0x20000 0x1000>;
	74	cache-line-size = <32>; // 32 bytes
	75	cache-size = <0x80000>; // L2, 512K
50cf6707	76	interrupt-parent = <&mpic>;
32f960e9	77	interrupts = <16 2>;
50cf6707 DJ	78	};
50cf6707 DJ	79
2654d638	80	i2c@3000 {
ec9686c4 KG	81	#address-cells = <1>;
	82	#size-cells = <0>;
	83	cell-index = <0>;
2654d638	84	compatible = "fsl-i2c";
32f960e9 KG	85	reg = <0x3000 0x100>;
32f960e9 KG	86	interrupts = <43 2>;
52094879	87	interrupt-parent = <&mpic>;
2654d638 AF	88	dfsrr;
	89	};
	90
ec9686c4 KG	91	i2c@3100 {
	92	#address-cells = <1>;
	93	#size-cells = <0>;
	94	cell-index = <1>;
	95	compatible = "fsl-i2c";
32f960e9 KG	96	reg = <0x3100 0x100>;
32f960e9 KG	97	interrupts = <43 2>;
ec9686c4 KG	98	interrupt-parent = <&mpic>;
	99	dfsrr;
	100	};
	101
2654d638 AF	102	mdio@24520 {
	103	#address-cells = <1>;
	104	#size-cells = <0>;
e77b28eb	105	compatible = "fsl,gianfar-mdio";
32f960e9	106	reg = <0x24520 0x20>;
e77b28eb	107
52094879 KG	108	phy0: ethernet-phy@0 {
52094879 KG	109	interrupt-parent = <&mpic>;
58fe255f	110	interrupts = <5 1>;
32f960e9	111	reg = <0x0>;
2654d638 AF	112	device_type = "ethernet-phy";
2654d638 AF	113	};
52094879 KG	114	phy1: ethernet-phy@1 {
52094879 KG	115	interrupt-parent = <&mpic>;
58fe255f	116	interrupts = <5 1>;
32f960e9	117	reg = <0x1>;
2654d638 AF	118	device_type = "ethernet-phy";
2654d638 AF	119	};
52094879 KG	120	phy2: ethernet-phy@2 {
52094879 KG	121	interrupt-parent = <&mpic>;
58fe255f	122	interrupts = <5 1>;
32f960e9	123	reg = <0x2>;
2654d638 AF	124	device_type = "ethernet-phy";
2654d638 AF	125	};
52094879 KG	126	phy3: ethernet-phy@3 {
52094879 KG	127	interrupt-parent = <&mpic>;
58fe255f	128	interrupts = <5 1>;
32f960e9	129	reg = <0x3>;
2654d638 AF	130	device_type = "ethernet-phy";
	131	};
	132	};
	133
e77b28eb KG	134	enet0: ethernet@24000 {
e77b28eb KG	135	cell-index = <0>;
2654d638 AF	136	device_type = "network";
	137	model = "eTSEC";
	138	compatible = "gianfar";
32f960e9	139	reg = <0x24000 0x1000>;
eae98266	140	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	141	interrupts = <29 2 30 2 34 2>;
52094879 KG	142	interrupt-parent = <&mpic>;
52094879 KG	143	phy-handle = <&phy0>;
2654d638 AF	144	};
2654d638 AF	145
e77b28eb KG	146	enet1: ethernet@25000 {
e77b28eb KG	147	cell-index = <1>;
2654d638 AF	148	device_type = "network";
	149	model = "eTSEC";
	150	compatible = "gianfar";
32f960e9	151	reg = <0x25000 0x1000>;
eae98266	152	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	153	interrupts = <35 2 36 2 40 2>;
52094879 KG	154	interrupt-parent = <&mpic>;
52094879 KG	155	phy-handle = <&phy1>;
2654d638 AF	156	};
2654d638 AF	157
52094879	158	/* eTSEC 3/4 are currently broken
e77b28eb KG	159	enet2: ethernet@26000 {
e77b28eb KG	160	cell-index = <2>;
2654d638 AF	161	device_type = "network";
	162	model = "eTSEC";
	163	compatible = "gianfar";
32f960e9	164	reg = <0x26000 0x1000>;
eae98266	165	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	166	interrupts = <31 2 32 2 33 2>;
52094879 KG	167	interrupt-parent = <&mpic>;
52094879 KG	168	phy-handle = <&phy2>;
2654d638 AF	169	};
2654d638 AF	170
e77b28eb KG	171	enet3: ethernet@27000 {
e77b28eb KG	172	cell-index = <3>;
2654d638 AF	173	device_type = "network";
	174	model = "eTSEC";
	175	compatible = "gianfar";
32f960e9	176	reg = <0x27000 0x1000>;
eae98266	177	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	178	interrupts = <37 2 38 2 39 2>;
52094879 KG	179	interrupt-parent = <&mpic>;
52094879 KG	180	phy-handle = <&phy3>;
2654d638 AF	181	};
	182	*/
	183
ea082fa9 KG	184	serial0: serial@4500 {
ea082fa9 KG	185	cell-index = <0>;
2654d638 AF	186	device_type = "serial";
2654d638 AF	187	compatible = "ns16550";
32f960e9	188	reg = <0x4500 0x100>; // reg base, size
6af01257	189	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	190	interrupts = <42 2>;
52094879	191	interrupt-parent = <&mpic>;
2654d638 AF	192	};
2654d638 AF	193
ea082fa9 KG	194	serial1: serial@4600 {
ea082fa9 KG	195	cell-index = <1>;
2654d638 AF	196	device_type = "serial";
2654d638 AF	197	compatible = "ns16550";
32f960e9	198	reg = <0x4600 0x100>; // reg base, size
6af01257	199	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	200	interrupts = <42 2>;
52094879	201	interrupt-parent = <&mpic>;
2654d638 AF	202	};
2654d638 AF	203
68fb0d20 RZ	204	global-utilities@e0000 { //global utilities reg
68fb0d20 RZ	205	compatible = "fsl,mpc8548-guts";
32f960e9	206	reg = <0xe0000 0x1000>;
68fb0d20 RZ	207	fsl,has-rstcr;
	208	};
	209
1b3c5cda KG	210	mpic: pic@40000 {
	211	clock-frequency = <0>;
	212	interrupt-controller;
	213	#address-cells = <0>;
	214	#interrupt-cells = <2>;
32f960e9	215	reg = <0x40000 0x40000>;
1b3c5cda KG	216	compatible = "chrp,open-pic";
	217	device_type = "open-pic";
	218	big-endian;
	219	};
	220	};
	221
ea082fa9 KG	222	pci0: pci@e0008000 {
ea082fa9 KG	223	cell-index = <0>;
32f960e9	224	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	225	interrupt-map = <
1b3c5cda KG	226	/* IDSEL 0x4 (PCIX Slot 2) */
32f960e9 KG	227	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
	228	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
	229	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
	230	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	231
1b3c5cda KG	232	/* IDSEL 0x5 (PCIX Slot 3) */
32f960e9 KG	233	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
	234	0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
	235	0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
	236	0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	237
1b3c5cda KG	238	/* IDSEL 0x6 (PCIX Slot 4) */
32f960e9 KG	239	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
	240	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
	241	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
	242	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	243
1b3c5cda KG	244	/* IDSEL 0x8 (PCIX Slot 5) */
32f960e9 KG	245	0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
	246	0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
	247	0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
	248	0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	249
1b3c5cda KG	250	/* IDSEL 0xC (Tsi310 bridge) */
32f960e9 KG	251	0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
	252	0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
	253	0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
	254	0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	255
1b3c5cda KG	256	/* IDSEL 0x14 (Slot 2) */
32f960e9 KG	257	0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
	258	0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
	259	0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
	260	0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	261
1b3c5cda KG	262	/* IDSEL 0x15 (Slot 3) */
32f960e9 KG	263	0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
	264	0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
	265	0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
	266	0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	267
1b3c5cda KG	268	/* IDSEL 0x16 (Slot 4) */
32f960e9 KG	269	0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
	270	0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
	271	0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
	272	0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	273
1b3c5cda KG	274	/* IDSEL 0x18 (Slot 5) */
32f960e9 KG	275	0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
	276	0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
	277	0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
	278	0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	279
1b3c5cda KG	280	/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
32f960e9 KG	281	0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
	282	0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
	283	0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
	284	0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	285
1b3c5cda KG	286	interrupt-parent = <&mpic>;
32f960e9	287	interrupts = <24 2>;
1b3c5cda	288	bus-range = <0 0>;
32f960e9 KG	289	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	290	0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
	291	clock-frequency = <66666666>;
1b3c5cda KG	292	#interrupt-cells = <1>;
	293	#size-cells = <2>;
	294	#address-cells = <3>;
32f960e9	295	reg = <0xe0008000 0x1000>;
1b3c5cda KG	296	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	297	device_type = "pci";
	298
	299	pci_bridge@1c {
32f960e9	300	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2654d638 AF	301	interrupt-map = <
2654d638 AF	302
1b3c5cda	303	/* IDSEL 0x00 (PrPMC Site) */
32f960e9 KG	304	0000 0x0 0x0 0x1 &mpic 0x0 0x1
	305	0000 0x0 0x0 0x2 &mpic 0x1 0x1
	306	0000 0x0 0x0 0x3 &mpic 0x2 0x1
	307	0000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	308
1b3c5cda KG	309	/* IDSEL 0x04 (VIA chip) */
32f960e9 KG	310	0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
	311	0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
	312	0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
	313	0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	314
1b3c5cda KG	315	/* IDSEL 0x05 (8139) */
32f960e9	316	0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
1b3c5cda KG	317
1b3c5cda KG	318	/* IDSEL 0x06 (Slot 6) */
32f960e9 KG	319	0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
	320	0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
	321	0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
	322	0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	323
1b3c5cda KG	324	/* IDESL 0x07 (Slot 7) */
32f960e9 KG	325	0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
	326	0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
	327	0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
	328	0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
1b3c5cda	329
32f960e9	330	reg = <0xe000 0x0 0x0 0x0 0x0>;
2654d638 AF	331	#interrupt-cells = <1>;
	332	#size-cells = <2>;
	333	#address-cells = <3>;
32f960e9 KG	334	ranges = <0x2000000 0x0 0x80000000
	335	0x2000000 0x0 0x80000000
	336	0x0 0x20000000
	337	0x1000000 0x0 0x0
	338	0x1000000 0x0 0x0
	339	0x0 0x80000>;
	340	clock-frequency = <33333333>;
2654d638	341
1b3c5cda KG	342	isa@4 {
	343	device_type = "isa";
	344	#interrupt-cells = <2>;
	345	#size-cells = <1>;
	346	#address-cells = <2>;
32f960e9 KG	347	reg = <0x2000 0x0 0x0 0x0 0x0>;
32f960e9 KG	348	ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
1b3c5cda KG	349	interrupt-parent = <&i8259>;
	350
	351	i8259: interrupt-controller@20 {
	352	interrupt-controller;
	353	device_type = "interrupt-controller";
32f960e9 KG	354	reg = <0x1 0x20 0x2
	355	0x1 0xa0 0x2
	356	0x1 0x4d0 0x2>;
1b3c5cda	357	#address-cells = <0>;
6af01257	358	#interrupt-cells = <2>;
1b3c5cda KG	359	compatible = "chrp,iic";
	360	interrupts = <0 1>;
	361	interrupt-parent = <&mpic>;
6af01257	362	};
2654d638	363
1b3c5cda KG	364	rtc@70 {
1b3c5cda KG	365	compatible = "pnpPNP,b00";
32f960e9	366	reg = <0x1 0x70 0x2>;
1b3c5cda KG	367	};
1b3c5cda KG	368	};
02edff59	369	};
1b3c5cda	370	};
02edff59	371
ea082fa9 KG	372	pci1: pci@e0009000 {
ea082fa9 KG	373	cell-index = <1>;
32f960e9	374	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	375	interrupt-map = <
	376
	377	/* IDSEL 0x15 */
32f960e9 KG	378	0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
	379	0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
	380	0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
	381	0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	382
1b3c5cda KG	383	interrupt-parent = <&mpic>;
32f960e9	384	interrupts = <25 2>;
1b3c5cda	385	bus-range = <0 0>;
32f960e9 KG	386	ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	387	0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
	388	clock-frequency = <66666666>;
1b3c5cda KG	389	#interrupt-cells = <1>;
	390	#size-cells = <2>;
	391	#address-cells = <3>;
32f960e9	392	reg = <0xe0009000 0x1000>;
1b3c5cda KG	393	compatible = "fsl,mpc8540-pci";
	394	device_type = "pci";
	395	};
02edff59	396
ea082fa9 KG	397	pci2: pcie@e000a000 {
ea082fa9 KG	398	cell-index = <2>;
32f960e9	399	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	400	interrupt-map = <
	401
	402	/* IDSEL 0x0 (PEX) */
32f960e9 KG	403	00000 0x0 0x0 0x1 &mpic 0x0 0x1
	404	00000 0x0 0x0 0x2 &mpic 0x1 0x1
	405	00000 0x0 0x0 0x3 &mpic 0x2 0x1
	406	00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda KG	407
1b3c5cda KG	408	interrupt-parent = <&mpic>;
32f960e9 KG	409	interrupts = <26 2>;
	410	bus-range = <0 255>;
	411	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
ad16880d	412	0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
32f960e9	413	clock-frequency = <33333333>;
1b3c5cda KG	414	#interrupt-cells = <1>;
	415	#size-cells = <2>;
	416	#address-cells = <3>;
32f960e9	417	reg = <0xe000a000 0x1000>;
1b3c5cda KG	418	compatible = "fsl,mpc8548-pcie";
	419	device_type = "pci";
	420	pcie@0 {
32f960e9	421	reg = <0x0 0x0 0x0 0x0 0x0>;
02edff59 RZ	422	#size-cells = <2>;
02edff59 RZ	423	#address-cells = <3>;
2654d638	424	device_type = "pci";
32f960e9 KG	425	ranges = <0x2000000 0x0 0xa0000000
	426	0x2000000 0x0 0xa0000000
	427	0x0 0x20000000
2654d638	428
32f960e9 KG	429	0x1000000 0x0 0x0
32f960e9 KG	430	0x1000000 0x0 0x0
ad16880d	431	0x0 0x100000>;
2654d638 AF	432	};
	433	};
	434	};