Commit | Line | Data |
---|---|---|
172ca926 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. |
cb3bc9d0 | 3 | * Copyright 2001-2012 IBM Corporation. |
1da177e4 LT |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
172ca926 | 9 | * |
1da177e4 LT |
10 | * This program is distributed in the hope that it will be useful, |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
172ca926 | 14 | * |
1da177e4 LT |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
8b8da358 BH |
20 | #ifndef _POWERPC_EEH_H |
21 | #define _POWERPC_EEH_H | |
88ced031 | 22 | #ifdef __KERNEL__ |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/init.h> |
25 | #include <linux/list.h> | |
26 | #include <linux/string.h> | |
5a71978e | 27 | #include <linux/time.h> |
05ec424e | 28 | #include <linux/atomic.h> |
1da177e4 LT |
29 | |
30 | struct pci_dev; | |
827c1a6c | 31 | struct pci_bus; |
1da177e4 | 32 | struct device_node; |
1da177e4 LT |
33 | |
34 | #ifdef CONFIG_EEH | |
35 | ||
8a5ad356 | 36 | /* EEH subsystem flags */ |
dc561fb9 GS |
37 | #define EEH_ENABLED 0x01 /* EEH enabled */ |
38 | #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */ | |
39 | #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */ | |
40 | #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */ | |
41 | #define EEH_ENABLE_IO_FOR_LOG 0x10 /* Enable IO for log */ | |
8a5ad356 | 42 | |
26833a50 GS |
43 | /* |
44 | * Delay for PE reset, all in ms | |
45 | * | |
46 | * PCI specification has reset hold time of 100 milliseconds. | |
47 | * We have 250 milliseconds here. The PCI bus settlement time | |
48 | * is specified as 1.5 seconds and we have 1.8 seconds. | |
49 | */ | |
50 | #define EEH_PE_RST_HOLD_TIME 250 | |
51 | #define EEH_PE_RST_SETTLE_TIME 1800 | |
52 | ||
968f968f GS |
53 | /* |
54 | * The struct is used to trace PE related EEH functionality. | |
55 | * In theory, there will have one instance of the struct to | |
56 | * be created against particular PE. In nature, PEs corelate | |
57 | * to each other. the struct has to reflect that hierarchy in | |
58 | * order to easily pick up those affected PEs when one particular | |
59 | * PE has EEH errors. | |
60 | * | |
61 | * Also, one particular PE might be composed of PCI device, PCI | |
62 | * bus and its subordinate components. The struct also need ship | |
63 | * the information. Further more, one particular PE is only meaingful | |
64 | * in the corresponding PHB. Therefore, the root PEs should be created | |
65 | * against existing PHBs in on-to-one fashion. | |
66 | */ | |
5efc3ad7 GS |
67 | #define EEH_PE_INVALID (1 << 0) /* Invalid */ |
68 | #define EEH_PE_PHB (1 << 1) /* PHB PE */ | |
69 | #define EEH_PE_DEVICE (1 << 2) /* Device PE */ | |
70 | #define EEH_PE_BUS (1 << 3) /* Bus PE */ | |
968f968f GS |
71 | |
72 | #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ | |
73 | #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ | |
d0914f50 | 74 | #define EEH_PE_RESET (1 << 2) /* PE reset in progress */ |
968f968f | 75 | |
807a827d GS |
76 | #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ |
77 | ||
968f968f GS |
78 | struct eeh_pe { |
79 | int type; /* PE type: PHB/Bus/Device */ | |
80 | int state; /* PE EEH dependent mode */ | |
81 | int config_addr; /* Traditional PCI address */ | |
82 | int addr; /* PE configuration address */ | |
83 | struct pci_controller *phb; /* Associated PHB */ | |
8cdb2833 | 84 | struct pci_bus *bus; /* Top PCI bus for bus PE */ |
968f968f GS |
85 | int check_count; /* Times of ignored error */ |
86 | int freeze_count; /* Times of froze up */ | |
5a71978e | 87 | struct timeval tstamp; /* Time on first-time freeze */ |
968f968f | 88 | int false_positives; /* Times of reported #ff's */ |
05ec424e | 89 | atomic_t pass_dev_cnt; /* Count of passed through devs */ |
968f968f | 90 | struct eeh_pe *parent; /* Parent PE */ |
bb593c00 | 91 | void *data; /* PE auxillary data */ |
968f968f GS |
92 | struct list_head child_list; /* Link PE to the child list */ |
93 | struct list_head edevs; /* Link list of EEH devices */ | |
94 | struct list_head child; /* Child PEs */ | |
95 | }; | |
96 | ||
9feed42e GS |
97 | #define eeh_pe_for_each_dev(pe, edev, tmp) \ |
98 | list_for_each_entry_safe(edev, tmp, &pe->edevs, list) | |
5b663529 | 99 | |
05ec424e GS |
100 | static inline bool eeh_pe_passed(struct eeh_pe *pe) |
101 | { | |
102 | return pe ? !!atomic_read(&pe->pass_dev_cnt) : false; | |
103 | } | |
104 | ||
eb740b5f GS |
105 | /* |
106 | * The struct is used to trace EEH state for the associated | |
107 | * PCI device node or PCI device. In future, it might | |
108 | * represent PE as well so that the EEH device to form | |
109 | * another tree except the currently existing tree of PCI | |
110 | * buses and PCI devices | |
111 | */ | |
4b83bd45 GS |
112 | #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ |
113 | #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ | |
114 | #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ | |
115 | #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ | |
116 | #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ | |
eb740b5f | 117 | |
f26c7a03 GS |
118 | #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */ |
119 | #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */ | |
d2b0f6f7 | 120 | #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */ |
ab55d218 | 121 | |
eb740b5f GS |
122 | struct eeh_dev { |
123 | int mode; /* EEH mode */ | |
124 | int class_code; /* Class code of the device */ | |
125 | int config_addr; /* Config address */ | |
126 | int pe_config_addr; /* PE config address */ | |
eb740b5f | 127 | u32 config_space[16]; /* Saved PCI config space */ |
2a18dfc6 GS |
128 | int pcix_cap; /* Saved PCIx capability */ |
129 | int pcie_cap; /* Saved PCIe capability */ | |
130 | int aer_cap; /* Saved AER capability */ | |
968f968f GS |
131 | struct eeh_pe *pe; /* Associated PE */ |
132 | struct list_head list; /* Form link list in the PE */ | |
eb740b5f GS |
133 | struct pci_controller *phb; /* Associated PHB */ |
134 | struct device_node *dn; /* Associated device node */ | |
135 | struct pci_dev *pdev; /* Associated PCI device */ | |
f5c57710 | 136 | struct pci_bus *bus; /* PCI bus for partial hotplug */ |
eb740b5f GS |
137 | }; |
138 | ||
139 | static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev) | |
140 | { | |
2d5c1216 | 141 | return edev ? edev->dn : NULL; |
eb740b5f GS |
142 | } |
143 | ||
144 | static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) | |
145 | { | |
2d5c1216 | 146 | return edev ? edev->pdev : NULL; |
eb740b5f GS |
147 | } |
148 | ||
2a58222f WY |
149 | static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev) |
150 | { | |
151 | return edev ? edev->pe : NULL; | |
152 | } | |
153 | ||
7e4e7867 GS |
154 | /* Return values from eeh_ops::next_error */ |
155 | enum { | |
156 | EEH_NEXT_ERR_NONE = 0, | |
157 | EEH_NEXT_ERR_INF, | |
158 | EEH_NEXT_ERR_FROZEN_PE, | |
159 | EEH_NEXT_ERR_FENCED_PHB, | |
160 | EEH_NEXT_ERR_DEAD_PHB, | |
161 | EEH_NEXT_ERR_DEAD_IOC | |
162 | }; | |
163 | ||
aa1e6374 GS |
164 | /* |
165 | * The struct is used to trace the registered EEH operation | |
166 | * callback functions. Actually, those operation callback | |
167 | * functions are heavily platform dependent. That means the | |
168 | * platform should register its own EEH operation callback | |
169 | * functions before any EEH further operations. | |
170 | */ | |
8fb8f709 GS |
171 | #define EEH_OPT_DISABLE 0 /* EEH disable */ |
172 | #define EEH_OPT_ENABLE 1 /* EEH enable */ | |
173 | #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */ | |
174 | #define EEH_OPT_THAW_DMA 3 /* DMA enable */ | |
0d5ee520 | 175 | #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */ |
eb594a47 GS |
176 | #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */ |
177 | #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */ | |
178 | #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */ | |
179 | #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */ | |
180 | #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */ | |
181 | #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */ | |
182 | #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */ | |
212d16cd GS |
183 | #define EEH_PE_STATE_NORMAL 0 /* Normal state */ |
184 | #define EEH_PE_STATE_RESET 1 /* PE reset asserted */ | |
185 | #define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */ | |
186 | #define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA, Enabled IO */ | |
187 | #define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */ | |
2652481f GS |
188 | #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */ |
189 | #define EEH_RESET_HOT 1 /* Hot reset */ | |
190 | #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */ | |
8d633291 GS |
191 | #define EEH_LOG_TEMP 1 /* EEH temporary error log */ |
192 | #define EEH_LOG_PERM 2 /* EEH permanent error log */ | |
eb594a47 | 193 | |
aa1e6374 GS |
194 | struct eeh_ops { |
195 | char *name; | |
196 | int (*init)(void); | |
21fd21f5 | 197 | int (*post_init)(void); |
d7bb8862 | 198 | void* (*of_probe)(struct device_node *dn, void *flag); |
51fb5f56 | 199 | int (*dev_probe)(struct pci_dev *dev, void *flag); |
371a395d GS |
200 | int (*set_option)(struct eeh_pe *pe, int option); |
201 | int (*get_pe_addr)(struct eeh_pe *pe); | |
202 | int (*get_state)(struct eeh_pe *pe, int *state); | |
203 | int (*reset)(struct eeh_pe *pe, int option); | |
204 | int (*wait_state)(struct eeh_pe *pe, int max_wait); | |
205 | int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len); | |
206 | int (*configure_bridge)(struct eeh_pe *pe); | |
3780444c GS |
207 | int (*read_config)(struct device_node *dn, int where, int size, u32 *val); |
208 | int (*write_config)(struct device_node *dn, int where, int size, u32 val); | |
8a6b1bc7 | 209 | int (*next_error)(struct eeh_pe **pe); |
1d350544 | 210 | int (*restore_config)(struct device_node *dn); |
aa1e6374 GS |
211 | }; |
212 | ||
8a5ad356 | 213 | extern int eeh_subsystem_flags; |
aa1e6374 | 214 | extern struct eeh_ops *eeh_ops; |
4907581d | 215 | extern raw_spinlock_t confirm_error_lock; |
d7bb8862 | 216 | |
05b1721d | 217 | static inline void eeh_add_flag(int flag) |
2ec5a0ad | 218 | { |
05b1721d | 219 | eeh_subsystem_flags |= flag; |
2ec5a0ad GS |
220 | } |
221 | ||
05b1721d | 222 | static inline void eeh_clear_flag(int flag) |
2ec5a0ad | 223 | { |
05b1721d | 224 | eeh_subsystem_flags &= ~flag; |
2ec5a0ad GS |
225 | } |
226 | ||
05b1721d | 227 | static inline bool eeh_has_flag(int flag) |
d7bb8862 | 228 | { |
05b1721d | 229 | return !!(eeh_subsystem_flags & flag); |
d7bb8862 GS |
230 | } |
231 | ||
05b1721d | 232 | static inline bool eeh_enabled(void) |
d7bb8862 | 233 | { |
05b1721d GS |
234 | if (eeh_has_flag(EEH_FORCE_DISABLED) || |
235 | !eeh_has_flag(EEH_ENABLED)) | |
236 | return false; | |
d7bb8862 | 237 | |
05b1721d | 238 | return true; |
d7bb8862 | 239 | } |
646a8499 | 240 | |
4907581d GS |
241 | static inline void eeh_serialize_lock(unsigned long *flags) |
242 | { | |
243 | raw_spin_lock_irqsave(&confirm_error_lock, *flags); | |
244 | } | |
245 | ||
246 | static inline void eeh_serialize_unlock(unsigned long flags) | |
247 | { | |
248 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); | |
249 | } | |
250 | ||
cb3bc9d0 GS |
251 | /* |
252 | * Max number of EEH freezes allowed before we consider the device | |
253 | * to be permanently disabled. | |
254 | */ | |
172ca926 LV |
255 | #define EEH_MAX_ALLOWED_FREEZES 5 |
256 | ||
22f4ab12 | 257 | typedef void *(*eeh_traverse_func)(void *data, void *flag); |
bb593c00 | 258 | void eeh_set_pe_aux_size(int size); |
cad5cef6 | 259 | int eeh_phb_pe_create(struct pci_controller *phb); |
9ff67433 | 260 | struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); |
01566808 | 261 | struct eeh_pe *eeh_pe_get(struct eeh_dev *edev); |
9b84348c | 262 | int eeh_add_to_parent_pe(struct eeh_dev *edev); |
807a827d | 263 | int eeh_rmv_from_parent_pe(struct eeh_dev *edev); |
5a71978e | 264 | void eeh_pe_update_time_stamp(struct eeh_pe *pe); |
f5c57710 GS |
265 | void *eeh_pe_traverse(struct eeh_pe *root, |
266 | eeh_traverse_func fn, void *flag); | |
9e6d2cf6 GS |
267 | void *eeh_pe_dev_traverse(struct eeh_pe *root, |
268 | eeh_traverse_func fn, void *flag); | |
269 | void eeh_pe_restore_bars(struct eeh_pe *pe); | |
357b2f3d | 270 | const char *eeh_pe_loc_get(struct eeh_pe *pe); |
9b3c76f0 | 271 | struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); |
55037d17 | 272 | |
cad5cef6 GKH |
273 | void *eeh_dev_init(struct device_node *dn, void *data); |
274 | void eeh_dev_phb_init_dynamic(struct pci_controller *phb); | |
eeb6361f | 275 | int eeh_init(void); |
aa1e6374 GS |
276 | int __init eeh_ops_register(struct eeh_ops *ops); |
277 | int __exit eeh_ops_unregister(const char *name); | |
3e938052 | 278 | int eeh_check_failure(const volatile void __iomem *token); |
f8f7d63f | 279 | int eeh_dev_check_failure(struct eeh_dev *edev); |
eeb6361f | 280 | void eeh_addr_cache_build(void); |
f2856491 | 281 | void eeh_add_device_early(struct device_node *); |
e2a296ee | 282 | void eeh_add_device_tree_early(struct device_node *); |
f2856491 | 283 | void eeh_add_device_late(struct pci_dev *); |
827c1a6c | 284 | void eeh_add_device_tree_late(struct pci_bus *); |
6a040ce7 | 285 | void eeh_add_sysfs_files(struct pci_bus *); |
807a827d | 286 | void eeh_remove_device(struct pci_dev *); |
212d16cd GS |
287 | int eeh_dev_open(struct pci_dev *pdev); |
288 | void eeh_dev_release(struct pci_dev *pdev); | |
289 | struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group); | |
290 | int eeh_pe_set_option(struct eeh_pe *pe, int option); | |
291 | int eeh_pe_get_state(struct eeh_pe *pe); | |
292 | int eeh_pe_reset(struct eeh_pe *pe, int option); | |
293 | int eeh_pe_configure(struct eeh_pe *pe); | |
e2a296ee | 294 | |
1da177e4 LT |
295 | /** |
296 | * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. | |
297 | * | |
298 | * If this macro yields TRUE, the caller relays to eeh_check_failure() | |
299 | * which does further tests out of line. | |
300 | */ | |
2ec5a0ad | 301 | #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) |
1da177e4 LT |
302 | |
303 | /* | |
304 | * Reads from a device which has been isolated by EEH will return | |
305 | * all 1s. This macro gives an all-1s value of the given size (in | |
306 | * bytes: 1, 2, or 4) for comparing with the result of a read. | |
307 | */ | |
308 | #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8)) | |
309 | ||
310 | #else /* !CONFIG_EEH */ | |
eb740b5f | 311 | |
2ec5a0ad GS |
312 | static inline bool eeh_enabled(void) |
313 | { | |
314 | return false; | |
315 | } | |
316 | ||
51fb5f56 GS |
317 | static inline int eeh_init(void) |
318 | { | |
319 | return 0; | |
320 | } | |
321 | ||
eb740b5f GS |
322 | static inline void *eeh_dev_init(struct device_node *dn, void *data) |
323 | { | |
324 | return NULL; | |
325 | } | |
326 | ||
327 | static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { } | |
328 | ||
3e938052 | 329 | static inline int eeh_check_failure(const volatile void __iomem *token) |
1da177e4 | 330 | { |
3e938052 | 331 | return 0; |
1da177e4 LT |
332 | } |
333 | ||
f8f7d63f | 334 | #define eeh_dev_check_failure(x) (0) |
1da177e4 | 335 | |
3ab96a02 | 336 | static inline void eeh_addr_cache_build(void) { } |
1da177e4 | 337 | |
f2856491 GS |
338 | static inline void eeh_add_device_early(struct device_node *dn) { } |
339 | ||
022930eb HM |
340 | static inline void eeh_add_device_tree_early(struct device_node *dn) { } |
341 | ||
f2856491 GS |
342 | static inline void eeh_add_device_late(struct pci_dev *dev) { } |
343 | ||
827c1a6c JR |
344 | static inline void eeh_add_device_tree_late(struct pci_bus *bus) { } |
345 | ||
6a040ce7 TLSC |
346 | static inline void eeh_add_sysfs_files(struct pci_bus *bus) { } |
347 | ||
807a827d | 348 | static inline void eeh_remove_device(struct pci_dev *dev) { } |
646a8499 | 349 | |
1da177e4 LT |
350 | #define EEH_POSSIBLE_ERROR(val, type) (0) |
351 | #define EEH_IO_ERROR_VALUE(size) (-1UL) | |
352 | #endif /* CONFIG_EEH */ | |
353 | ||
8b8da358 | 354 | #ifdef CONFIG_PPC64 |
172ca926 | 355 | /* |
1da177e4 LT |
356 | * MMIO read/write operations with EEH support. |
357 | */ | |
358 | static inline u8 eeh_readb(const volatile void __iomem *addr) | |
359 | { | |
360 | u8 val = in_8(addr); | |
361 | if (EEH_POSSIBLE_ERROR(val, u8)) | |
3e938052 | 362 | eeh_check_failure(addr); |
1da177e4 LT |
363 | return val; |
364 | } | |
1da177e4 LT |
365 | |
366 | static inline u16 eeh_readw(const volatile void __iomem *addr) | |
367 | { | |
368 | u16 val = in_le16(addr); | |
369 | if (EEH_POSSIBLE_ERROR(val, u16)) | |
3e938052 | 370 | eeh_check_failure(addr); |
1da177e4 LT |
371 | return val; |
372 | } | |
1da177e4 LT |
373 | |
374 | static inline u32 eeh_readl(const volatile void __iomem *addr) | |
375 | { | |
376 | u32 val = in_le32(addr); | |
377 | if (EEH_POSSIBLE_ERROR(val, u32)) | |
3e938052 | 378 | eeh_check_failure(addr); |
1da177e4 LT |
379 | return val; |
380 | } | |
4cb3cee0 BH |
381 | |
382 | static inline u64 eeh_readq(const volatile void __iomem *addr) | |
1da177e4 | 383 | { |
4cb3cee0 BH |
384 | u64 val = in_le64(addr); |
385 | if (EEH_POSSIBLE_ERROR(val, u64)) | |
3e938052 | 386 | eeh_check_failure(addr); |
1da177e4 LT |
387 | return val; |
388 | } | |
1da177e4 | 389 | |
4cb3cee0 | 390 | static inline u16 eeh_readw_be(const volatile void __iomem *addr) |
1da177e4 | 391 | { |
4cb3cee0 BH |
392 | u16 val = in_be16(addr); |
393 | if (EEH_POSSIBLE_ERROR(val, u16)) | |
3e938052 | 394 | eeh_check_failure(addr); |
1da177e4 LT |
395 | return val; |
396 | } | |
4cb3cee0 BH |
397 | |
398 | static inline u32 eeh_readl_be(const volatile void __iomem *addr) | |
1da177e4 | 399 | { |
4cb3cee0 BH |
400 | u32 val = in_be32(addr); |
401 | if (EEH_POSSIBLE_ERROR(val, u32)) | |
3e938052 | 402 | eeh_check_failure(addr); |
4cb3cee0 | 403 | return val; |
1da177e4 | 404 | } |
4cb3cee0 BH |
405 | |
406 | static inline u64 eeh_readq_be(const volatile void __iomem *addr) | |
1da177e4 LT |
407 | { |
408 | u64 val = in_be64(addr); | |
409 | if (EEH_POSSIBLE_ERROR(val, u64)) | |
3e938052 | 410 | eeh_check_failure(addr); |
1da177e4 LT |
411 | return val; |
412 | } | |
1da177e4 | 413 | |
68a64357 BH |
414 | static inline void eeh_memcpy_fromio(void *dest, const |
415 | volatile void __iomem *src, | |
1da177e4 LT |
416 | unsigned long n) |
417 | { | |
68a64357 | 418 | _memcpy_fromio(dest, src, n); |
1da177e4 LT |
419 | |
420 | /* Look for ffff's here at dest[n]. Assume that at least 4 bytes | |
421 | * were copied. Check all four bytes. | |
422 | */ | |
68a64357 | 423 | if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32)) |
3e938052 | 424 | eeh_check_failure(src); |
1da177e4 LT |
425 | } |
426 | ||
1da177e4 | 427 | /* in-string eeh macros */ |
4cb3cee0 BH |
428 | static inline void eeh_readsb(const volatile void __iomem *addr, void * buf, |
429 | int ns) | |
1da177e4 | 430 | { |
4cb3cee0 | 431 | _insb(addr, buf, ns); |
1da177e4 | 432 | if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) |
3e938052 | 433 | eeh_check_failure(addr); |
1da177e4 LT |
434 | } |
435 | ||
4cb3cee0 BH |
436 | static inline void eeh_readsw(const volatile void __iomem *addr, void * buf, |
437 | int ns) | |
1da177e4 | 438 | { |
4cb3cee0 | 439 | _insw(addr, buf, ns); |
1da177e4 | 440 | if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) |
3e938052 | 441 | eeh_check_failure(addr); |
1da177e4 LT |
442 | } |
443 | ||
4cb3cee0 BH |
444 | static inline void eeh_readsl(const volatile void __iomem *addr, void * buf, |
445 | int nl) | |
1da177e4 | 446 | { |
4cb3cee0 | 447 | _insl(addr, buf, nl); |
1da177e4 | 448 | if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) |
3e938052 | 449 | eeh_check_failure(addr); |
1da177e4 LT |
450 | } |
451 | ||
8b8da358 | 452 | #endif /* CONFIG_PPC64 */ |
88ced031 | 453 | #endif /* __KERNEL__ */ |
8b8da358 | 454 | #endif /* _POWERPC_EEH_H */ |