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27f44888 BH |
1 | /* |
2 | * PowerNV OPAL definitions. | |
3 | * | |
4 | * Copyright 2011 IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #ifndef __OPAL_H | |
13 | #define __OPAL_H | |
14 | ||
15 | /****** Takeover interface ********/ | |
16 | ||
17 | /* PAPR H-Call used to querty the HAL existence and/or instanciate | |
18 | * it from within pHyp (tech preview only). | |
19 | * | |
20 | * This is exclusively used in prom_init.c | |
21 | */ | |
22 | ||
23 | #ifndef __ASSEMBLY__ | |
24 | ||
25 | struct opal_takeover_args { | |
26 | u64 k_image; /* r4 */ | |
27 | u64 k_size; /* r5 */ | |
28 | u64 k_entry; /* r6 */ | |
29 | u64 k_entry2; /* r7 */ | |
30 | u64 hal_addr; /* r8 */ | |
31 | u64 rd_image; /* r9 */ | |
32 | u64 rd_size; /* r10 */ | |
33 | u64 rd_loc; /* r11 */ | |
34 | }; | |
35 | ||
7e1ce5a4 VH |
36 | /* |
37 | * SG entry | |
38 | * | |
39 | * WARNING: The current implementation requires each entry | |
40 | * to represent a block that is 4k aligned *and* each block | |
41 | * size except the last one in the list to be as well. | |
42 | */ | |
43 | struct opal_sg_entry { | |
44 | void *data; | |
45 | long length; | |
46 | }; | |
47 | ||
48 | /* sg list */ | |
49 | struct opal_sg_list { | |
50 | unsigned long num_entries; | |
51 | struct opal_sg_list *next; | |
52 | struct opal_sg_entry entry[]; | |
53 | }; | |
54 | ||
55 | /* We calculate number of sg entries based on PAGE_SIZE */ | |
56 | #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry)) | |
57 | ||
27f44888 BH |
58 | extern long opal_query_takeover(u64 *hal_size, u64 *hal_align); |
59 | ||
60 | extern long opal_do_takeover(struct opal_takeover_args *args); | |
61 | ||
14a43e69 | 62 | struct rtas_args; |
27f44888 BH |
63 | extern int opal_enter_rtas(struct rtas_args *args, |
64 | unsigned long data, | |
65 | unsigned long entry); | |
66 | ||
27f44888 BH |
67 | #endif /* __ASSEMBLY__ */ |
68 | ||
69 | /****** OPAL APIs ******/ | |
70 | ||
14a43e69 BH |
71 | /* Return codes */ |
72 | #define OPAL_SUCCESS 0 | |
73 | #define OPAL_PARAMETER -1 | |
74 | #define OPAL_BUSY -2 | |
75 | #define OPAL_PARTIAL -3 | |
76 | #define OPAL_CONSTRAINED -4 | |
77 | #define OPAL_CLOSED -5 | |
78 | #define OPAL_HARDWARE -6 | |
79 | #define OPAL_UNSUPPORTED -7 | |
80 | #define OPAL_PERMISSION -8 | |
81 | #define OPAL_NO_MEM -9 | |
82 | #define OPAL_RESOURCE -10 | |
83 | #define OPAL_INTERNAL_ERROR -11 | |
84 | #define OPAL_BUSY_EVENT -12 | |
85 | #define OPAL_HARDWARE_FROZEN -13 | |
86 | ||
87 | /* API Tokens (in r0) */ | |
88 | #define OPAL_CONSOLE_WRITE 1 | |
89 | #define OPAL_CONSOLE_READ 2 | |
90 | #define OPAL_RTC_READ 3 | |
91 | #define OPAL_RTC_WRITE 4 | |
92 | #define OPAL_CEC_POWER_DOWN 5 | |
93 | #define OPAL_CEC_REBOOT 6 | |
94 | #define OPAL_READ_NVRAM 7 | |
95 | #define OPAL_WRITE_NVRAM 8 | |
96 | #define OPAL_HANDLE_INTERRUPT 9 | |
97 | #define OPAL_POLL_EVENTS 10 | |
98 | #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 | |
99 | #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 | |
100 | #define OPAL_PCI_CONFIG_READ_BYTE 13 | |
101 | #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 | |
102 | #define OPAL_PCI_CONFIG_READ_WORD 15 | |
103 | #define OPAL_PCI_CONFIG_WRITE_BYTE 16 | |
104 | #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 | |
105 | #define OPAL_PCI_CONFIG_WRITE_WORD 18 | |
106 | #define OPAL_SET_XIVE 19 | |
107 | #define OPAL_GET_XIVE 20 | |
108 | #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ | |
109 | #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 | |
110 | #define OPAL_PCI_EEH_FREEZE_STATUS 23 | |
111 | #define OPAL_PCI_SHPC 24 | |
112 | #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 | |
113 | #define OPAL_PCI_EEH_FREEZE_CLEAR 26 | |
114 | #define OPAL_PCI_PHB_MMIO_ENABLE 27 | |
115 | #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 | |
116 | #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 | |
117 | #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 | |
118 | #define OPAL_PCI_SET_PE 31 | |
119 | #define OPAL_PCI_SET_PELTV 32 | |
120 | #define OPAL_PCI_SET_MVE 33 | |
121 | #define OPAL_PCI_SET_MVE_ENABLE 34 | |
122 | #define OPAL_PCI_GET_XIVE_REISSUE 35 | |
123 | #define OPAL_PCI_SET_XIVE_REISSUE 36 | |
124 | #define OPAL_PCI_SET_XIVE_PE 37 | |
125 | #define OPAL_GET_XIVE_SOURCE 38 | |
126 | #define OPAL_GET_MSI_32 39 | |
127 | #define OPAL_GET_MSI_64 40 | |
128 | #define OPAL_START_CPU 41 | |
129 | #define OPAL_QUERY_CPU_STATUS 42 | |
130 | #define OPAL_WRITE_OPPANEL 43 | |
131 | #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 | |
132 | #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 | |
133 | #define OPAL_PCI_RESET 49 | |
f11fe552 BH |
134 | #define OPAL_PCI_GET_HUB_DIAG_DATA 50 |
135 | #define OPAL_PCI_GET_PHB_DIAG_DATA 51 | |
136 | #define OPAL_PCI_FENCE_PHB 52 | |
137 | #define OPAL_PCI_REINIT 53 | |
138 | #define OPAL_PCI_MASK_PE_ERROR 54 | |
139 | #define OPAL_SET_SLOT_LED_STATUS 55 | |
140 | #define OPAL_GET_EPOW_STATUS 56 | |
141 | #define OPAL_SET_SYSTEM_ATTENTION_LED 57 | |
23773230 GS |
142 | #define OPAL_RESERVED1 58 |
143 | #define OPAL_RESERVED2 59 | |
144 | #define OPAL_PCI_NEXT_ERROR 60 | |
145 | #define OPAL_PCI_EEH_FREEZE_STATUS2 61 | |
146 | #define OPAL_PCI_POLL 62 | |
137436c9 | 147 | #define OPAL_PCI_MSI_EOI 63 |
23773230 | 148 | #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 |
cc0efb57 BH |
149 | #define OPAL_XSCOM_READ 65 |
150 | #define OPAL_XSCOM_WRITE 66 | |
151 | #define OPAL_LPC_READ 67 | |
152 | #define OPAL_LPC_WRITE 68 | |
13906db6 | 153 | #define OPAL_RETURN_CPU 69 |
50bd6153 VH |
154 | #define OPAL_FLASH_VALIDATE 76 |
155 | #define OPAL_FLASH_MANAGE 77 | |
156 | #define OPAL_FLASH_UPDATE 78 | |
24366360 MS |
157 | #define OPAL_GET_MSG 85 |
158 | #define OPAL_CHECK_ASYNC_COMPLETION 86 | |
14a43e69 BH |
159 | |
160 | #ifndef __ASSEMBLY__ | |
161 | ||
162 | /* Other enums */ | |
163 | enum OpalVendorApiTokens { | |
164 | OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999 | |
165 | }; | |
23773230 | 166 | |
14a43e69 BH |
167 | enum OpalFreezeState { |
168 | OPAL_EEH_STOPPED_NOT_FROZEN = 0, | |
169 | OPAL_EEH_STOPPED_MMIO_FREEZE = 1, | |
170 | OPAL_EEH_STOPPED_DMA_FREEZE = 2, | |
171 | OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, | |
172 | OPAL_EEH_STOPPED_RESET = 4, | |
173 | OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, | |
174 | OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 | |
175 | }; | |
23773230 | 176 | |
14a43e69 BH |
177 | enum OpalEehFreezeActionToken { |
178 | OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, | |
179 | OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, | |
180 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3 | |
181 | }; | |
23773230 | 182 | |
14a43e69 | 183 | enum OpalPciStatusToken { |
23773230 GS |
184 | OPAL_EEH_NO_ERROR = 0, |
185 | OPAL_EEH_IOC_ERROR = 1, | |
186 | OPAL_EEH_PHB_ERROR = 2, | |
187 | OPAL_EEH_PE_ERROR = 3, | |
188 | OPAL_EEH_PE_MMIO_ERROR = 4, | |
189 | OPAL_EEH_PE_DMA_ERROR = 5 | |
14a43e69 | 190 | }; |
23773230 GS |
191 | |
192 | enum OpalPciErrorSeverity { | |
193 | OPAL_EEH_SEV_NO_ERROR = 0, | |
194 | OPAL_EEH_SEV_IOC_DEAD = 1, | |
195 | OPAL_EEH_SEV_PHB_DEAD = 2, | |
196 | OPAL_EEH_SEV_PHB_FENCED = 3, | |
197 | OPAL_EEH_SEV_PE_ER = 4, | |
198 | OPAL_EEH_SEV_INF = 5 | |
199 | }; | |
200 | ||
14a43e69 BH |
201 | enum OpalShpcAction { |
202 | OPAL_SHPC_GET_LINK_STATE = 0, | |
203 | OPAL_SHPC_GET_SLOT_STATE = 1 | |
204 | }; | |
23773230 | 205 | |
14a43e69 BH |
206 | enum OpalShpcLinkState { |
207 | OPAL_SHPC_LINK_DOWN = 0, | |
208 | OPAL_SHPC_LINK_UP = 1 | |
209 | }; | |
23773230 | 210 | |
14a43e69 BH |
211 | enum OpalMmioWindowType { |
212 | OPAL_M32_WINDOW_TYPE = 1, | |
213 | OPAL_M64_WINDOW_TYPE = 2, | |
214 | OPAL_IO_WINDOW_TYPE = 3 | |
215 | }; | |
23773230 | 216 | |
14a43e69 BH |
217 | enum OpalShpcSlotState { |
218 | OPAL_SHPC_DEV_NOT_PRESENT = 0, | |
219 | OPAL_SHPC_DEV_PRESENT = 1 | |
220 | }; | |
23773230 | 221 | |
14a43e69 BH |
222 | enum OpalExceptionHandler { |
223 | OPAL_MACHINE_CHECK_HANDLER = 1, | |
224 | OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, | |
225 | OPAL_SOFTPATCH_HANDLER = 3 | |
226 | }; | |
23773230 | 227 | |
14a43e69 | 228 | enum OpalPendingState { |
23773230 GS |
229 | OPAL_EVENT_OPAL_INTERNAL = 0x1, |
230 | OPAL_EVENT_NVRAM = 0x2, | |
231 | OPAL_EVENT_RTC = 0x4, | |
232 | OPAL_EVENT_CONSOLE_OUTPUT = 0x8, | |
233 | OPAL_EVENT_CONSOLE_INPUT = 0x10, | |
234 | OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, | |
235 | OPAL_EVENT_ERROR_LOG = 0x40, | |
236 | OPAL_EVENT_EPOW = 0x80, | |
237 | OPAL_EVENT_LED_STATUS = 0x100, | |
24366360 MS |
238 | OPAL_EVENT_PCI_ERROR = 0x200, |
239 | OPAL_EVENT_MSG_PENDING = 0x800, | |
240 | }; | |
241 | ||
242 | enum OpalMessageType { | |
243 | OPAL_MSG_ASYNC_COMP = 0, | |
244 | OPAL_MSG_MEM_ERR, | |
245 | OPAL_MSG_EPOW, | |
246 | OPAL_MSG_SHUTDOWN, | |
247 | OPAL_MSG_TYPE_MAX, | |
14a43e69 BH |
248 | }; |
249 | ||
250 | /* Machine check related definitions */ | |
251 | enum OpalMCE_Version { | |
252 | OpalMCE_V1 = 1, | |
253 | }; | |
254 | ||
255 | enum OpalMCE_Severity { | |
256 | OpalMCE_SEV_NO_ERROR = 0, | |
257 | OpalMCE_SEV_WARNING = 1, | |
258 | OpalMCE_SEV_ERROR_SYNC = 2, | |
259 | OpalMCE_SEV_FATAL = 3, | |
260 | }; | |
261 | ||
262 | enum OpalMCE_Disposition { | |
263 | OpalMCE_DISPOSITION_RECOVERED = 0, | |
264 | OpalMCE_DISPOSITION_NOT_RECOVERED = 1, | |
265 | }; | |
266 | ||
267 | enum OpalMCE_Initiator { | |
268 | OpalMCE_INITIATOR_UNKNOWN = 0, | |
269 | OpalMCE_INITIATOR_CPU = 1, | |
270 | }; | |
271 | ||
272 | enum OpalMCE_ErrorType { | |
273 | OpalMCE_ERROR_TYPE_UNKNOWN = 0, | |
274 | OpalMCE_ERROR_TYPE_UE = 1, | |
275 | OpalMCE_ERROR_TYPE_SLB = 2, | |
276 | OpalMCE_ERROR_TYPE_ERAT = 3, | |
277 | OpalMCE_ERROR_TYPE_TLB = 4, | |
278 | }; | |
279 | ||
280 | enum OpalMCE_UeErrorType { | |
281 | OpalMCE_UE_ERROR_INDETERMINATE = 0, | |
282 | OpalMCE_UE_ERROR_IFETCH = 1, | |
283 | OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2, | |
284 | OpalMCE_UE_ERROR_LOAD_STORE = 3, | |
285 | OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4, | |
286 | }; | |
287 | ||
288 | enum OpalMCE_SlbErrorType { | |
289 | OpalMCE_SLB_ERROR_INDETERMINATE = 0, | |
290 | OpalMCE_SLB_ERROR_PARITY = 1, | |
291 | OpalMCE_SLB_ERROR_MULTIHIT = 2, | |
292 | }; | |
293 | ||
294 | enum OpalMCE_EratErrorType { | |
295 | OpalMCE_ERAT_ERROR_INDETERMINATE = 0, | |
296 | OpalMCE_ERAT_ERROR_PARITY = 1, | |
297 | OpalMCE_ERAT_ERROR_MULTIHIT = 2, | |
298 | }; | |
299 | ||
300 | enum OpalMCE_TlbErrorType { | |
301 | OpalMCE_TLB_ERROR_INDETERMINATE = 0, | |
302 | OpalMCE_TLB_ERROR_PARITY = 1, | |
303 | OpalMCE_TLB_ERROR_MULTIHIT = 2, | |
304 | }; | |
305 | ||
306 | enum OpalThreadStatus { | |
307 | OPAL_THREAD_INACTIVE = 0x0, | |
75b93da4 BH |
308 | OPAL_THREAD_STARTED = 0x1, |
309 | OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ | |
14a43e69 BH |
310 | }; |
311 | ||
312 | enum OpalPciBusCompare { | |
313 | OpalPciBusAny = 0, /* Any bus number match */ | |
314 | OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ | |
315 | OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ | |
316 | OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ | |
317 | OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ | |
318 | OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ | |
319 | OpalPciBusAll = 7, /* Match bus number exactly */ | |
320 | }; | |
321 | ||
322 | enum OpalDeviceCompare { | |
323 | OPAL_IGNORE_RID_DEVICE_NUMBER = 0, | |
324 | OPAL_COMPARE_RID_DEVICE_NUMBER = 1 | |
325 | }; | |
326 | ||
327 | enum OpalFuncCompare { | |
328 | OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, | |
329 | OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 | |
330 | }; | |
331 | ||
332 | enum OpalPeAction { | |
333 | OPAL_UNMAP_PE = 0, | |
334 | OPAL_MAP_PE = 1 | |
335 | }; | |
336 | ||
f11fe552 BH |
337 | enum OpalPeltvAction { |
338 | OPAL_REMOVE_PE_FROM_DOMAIN = 0, | |
339 | OPAL_ADD_PE_TO_DOMAIN = 1 | |
340 | }; | |
341 | ||
342 | enum OpalMveEnableAction { | |
343 | OPAL_DISABLE_MVE = 0, | |
344 | OPAL_ENABLE_MVE = 1 | |
345 | }; | |
346 | ||
14a43e69 BH |
347 | enum OpalPciResetAndReinitScope { |
348 | OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, | |
349 | OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, | |
f11fe552 BH |
350 | OPAL_PCI_IODA_TABLE_RESET = 6, |
351 | }; | |
352 | ||
353 | enum OpalPciResetState { | |
354 | OPAL_DEASSERT_RESET = 0, | |
355 | OPAL_ASSERT_RESET = 1 | |
14a43e69 BH |
356 | }; |
357 | ||
f11fe552 BH |
358 | enum OpalPciMaskAction { |
359 | OPAL_UNMASK_ERROR_TYPE = 0, | |
360 | OPAL_MASK_ERROR_TYPE = 1 | |
361 | }; | |
362 | ||
363 | enum OpalSlotLedType { | |
364 | OPAL_SLOT_LED_ID_TYPE = 0, | |
365 | OPAL_SLOT_LED_FAULT_TYPE = 1 | |
366 | }; | |
367 | ||
368 | enum OpalLedAction { | |
369 | OPAL_TURN_OFF_LED = 0, | |
370 | OPAL_TURN_ON_LED = 1, | |
371 | OPAL_QUERY_LED_STATE_AFTER_BUSY = 2 | |
372 | }; | |
373 | ||
374 | enum OpalEpowStatus { | |
375 | OPAL_EPOW_NONE = 0, | |
376 | OPAL_EPOW_UPS = 1, | |
377 | OPAL_EPOW_OVER_AMBIENT_TEMP = 2, | |
378 | OPAL_EPOW_OVER_INTERNAL_TEMP = 3 | |
379 | }; | |
14a43e69 | 380 | |
cc0efb57 BH |
381 | /* |
382 | * Address cycle types for LPC accesses. These also correspond | |
383 | * to the content of the first cell of the "reg" property for | |
384 | * device nodes on the LPC bus | |
385 | */ | |
386 | enum OpalLPCAddressType { | |
387 | OPAL_LPC_MEM = 0, | |
388 | OPAL_LPC_IO = 1, | |
389 | OPAL_LPC_FW = 2, | |
390 | }; | |
391 | ||
24366360 MS |
392 | struct opal_msg { |
393 | uint32_t msg_type; | |
394 | uint32_t reserved; | |
395 | uint64_t params[8]; | |
396 | }; | |
397 | ||
14a43e69 BH |
398 | struct opal_machine_check_event { |
399 | enum OpalMCE_Version version:8; /* 0x00 */ | |
400 | uint8_t in_use; /* 0x01 */ | |
401 | enum OpalMCE_Severity severity:8; /* 0x02 */ | |
402 | enum OpalMCE_Initiator initiator:8; /* 0x03 */ | |
403 | enum OpalMCE_ErrorType error_type:8; /* 0x04 */ | |
404 | enum OpalMCE_Disposition disposition:8; /* 0x05 */ | |
405 | uint8_t reserved_1[2]; /* 0x06 */ | |
406 | uint64_t gpr3; /* 0x08 */ | |
407 | uint64_t srr0; /* 0x10 */ | |
408 | uint64_t srr1; /* 0x18 */ | |
409 | union { /* 0x20 */ | |
410 | struct { | |
411 | enum OpalMCE_UeErrorType ue_error_type:8; | |
412 | uint8_t effective_address_provided; | |
413 | uint8_t physical_address_provided; | |
414 | uint8_t reserved_1[5]; | |
415 | uint64_t effective_address; | |
416 | uint64_t physical_address; | |
417 | uint8_t reserved_2[8]; | |
418 | } ue_error; | |
419 | ||
420 | struct { | |
421 | enum OpalMCE_SlbErrorType slb_error_type:8; | |
422 | uint8_t effective_address_provided; | |
423 | uint8_t reserved_1[6]; | |
424 | uint64_t effective_address; | |
425 | uint8_t reserved_2[16]; | |
426 | } slb_error; | |
427 | ||
428 | struct { | |
429 | enum OpalMCE_EratErrorType erat_error_type:8; | |
430 | uint8_t effective_address_provided; | |
431 | uint8_t reserved_1[6]; | |
432 | uint64_t effective_address; | |
433 | uint8_t reserved_2[16]; | |
434 | } erat_error; | |
435 | ||
436 | struct { | |
437 | enum OpalMCE_TlbErrorType tlb_error_type:8; | |
438 | uint8_t effective_address_provided; | |
439 | uint8_t reserved_1[6]; | |
440 | uint64_t effective_address; | |
441 | uint8_t reserved_2[16]; | |
442 | } tlb_error; | |
443 | } u; | |
444 | }; | |
445 | ||
23773230 GS |
446 | enum { |
447 | OPAL_P7IOC_DIAG_TYPE_NONE = 0, | |
448 | OPAL_P7IOC_DIAG_TYPE_RGC = 1, | |
449 | OPAL_P7IOC_DIAG_TYPE_BI = 2, | |
450 | OPAL_P7IOC_DIAG_TYPE_CI = 3, | |
451 | OPAL_P7IOC_DIAG_TYPE_MISC = 4, | |
452 | OPAL_P7IOC_DIAG_TYPE_I2C = 5, | |
453 | OPAL_P7IOC_DIAG_TYPE_LAST = 6 | |
454 | }; | |
455 | ||
456 | struct OpalIoP7IOCErrorData { | |
457 | uint16_t type; | |
458 | ||
459 | /* GEM */ | |
460 | uint64_t gemXfir; | |
461 | uint64_t gemRfir; | |
462 | uint64_t gemRirqfir; | |
463 | uint64_t gemMask; | |
464 | uint64_t gemRwof; | |
465 | ||
466 | /* LEM */ | |
467 | uint64_t lemFir; | |
468 | uint64_t lemErrMask; | |
469 | uint64_t lemAction0; | |
470 | uint64_t lemAction1; | |
471 | uint64_t lemWof; | |
472 | ||
473 | union { | |
474 | struct OpalIoP7IOCRgcErrorData { | |
475 | uint64_t rgcStatus; /* 3E1C10 */ | |
476 | uint64_t rgcLdcp; /* 3E1C18 */ | |
477 | }rgc; | |
478 | struct OpalIoP7IOCBiErrorData { | |
479 | uint64_t biLdcp0; /* 3C0100, 3C0118 */ | |
480 | uint64_t biLdcp1; /* 3C0108, 3C0120 */ | |
481 | uint64_t biLdcp2; /* 3C0110, 3C0128 */ | |
482 | uint64_t biFenceStatus; /* 3C0130, 3C0130 */ | |
483 | ||
484 | uint8_t biDownbound; /* BI Downbound or Upbound */ | |
485 | }bi; | |
486 | struct OpalIoP7IOCCiErrorData { | |
487 | uint64_t ciPortStatus; /* 3Dn008 */ | |
488 | uint64_t ciPortLdcp; /* 3Dn010 */ | |
489 | ||
490 | uint8_t ciPort; /* Index of CI port: 0/1 */ | |
491 | }ci; | |
492 | }; | |
493 | }; | |
494 | ||
f11fe552 BH |
495 | /** |
496 | * This structure defines the overlay which will be used to store PHB error | |
497 | * data upon request. | |
498 | */ | |
23773230 GS |
499 | enum { |
500 | OPAL_PHB_ERROR_DATA_VERSION_1 = 1, | |
501 | }; | |
502 | ||
503 | enum { | |
504 | OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, | |
8c6852e0 | 505 | OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2 |
23773230 GS |
506 | }; |
507 | ||
f11fe552 BH |
508 | enum { |
509 | OPAL_P7IOC_NUM_PEST_REGS = 128, | |
8c6852e0 | 510 | OPAL_PHB3_NUM_PEST_REGS = 256 |
f11fe552 BH |
511 | }; |
512 | ||
23773230 GS |
513 | struct OpalIoPhbErrorCommon { |
514 | uint32_t version; | |
515 | uint32_t ioType; | |
516 | uint32_t len; | |
517 | }; | |
518 | ||
f11fe552 | 519 | struct OpalIoP7IOCPhbErrorData { |
23773230 GS |
520 | struct OpalIoPhbErrorCommon common; |
521 | ||
f11fe552 BH |
522 | uint32_t brdgCtl; |
523 | ||
524 | // P7IOC utl regs | |
525 | uint32_t portStatusReg; | |
526 | uint32_t rootCmplxStatus; | |
527 | uint32_t busAgentStatus; | |
528 | ||
529 | // P7IOC cfg regs | |
530 | uint32_t deviceStatus; | |
531 | uint32_t slotStatus; | |
532 | uint32_t linkStatus; | |
533 | uint32_t devCmdStatus; | |
534 | uint32_t devSecStatus; | |
535 | ||
536 | // cfg AER regs | |
537 | uint32_t rootErrorStatus; | |
538 | uint32_t uncorrErrorStatus; | |
539 | uint32_t corrErrorStatus; | |
540 | uint32_t tlpHdr1; | |
541 | uint32_t tlpHdr2; | |
542 | uint32_t tlpHdr3; | |
543 | uint32_t tlpHdr4; | |
544 | uint32_t sourceId; | |
545 | ||
546 | uint32_t rsv3; | |
547 | ||
548 | // Record data about the call to allocate a buffer. | |
549 | uint64_t errorClass; | |
550 | uint64_t correlator; | |
551 | ||
552 | //P7IOC MMIO Error Regs | |
553 | uint64_t p7iocPlssr; // n120 | |
554 | uint64_t p7iocCsr; // n110 | |
555 | uint64_t lemFir; // nC00 | |
556 | uint64_t lemErrorMask; // nC18 | |
557 | uint64_t lemWOF; // nC40 | |
558 | uint64_t phbErrorStatus; // nC80 | |
559 | uint64_t phbFirstErrorStatus; // nC88 | |
560 | uint64_t phbErrorLog0; // nCC0 | |
561 | uint64_t phbErrorLog1; // nCC8 | |
562 | uint64_t mmioErrorStatus; // nD00 | |
563 | uint64_t mmioFirstErrorStatus; // nD08 | |
564 | uint64_t mmioErrorLog0; // nD40 | |
565 | uint64_t mmioErrorLog1; // nD48 | |
566 | uint64_t dma0ErrorStatus; // nD80 | |
567 | uint64_t dma0FirstErrorStatus; // nD88 | |
568 | uint64_t dma0ErrorLog0; // nDC0 | |
569 | uint64_t dma0ErrorLog1; // nDC8 | |
570 | uint64_t dma1ErrorStatus; // nE00 | |
571 | uint64_t dma1FirstErrorStatus; // nE08 | |
572 | uint64_t dma1ErrorLog0; // nE40 | |
573 | uint64_t dma1ErrorLog1; // nE48 | |
574 | uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS]; | |
575 | uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS]; | |
576 | }; | |
577 | ||
8c6852e0 GS |
578 | struct OpalIoPhb3ErrorData { |
579 | struct OpalIoPhbErrorCommon common; | |
580 | ||
581 | uint32_t brdgCtl; | |
582 | ||
583 | /* PHB3 UTL regs */ | |
584 | uint32_t portStatusReg; | |
585 | uint32_t rootCmplxStatus; | |
586 | uint32_t busAgentStatus; | |
587 | ||
588 | /* PHB3 cfg regs */ | |
589 | uint32_t deviceStatus; | |
590 | uint32_t slotStatus; | |
591 | uint32_t linkStatus; | |
592 | uint32_t devCmdStatus; | |
593 | uint32_t devSecStatus; | |
594 | ||
595 | /* cfg AER regs */ | |
596 | uint32_t rootErrorStatus; | |
597 | uint32_t uncorrErrorStatus; | |
598 | uint32_t corrErrorStatus; | |
599 | uint32_t tlpHdr1; | |
600 | uint32_t tlpHdr2; | |
601 | uint32_t tlpHdr3; | |
602 | uint32_t tlpHdr4; | |
603 | uint32_t sourceId; | |
604 | ||
605 | uint32_t rsv3; | |
606 | ||
607 | /* Record data about the call to allocate a buffer */ | |
608 | uint64_t errorClass; | |
609 | uint64_t correlator; | |
610 | ||
611 | uint64_t nFir; /* 000 */ | |
612 | uint64_t nFirMask; /* 003 */ | |
613 | uint64_t nFirWOF; /* 008 */ | |
614 | ||
615 | /* PHB3 MMIO Error Regs */ | |
616 | uint64_t phbPlssr; /* 120 */ | |
617 | uint64_t phbCsr; /* 110 */ | |
618 | uint64_t lemFir; /* C00 */ | |
619 | uint64_t lemErrorMask; /* C18 */ | |
620 | uint64_t lemWOF; /* C40 */ | |
621 | uint64_t phbErrorStatus; /* C80 */ | |
622 | uint64_t phbFirstErrorStatus; /* C88 */ | |
623 | uint64_t phbErrorLog0; /* CC0 */ | |
624 | uint64_t phbErrorLog1; /* CC8 */ | |
625 | uint64_t mmioErrorStatus; /* D00 */ | |
626 | uint64_t mmioFirstErrorStatus; /* D08 */ | |
627 | uint64_t mmioErrorLog0; /* D40 */ | |
628 | uint64_t mmioErrorLog1; /* D48 */ | |
629 | uint64_t dma0ErrorStatus; /* D80 */ | |
630 | uint64_t dma0FirstErrorStatus; /* D88 */ | |
631 | uint64_t dma0ErrorLog0; /* DC0 */ | |
632 | uint64_t dma0ErrorLog1; /* DC8 */ | |
633 | uint64_t dma1ErrorStatus; /* E00 */ | |
634 | uint64_t dma1FirstErrorStatus; /* E08 */ | |
635 | uint64_t dma1ErrorLog0; /* E40 */ | |
636 | uint64_t dma1ErrorLog1; /* E48 */ | |
637 | uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS]; | |
638 | uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS]; | |
639 | }; | |
640 | ||
14a43e69 | 641 | typedef struct oppanel_line { |
f11fe552 BH |
642 | const char * line; |
643 | uint64_t line_len; | |
14a43e69 BH |
644 | } oppanel_line_t; |
645 | ||
6f68b5e2 VH |
646 | /* /sys/firmware/opal */ |
647 | extern struct kobject *opal_kobj; | |
648 | ||
14a43e69 | 649 | /* API functions */ |
4f89363b | 650 | int64_t opal_console_write(int64_t term_number, __be64 *length, |
14a43e69 | 651 | const uint8_t *buffer); |
4f89363b | 652 | int64_t opal_console_read(int64_t term_number, __be64 *length, |
14a43e69 BH |
653 | uint8_t *buffer); |
654 | int64_t opal_console_write_buffer_space(int64_t term_number, | |
4f89363b | 655 | __be64 *length); |
6feff6d4 AB |
656 | int64_t opal_rtc_read(__be32 *year_month_day, |
657 | __be64 *hour_minute_second_millisecond); | |
14a43e69 BH |
658 | int64_t opal_rtc_write(uint32_t year_month_day, |
659 | uint64_t hour_minute_second_millisecond); | |
660 | int64_t opal_cec_power_down(uint64_t request); | |
661 | int64_t opal_cec_reboot(void); | |
662 | int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset); | |
663 | int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset); | |
5e4da530 | 664 | int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask); |
4f89363b | 665 | int64_t opal_poll_events(__be64 *outstanding_event_mask); |
14a43e69 BH |
666 | int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr, |
667 | uint64_t tce_mem_size); | |
668 | int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr, | |
669 | uint64_t tce_mem_size); | |
670 | int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func, | |
671 | uint64_t offset, uint8_t *data); | |
672 | int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func, | |
5e4da530 | 673 | uint64_t offset, __be16 *data); |
14a43e69 | 674 | int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func, |
5e4da530 | 675 | uint64_t offset, __be32 *data); |
14a43e69 BH |
676 | int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func, |
677 | uint64_t offset, uint8_t data); | |
678 | int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func, | |
679 | uint64_t offset, uint16_t data); | |
680 | int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func, | |
681 | uint64_t offset, uint32_t data); | |
682 | int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); | |
5e4da530 | 683 | int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority); |
14a43e69 BH |
684 | int64_t opal_register_exception_handler(uint64_t opal_exception, |
685 | uint64_t handler_address, | |
686 | uint64_t glue_cache_line); | |
687 | int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, | |
688 | uint8_t *freeze_state, | |
5e4da530 AB |
689 | __be16 *pci_error_type, |
690 | __be64 *phb_status); | |
14a43e69 BH |
691 | int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, |
692 | uint64_t eeh_action_token); | |
693 | int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state); | |
694 | ||
695 | ||
696 | ||
697 | int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, | |
698 | uint16_t window_num, uint16_t enable); | |
699 | int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, | |
700 | uint16_t window_num, | |
701 | uint64_t starting_real_address, | |
702 | uint64_t starting_pci_address, | |
703 | uint16_t segment_size); | |
704 | int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, | |
705 | uint16_t window_type, uint16_t window_num, | |
706 | uint16_t segment_num); | |
707 | int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr, | |
708 | uint64_t ivt_addr, uint64_t ivt_len, | |
709 | uint64_t reject_array_addr, | |
710 | uint64_t peltv_addr); | |
711 | int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func, | |
712 | uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare, | |
713 | uint8_t pe_action); | |
714 | int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, | |
715 | uint8_t state); | |
716 | int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); | |
717 | int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, | |
718 | uint32_t state); | |
719 | int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, | |
720 | uint8_t *p_bit, uint8_t *q_bit); | |
721 | int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, | |
722 | uint8_t p_bit, uint8_t q_bit); | |
137436c9 | 723 | int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); |
14a43e69 BH |
724 | int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, |
725 | uint32_t xive_num); | |
726 | int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, | |
5e4da530 | 727 | __be32 *interrupt_source_number); |
14a43e69 | 728 | int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, |
5e4da530 AB |
729 | uint8_t msi_range, __be32 *msi_address, |
730 | __be32 *message_data); | |
14a43e69 BH |
731 | int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, |
732 | uint32_t xive_num, uint8_t msi_range, | |
5e4da530 | 733 | __be64 *msi_address, __be32 *message_data); |
14a43e69 BH |
734 | int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address); |
735 | int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status); | |
736 | int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines); | |
737 | int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id, | |
738 | uint16_t tce_levels, uint64_t tce_table_addr, | |
739 | uint64_t tce_table_size, uint64_t tce_page_size); | |
740 | int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number, | |
741 | uint16_t dma_window_number, uint64_t pci_start_addr, | |
742 | uint64_t pci_mem_size); | |
743 | int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state); | |
744 | ||
23773230 GS |
745 | int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, |
746 | uint64_t diag_buffer_len); | |
747 | int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, | |
748 | uint64_t diag_buffer_len); | |
749 | int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, | |
750 | uint64_t diag_buffer_len); | |
f11fe552 BH |
751 | int64_t opal_pci_fence_phb(uint64_t phb_id); |
752 | int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope); | |
753 | int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); | |
754 | int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); | |
5e4da530 | 755 | int64_t opal_get_epow_status(__be64 *status); |
f11fe552 | 756 | int64_t opal_set_system_attention_led(uint8_t led_action); |
23773230 GS |
757 | int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe, |
758 | uint16_t *pci_error_type, uint16_t *severity); | |
759 | int64_t opal_pci_poll(uint64_t phb_id); | |
13906db6 | 760 | int64_t opal_return_cpu(void); |
f11fe552 | 761 | |
cc0efb57 BH |
762 | int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val); |
763 | int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val); | |
764 | ||
765 | int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, | |
766 | uint32_t addr, uint32_t data, uint32_t sz); | |
767 | int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, | |
768 | uint32_t addr, uint32_t *data, uint32_t sz); | |
50bd6153 VH |
769 | int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); |
770 | int64_t opal_manage_flash(uint8_t op); | |
771 | int64_t opal_update_flash(uint64_t blk_list); | |
cc0efb57 | 772 | |
24366360 MS |
773 | int64_t opal_get_msg(uint64_t buffer, size_t size); |
774 | int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token); | |
775 | ||
14a43e69 BH |
776 | /* Internal functions */ |
777 | extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data); | |
778 | ||
779 | extern int opal_get_chars(uint32_t vtermno, char *buf, int count); | |
780 | extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); | |
781 | ||
782 | extern void hvc_opal_init_early(void); | |
783 | ||
784 | /* Internal functions */ | |
785 | extern int early_init_dt_scan_opal(unsigned long node, const char *uname, | |
786 | int depth, void *data); | |
787 | ||
1bc98de2 | 788 | extern int opal_notifier_register(struct notifier_block *nb); |
24366360 MS |
789 | extern int opal_message_notifier_register(enum OpalMessageType msg_type, |
790 | struct notifier_block *nb); | |
1bc98de2 GS |
791 | extern void opal_notifier_enable(void); |
792 | extern void opal_notifier_disable(void); | |
793 | extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); | |
794 | ||
daea1175 BH |
795 | extern int opal_get_chars(uint32_t vtermno, char *buf, int count); |
796 | extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); | |
797 | ||
798 | extern void hvc_opal_init_early(void); | |
799 | ||
628daa8d BH |
800 | struct rtc_time; |
801 | extern int opal_set_rtc_time(struct rtc_time *tm); | |
802 | extern void opal_get_rtc_time(struct rtc_time *tm); | |
803 | extern unsigned long opal_get_boot_time(void); | |
804 | extern void opal_nvram_init(void); | |
50bd6153 | 805 | extern void opal_flash_init(void); |
628daa8d | 806 | |
ed79ba9e BH |
807 | extern int opal_machine_check(struct pt_regs *regs); |
808 | ||
73ed148a BH |
809 | extern void opal_shutdown(void); |
810 | ||
3fafe9c2 BH |
811 | extern void opal_lpc_init(void); |
812 | ||
14a43e69 | 813 | #endif /* __ASSEMBLY__ */ |
27f44888 BH |
814 | |
815 | #endif /* __OPAL_H */ |