[deliverable/linux.git] / arch / powerpc / include / asm / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <asm-generic/pci-bridge.h>

struct device_node;

/*
 * PCI controller operations
 */
struct pci_controller_ops {
	void		(*dma_dev_setup)(struct pci_dev *dev);
	void		(*dma_bus_setup)(struct pci_bus *bus);

	int		(*probe_mode)(struct pci_bus *);

	/* Called when pci_enable_device() is called. Returns true to
	 * allow assignment/enabling of the device. */
	bool		(*enable_device_hook)(struct pci_dev *);

	/* Called during PCI resource reassignment */
	resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
	void		(*reset_secondary_bus)(struct pci_dev *dev);
};

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;
	struct resource busn;

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_controller_ops controller_ops;
	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
	 *   link status is in a RC PCIe cfg register (vs being a SoC register)
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK	0x00000040
	u32 indirect_type;
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	resource_size_t mem_offset[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;
	struct pci_dn *pci_data;
#endif	/* CONFIG_PPC64 */

	void *private_data;
};

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);

extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
				int offset, int len, u32 *val);

extern int __indirect_read_config(struct pci_controller *hose,
				  unsigned char bus_number, unsigned int devfn,
				  int offset, int len, u32 *val);

extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
				 int offset, int len, u32 val);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

#ifndef CONFIG_PPC64

extern int pci_device_from_OF_node(struct device_node *node,
				   u8 *bus, u8 *devfn);
extern void pci_create_OF_bus_map(void);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* No specific ISA handling on ppc32 at this stage, it
	 * all goes through PCI
	 */
	return 0;
}

#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int     flags;

	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */
	int	vendor_id;		/* Vendor ID */
	int	device_id;		/* Device ID */
	int	class_code;		/* Device class code */

	struct  pci_dn *parent;
	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table *iommu_table;	/* for phb's or bridges */
	struct	device_node *node;	/* back-pointer to the device_node */

	int	pci_ext_config_space;	/* for pci devices */

	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
#ifdef CONFIG_EEH
	struct eeh_dev *edev;		/* eeh device */
#endif
#define IODA_INVALID_PE		(-1)
#ifdef CONFIG_PPC_POWERNV
	int	pe_number;
#endif
	struct list_head child_list;
	struct list_head list;
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
					   int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
extern void *update_dn_pci_info(struct device_node *dn, void *data);

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

#if defined(CONFIG_EEH)
static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
{
	return pdn ? pdn->edev : NULL;
}
#else
#define pdn_to_eeh_dev(x)	(NULL)
#endif

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pcibios_remove_pci_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pcibios_add_pci_devices(struct pci_bus *bus);


extern void isa_bridge_find_early(struct pci_controller *hose);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* Check if address hits the reserved legacy IO range */
	unsigned long ea = (unsigned long)address;
	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
}

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);

#ifdef CONFIG_PCI
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
7cd1de6b SR	4	/*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
5531e41b	10	#include <linux/pci.h>
a4c9e328 KG	11	#include <linux/list.h>
a4c9e328 KG	12	#include <linux/ioport.h>
f4ffd5e5	13	#include <asm-generic/pci-bridge.h>
a4c9e328	14
44ef3390 SR	15	struct device_node;
44ef3390 SR	16
e02def5b DA	17	/*
	18	* PCI controller operations
	19	*/
	20	struct pci_controller_ops {
	21	void (dma_dev_setup)(struct pci_dev dev);
b122c954	22	void (dma_bus_setup)(struct pci_bus bus);
ff9df8c8 DA	23
ff9df8c8 DA	24	int (probe_mode)(struct pci_bus );
b31e79f8 DA	25
	26	/* Called when pci_enable_device() is called. Returns true to
	27	* allow assignment/enabling of the device. */
	28	bool (enable_device_hook)(struct pci_dev );
542070ba DA	29
	30	/* Called during PCI resource reassignment */
	31	resource_size_t (window_alignment)(struct pci_bus , unsigned long type);
cd16c7ba	32	void (reset_secondary_bus)(struct pci_dev dev);
e02def5b DA	33	};
e02def5b DA	34
5531e41b KG	35	/*
	36	* Structure of a PCI controller (host bridge)
	37	*/
	38	struct pci_controller {
	39	struct pci_bus *bus;
a4c9e328	40	char is_dynamic;
7211991f SR	41	#ifdef CONFIG_PPC64
	42	int node;
	43	#endif
44ef3390	44	struct device_node *dn;
a4c9e328	45	struct list_head list_node;
5531e41b KG	46	struct device *parent;
	47
	48	int first_busno;
	49	int last_busno;
	50	int self_busno;
be8e60d8	51	struct resource busn;
5531e41b KG	52
5531e41b KG	53	void __iomem *io_base_virt;
7211991f SR	54	#ifdef CONFIG_PPC64
	55	void *io_base_alloc;
	56	#endif
5531e41b	57	resource_size_t io_base_phys;
13dccb9e	58	resource_size_t pci_io_size;
5531e41b	59
e9f82cb7 BH	60	/* Some machines have a special region to forward the ISA
	61	* "memory" cycles such as VGA memory regions. Left to 0
	62	* if unsupported
	63	*/
	64	resource_size_t isa_mem_phys;
	65	resource_size_t isa_mem_size;
	66
e02def5b	67	struct pci_controller_ops controller_ops;
5531e41b	68	struct pci_ops *ops;
70fbb938 SR	69	unsigned int __iomem *cfg_addr;
70fbb938 SR	70	void __iomem *cfg_data;
5531e41b KG	71
	72	/*
	73	* Used for variants of PCI indirect handling and possible quirks:
	74	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	75	* EXT_REG - provides access to PCI-e extended registers
25985edc	76	* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
5531e41b KG	77	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	78	* to determine which bus number to match on when generating type0
	79	* config cycles
62c66c8e KG	80	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	81	* hanging if we don't have link and try to do config cycles to
	82	* anything but the PHB. Only allow talking to the PHB if this is
	83	* set.
2e56ff20	84	* BIG_ENDIAN - cfg_addr is a big endian register
5ce4b596 JB	85	* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
5ce4b596 JB	86	* the PLB4. Effectively disable MRM commands by setting this.
34642bbb KG	87	* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
34642bbb KG	88	* link status is in a RC PCIe cfg register (vs being a SoC register)
5531e41b	89	*/
7cd1de6b SR	90	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	91	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	92	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	93	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	94	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5ce4b596	95	#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
34642bbb	96	#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
5531e41b	97	u32 indirect_type;
5531e41b KG	98	/* Currently, we limit ourselves to 1 IO range and 3 mem
	99	* ranges since the common pci_bus structure can't handle more
	100	*/
	101	struct resource io_resource;
	102	struct resource mem_resources[3];
3fd47f06	103	resource_size_t mem_offset[3];
5516b540	104	int global_number; /* PCI domain number */
89d93347 BB	105
	106	resource_size_t dma_window_base_cur;
	107	resource_size_t dma_window_size;
	108
7211991f SR	109	#ifdef CONFIG_PPC64
7211991f SR	110	unsigned long buid;
cca87d30	111	struct pci_dn *pci_data;
34642bbb	112	#endif /* CONFIG_PPC64 */
7211991f SR	113
7211991f SR	114	void *private_data;
5531e41b KG	115	};
5531e41b KG	116
5531e41b KG	117	/* These are used for config access before all the PCI probing
5531e41b KG	118	has been done. */
7cd1de6b SR	119	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	120	int dev_fn, int where, u8 *val);
	121	extern int early_read_config_word(struct pci_controller *hose, int bus,
	122	int dev_fn, int where, u16 *val);
	123	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	124	int dev_fn, int where, u32 *val);
	125	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	126	int dev_fn, int where, u8 val);
	127	extern int early_write_config_word(struct pci_controller *hose, int bus,
	128	int dev_fn, int where, u16 val);
	129	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	130	int dev_fn, int where, u32 val);
5531e41b	131
38805e5f KG	132	extern int early_find_capability(struct pci_controller *hose, int bus,
	133	int dev_fn, int cap);
	134
5531e41b	135	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	136	resource_size_t cfg_addr,
d94bad82 VB	137	resource_size_t cfg_data, u32 flags);
89c2dd62	138
50d8f87d RI	139	extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
	140	int offset, int len, u32 *val);
	141
6d5f6a0e KP	142	extern int __indirect_read_config(struct pci_controller *hose,
	143	unsigned char bus_number, unsigned int devfn,
	144	int offset, int len, u32 *val);
	145
50d8f87d RI	146	extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
	147	int offset, int len, u32 val);
	148
89c2dd62 KG	149	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
	150	{
	151	return bus->sysdata;
	152	}
	153
98d9f30c BH	154	#ifndef CONFIG_PPC64
	155
	156	extern int pci_device_from_OF_node(struct device_node *node,
	157	u8 bus, u8 devfn);
	158	extern void pci_create_OF_bus_map(void);
	159
89c2dd62 KG	160	static inline int isa_vaddr_is_ioport(void __iomem *address)
	161	{
	162	/* No specific ISA handling on ppc32 at this stage, it
	163	* all goes through PCI
	164	*/
	165	return 0;
	166	}
	167
7cd1de6b	168	#else /* CONFIG_PPC64 */
1da177e4	169
1635317f PM	170	/*
	171	* PCI stuff, for nodes representing PCI devices, pointed to
	172	* by device_node->data.
	173	*/
1635317f PM	174	struct iommu_table;
	175
	176	struct pci_dn {
cca87d30 GS	177	int flags;
cca87d30 GS	178
7684b40c	179	int busno; /* pci bus number */
7684b40c	180	int devfn; /* pci device and function number */
c035ff1d GS	181	int vendor_id; /* Vendor ID */
	182	int device_id; /* Device ID */
	183	int class_code; /* Device class code */
b5166cc2	184
cca87d30	185	struct pci_dn *parent;
c2e221e8 LV	186	struct pci_controller phb; / for pci devices */
c2e221e8 LV	187	struct iommu_table iommu_table; / for phb's or bridges */
c2e221e8 LV	188	struct device_node node; / back-pointer to the device_node */
	189
	190	int pci_ext_config_space; /* for pci devices */
	191
b6ed42a7	192	struct pci_dev pcidev; / back-pointer to the pci device */
184cd4a3	193	#ifdef CONFIG_EEH
2a0352fa	194	struct eeh_dev edev; / eeh device */
c2e221e8	195	#endif
184cd4a3 BH	196	#define IODA_INVALID_PE (-1)
	197	#ifdef CONFIG_PPC_POWERNV
	198	int pe_number;
	199	#endif
cca87d30 GS	200	struct list_head child_list;
cca87d30 GS	201	struct list_head list;
1635317f PM	202	};
	203
	204	/* Get the pointer to a device_node's pci_dn */
	205	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	206
cca87d30 GS	207	extern struct pci_dn pci_get_pdn_by_devfn(struct pci_bus bus,
cca87d30 GS	208	int devfn);
b72c1f65	209	extern struct pci_dn pci_get_pdn(struct pci_dev pdev);
cca87d30	210	extern void update_dn_pci_info(struct device_node dn, void *data);
1da177e4	211
40ef8cbc PM	212	static inline int pci_device_from_OF_node(struct device_node *np,
	213	u8 bus, u8 devfn)
	214	{
	215	if (!PCI_DN(np))
	216	return -ENODEV;
	217	*bus = PCI_DN(np)->busno;
	218	*devfn = PCI_DN(np)->devfn;
	219	return 0;
	220	}
	221
2a0352fa	222	#if defined(CONFIG_EEH)
e8e9b34c GS	223	static inline struct eeh_dev pdn_to_eeh_dev(struct pci_dn pdn)
	224	{
	225	return pdn ? pdn->edev : NULL;
	226	}
f8f7d63f	227	#else
e8e9b34c	228	#define pdn_to_eeh_dev(x) (NULL)
2a0352fa GS	229	#endif
2a0352fa GS	230
2bf6a8fa	231	/** Find the bus corresponding to the indicated device node */
7cd1de6b	232	extern struct pci_bus pcibios_find_pci_bus(struct device_node dn);
2bf6a8fa	233
2bf6a8fa	234	/** Remove all of the PCI devices under this bus */
7cd1de6b	235	extern void pcibios_remove_pci_devices(struct pci_bus *bus);
2bf6a8fa LV	236
2bf6a8fa LV	237	/** Discover new pci devices under this bus, and add them */
7cd1de6b	238	extern void pcibios_add_pci_devices(struct pci_bus *bus);
1da177e4	239
b5166cc2	240
3d5134ee BH	241	extern void isa_bridge_find_early(struct pci_controller *hose);
3d5134ee BH	242
6dfbde20 BH	243	static inline int isa_vaddr_is_ioport(void __iomem *address)
	244	{
	245	/* Check if address hits the reserved legacy IO range */
	246	unsigned long ea = (unsigned long)address;
	247	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
	248	}
	249
3d5134ee BH	250	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	251	extern int pcibios_map_io_space(struct pci_bus *bus);
	252
357518fa AB	253	#ifdef CONFIG_NUMA
	254	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	255	#else
	256	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
	257	#endif
	258
7cd1de6b	259	#endif /* CONFIG_PPC64 */
5531e41b KG	260
5531e41b KG	261	/* Get the PCI host controller for an OF device */
7cd1de6b SR	262	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	263	struct device_node* node);
5531e41b KG	264
5531e41b KG	265	/* Fill up host controller resources from the OF node */
7cd1de6b SR	266	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	267	struct device_node *dev, int primary);
5531e41b	268
5131d4d8	269	/* Allocate & free a PCI host bridge structure */
7cd1de6b	270	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8 BH	271	extern void pcibios_free_controller(struct pci_controller *phb);
5131d4d8 BH	272
5531e41b	273	#ifdef CONFIG_PCI
6dfbde20	274	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b	275	#else
6dfbde20 BH	276	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	277	{
	278	return 0;
	279	}
7cd1de6b	280	#endif /* CONFIG_PCI */
5531e41b	281
7cd1de6b SR	282	#endif /* __KERNEL__ */
7cd1de6b SR	283	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */