[deliverable/linux.git] / arch / powerpc / include / asm / perf_event_server.h

/*
 * Performance event support - PowerPC classic/server specific definitions.
 *
 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/types.h>
#include <asm/hw_irq.h>
#include <linux/device.h>

#define MAX_HWEVENTS		8
#define MAX_EVENT_ALTERNATIVES	8
#define MAX_LIMITED_HWCOUNTERS	2

/*
 * This struct provides the constants and functions needed to
 * describe the PMU on a particular POWER-family CPU.
 */
struct power_pmu {
	const char	*name;
	int		n_counter;
	int		max_alternatives;
	unsigned long	add_fields;
	unsigned long	test_adder;
	int		(*compute_mmcr)(u64 events[], int n_ev,
				unsigned int hwc[], unsigned long mmcr[]);
	int		(*get_constraint)(u64 event_id, unsigned long *mskp,
				unsigned long *valp);
	int		(*get_alternatives)(u64 event_id, unsigned int flags,
				u64 alt[]);
	void		(*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
	int		(*limited_pmc_event)(u64 event_id);
	u32		flags;
	const struct attribute_group	**attr_groups;
	int		n_generic;
	int		*generic_events;
	int		(*cache_events)[PERF_COUNT_HW_CACHE_MAX]
			       [PERF_COUNT_HW_CACHE_OP_MAX]
			       [PERF_COUNT_HW_CACHE_RESULT_MAX];
};

/*
 * Values for power_pmu.flags
 */
#define PPMU_LIMITED_PMC5_6	1	/* PMC5/6 have limited function */
#define PPMU_ALT_SIPR		2	/* uses alternate posn for SIPR/HV */
#define PPMU_NO_SIPR		4	/* no SIPR/HV in MMCRA at all */
#define PPMU_NO_CONT_SAMPLING	8	/* no continuous sampling */
#define PPMU_SIAR_VALID		16	/* Processor has SIAR Valid bit */

/*
 * Values for flags to get_alternatives()
 */
#define PPMU_LIMITED_PMC_OK	1	/* can put this on a limited PMC */
#define PPMU_LIMITED_PMC_REQD	2	/* have to put this on a limited PMC */
#define PPMU_ONLY_COUNT_RUN	4	/* only counting in run state */

extern int register_power_pmu(struct power_pmu *);

struct pt_regs;
extern unsigned long perf_misc_flags(struct pt_regs *regs);
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);

/*
 * Only override the default definitions in include/linux/perf_event.h
 * if we have hardware PMU support.
 */
#ifdef CONFIG_PPC_PERF_CTRS
#define perf_misc_flags(regs)	perf_misc_flags(regs)
#endif

/*
 * The power_pmu.get_constraint function returns a 32/64-bit value and
 * a 32/64-bit mask that express the constraints between this event_id and
 * other events.
 *
 * The value and mask are divided up into (non-overlapping) bitfields
 * of three different types:
 *
 * Select field: this expresses the constraint that some set of bits
 * in MMCR* needs to be set to a specific value for this event_id.  For a
 * select field, the mask contains 1s in every bit of the field, and
 * the value contains a unique value for each possible setting of the
 * MMCR* bits.  The constraint checking code will ensure that two events
 * that set the same field in their masks have the same value in their
 * value dwords.
 *
 * Add field: this expresses the constraint that there can be at most
 * N events in a particular class.  A field of k bits can be used for
 * N <= 2^(k-1) - 1.  The mask has the most significant bit of the field
 * set (and the other bits 0), and the value has only the least significant
 * bit of the field set.  In addition, the 'add_fields' and 'test_adder'
 * in the struct power_pmu for this processor come into play.  The
 * add_fields value contains 1 in the LSB of the field, and the
 * test_adder contains 2^(k-1) - 1 - N in the field.
 *
 * NAND field: this expresses the constraint that you may not have events
 * in all of a set of classes.  (For example, on PPC970, you can't select
 * events from the FPU, ISU and IDU simultaneously, although any two are
 * possible.)  For N classes, the field is N+1 bits wide, and each class
 * is assigned one bit from the least-significant N bits.  The mask has
 * only the most-significant bit set, and the value has only the bit
 * for the event_id's class set.  The test_adder has the least significant
 * bit set in the field.
 *
 * If an event_id is not subject to the constraint expressed by a particular
 * field, then it will have 0 in both the mask and value for that field.
 */

extern ssize_t power_events_sysfs_show(struct device *dev,
				struct device_attribute *attr, char *page);

/*
 * EVENT_VAR() is same as PMU_EVENT_VAR with a suffix.
 *
 * Having a suffix allows us to have aliases in sysfs - eg: the generic
 * event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and
 * 'PM_CYC' where the latter is the name by which the event is known in
 * POWER CPU specification.
 */
#define	EVENT_VAR(_id, _suffix)		event_attr_##_id##_suffix
#define	EVENT_PTR(_id, _suffix)		&EVENT_VAR(_id, _suffix)

#define	EVENT_ATTR(_name, _id, _suffix)					\
	PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_PM_##_id,	\
			power_events_sysfs_show)

#define	GENERIC_EVENT_ATTR(_name, _id)	EVENT_ATTR(_name, _id, _g)
#define	GENERIC_EVENT_PTR(_id)		EVENT_PTR(_id, _g)
Commit	Line	Data
a1110654 SW	1	/*
	2	* Performance event support - PowerPC classic/server specific definitions.
	3	*
	4	* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <asm/hw_irq.h>
1c53a270	14	#include <linux/device.h>
a1110654 SW	15
	16	#define MAX_HWEVENTS 8
	17	#define MAX_EVENT_ALTERNATIVES 8
	18	#define MAX_LIMITED_HWCOUNTERS 2
	19
	20	/*
	21	* This struct provides the constants and functions needed to
	22	* describe the PMU on a particular POWER-family CPU.
	23	*/
	24	struct power_pmu {
	25	const char *name;
	26	int n_counter;
	27	int max_alternatives;
	28	unsigned long add_fields;
	29	unsigned long test_adder;
	30	int (*compute_mmcr)(u64 events[], int n_ev,
	31	unsigned int hwc[], unsigned long mmcr[]);
	32	int (get_constraint)(u64 event_id, unsigned long mskp,
	33	unsigned long *valp);
	34	int (*get_alternatives)(u64 event_id, unsigned int flags,
	35	u64 alt[]);
	36	void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
	37	int (*limited_pmc_event)(u64 event_id);
	38	u32 flags;
1c53a270	39	const struct attribute_group **attr_groups;
a1110654 SW	40	int n_generic;
	41	int *generic_events;
	42	int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
	43	[PERF_COUNT_HW_CACHE_OP_MAX]
	44	[PERF_COUNT_HW_CACHE_RESULT_MAX];
	45	};
	46
	47	/*
	48	* Values for power_pmu.flags
	49	*/
	50	#define PPMU_LIMITED_PMC5_6 1 /* PMC5/6 have limited function */
	51	#define PPMU_ALT_SIPR 2 /* uses alternate posn for SIPR/HV */
1ce447b9 BH	52	#define PPMU_NO_SIPR 4 /* no SIPR/HV in MMCRA at all */
1ce447b9 BH	53	#define PPMU_NO_CONT_SAMPLING 8 /* no continuous sampling */
e6878835	54	#define PPMU_SIAR_VALID 16 /* Processor has SIAR Valid bit */
a1110654 SW	55
	56	/*
	57	* Values for flags to get_alternatives()
	58	*/
	59	#define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */
	60	#define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
	61	#define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */
	62
	63	extern int register_power_pmu(struct power_pmu *);
	64
	65	struct pt_regs;
	66	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	67	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
	68
a1110654 SW	69	/*
	70	* Only override the default definitions in include/linux/perf_event.h
	71	* if we have hardware PMU support.
	72	*/
	73	#ifdef CONFIG_PPC_PERF_CTRS
	74	#define perf_misc_flags(regs) perf_misc_flags(regs)
	75	#endif
	76
	77	/*
	78	* The power_pmu.get_constraint function returns a 32/64-bit value and
	79	* a 32/64-bit mask that express the constraints between this event_id and
	80	* other events.
	81	*
	82	* The value and mask are divided up into (non-overlapping) bitfields
	83	* of three different types:
	84	*
	85	* Select field: this expresses the constraint that some set of bits
	86	* in MMCR* needs to be set to a specific value for this event_id. For a
	87	* select field, the mask contains 1s in every bit of the field, and
	88	* the value contains a unique value for each possible setting of the
	89	* MMCR* bits. The constraint checking code will ensure that two events
	90	* that set the same field in their masks have the same value in their
	91	* value dwords.
	92	*
	93	* Add field: this expresses the constraint that there can be at most
	94	* N events in a particular class. A field of k bits can be used for
	95	* N <= 2^(k-1) - 1. The mask has the most significant bit of the field
	96	* set (and the other bits 0), and the value has only the least significant
	97	* bit of the field set. In addition, the 'add_fields' and 'test_adder'
	98	* in the struct power_pmu for this processor come into play. The
	99	* add_fields value contains 1 in the LSB of the field, and the
	100	* test_adder contains 2^(k-1) - 1 - N in the field.
	101	*
	102	* NAND field: this expresses the constraint that you may not have events
	103	* in all of a set of classes. (For example, on PPC970, you can't select
	104	* events from the FPU, ISU and IDU simultaneously, although any two are
	105	* possible.) For N classes, the field is N+1 bits wide, and each class
	106	* is assigned one bit from the least-significant N bits. The mask has
	107	* only the most-significant bit set, and the value has only the bit
	108	* for the event_id's class set. The test_adder has the least significant
	109	* bit set in the field.
	110	*
	111	* If an event_id is not subject to the constraint expressed by a particular
	112	* field, then it will have 0 in both the mask and value for that field.
	113	*/
1c53a270 SB	114
	115	extern ssize_t power_events_sysfs_show(struct device *dev,
	116	struct device_attribute attr, char page);
	117
	118	/*
	119	* EVENT_VAR() is same as PMU_EVENT_VAR with a suffix.
	120	*
	121	* Having a suffix allows us to have aliases in sysfs - eg: the generic
	122	* event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and
	123	* 'PM_CYC' where the latter is the name by which the event is known in
	124	* POWER CPU specification.
	125	*/
	126	#define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix
	127	#define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix)
	128
	129	#define EVENT_ATTR(_name, _id, _suffix) \
	130	PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_PM_##_id, \
	131	power_events_sysfs_show)
	132
	133	#define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
	134	#define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)