[deliverable/linux.git] / arch / powerpc / include / asm / perf_event_server.h

/*
 * Performance event support - PowerPC classic/server specific definitions.
 *
 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/types.h>
#include <asm/hw_irq.h>
#include <linux/device.h>
#include <uapi/asm/perf_event.h>

#define MAX_HWEVENTS		8
#define MAX_EVENT_ALTERNATIVES	8
#define MAX_LIMITED_HWCOUNTERS	2

/*
 * This struct provides the constants and functions needed to
 * describe the PMU on a particular POWER-family CPU.
 */
struct power_pmu {
	const char	*name;
	int		n_counter;
	int		max_alternatives;
	unsigned long	add_fields;
	unsigned long	test_adder;
	int		(*compute_mmcr)(u64 events[], int n_ev,
				unsigned int hwc[], unsigned long mmcr[]);
	int		(*get_constraint)(u64 event_id, unsigned long *mskp,
				unsigned long *valp);
	int		(*get_alternatives)(u64 event_id, unsigned int flags,
				u64 alt[]);
	u64             (*bhrb_filter_map)(u64 branch_sample_type);
	void            (*config_bhrb)(u64 pmu_bhrb_filter);
	void		(*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
	int		(*limited_pmc_event)(u64 event_id);
	u32		flags;
	const struct attribute_group	**attr_groups;
	int		n_generic;
	int		*generic_events;
	int		(*cache_events)[PERF_COUNT_HW_CACHE_MAX]
			       [PERF_COUNT_HW_CACHE_OP_MAX]
			       [PERF_COUNT_HW_CACHE_RESULT_MAX];

	/* BHRB entries in the PMU */
	int		bhrb_nr;
};

/*
 * Values for power_pmu.flags
 */
#define PPMU_LIMITED_PMC5_6	0x00000001 /* PMC5/6 have limited function */
#define PPMU_ALT_SIPR		0x00000002 /* uses alternate posn for SIPR/HV */
#define PPMU_NO_SIPR		0x00000004 /* no SIPR/HV in MMCRA at all */
#define PPMU_NO_CONT_SAMPLING	0x00000008 /* no continuous sampling */
#define PPMU_SIAR_VALID		0x00000010 /* Processor has SIAR Valid bit */
#define PPMU_HAS_SSLOT		0x00000020 /* Has sampled slot in MMCRA */
#define PPMU_HAS_SIER		0x00000040 /* Has SIER */
#define PPMU_BHRB		0x00000080 /* has BHRB feature enabled */
#define PPMU_EBB		0x00000100 /* supports event based branch */

/*
 * Values for flags to get_alternatives()
 */
#define PPMU_LIMITED_PMC_OK	1	/* can put this on a limited PMC */
#define PPMU_LIMITED_PMC_REQD	2	/* have to put this on a limited PMC */
#define PPMU_ONLY_COUNT_RUN	4	/* only counting in run state */

extern int register_power_pmu(struct power_pmu *);

struct pt_regs;
extern unsigned long perf_misc_flags(struct pt_regs *regs);
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long int read_bhrb(int n);

/*
 * Only override the default definitions in include/linux/perf_event.h
 * if we have hardware PMU support.
 */
#ifdef CONFIG_PPC_PERF_CTRS
#define perf_misc_flags(regs)	perf_misc_flags(regs)
#endif

/*
 * The power_pmu.get_constraint function returns a 32/64-bit value and
 * a 32/64-bit mask that express the constraints between this event_id and
 * other events.
 *
 * The value and mask are divided up into (non-overlapping) bitfields
 * of three different types:
 *
 * Select field: this expresses the constraint that some set of bits
 * in MMCR* needs to be set to a specific value for this event_id.  For a
 * select field, the mask contains 1s in every bit of the field, and
 * the value contains a unique value for each possible setting of the
 * MMCR* bits.  The constraint checking code will ensure that two events
 * that set the same field in their masks have the same value in their
 * value dwords.
 *
 * Add field: this expresses the constraint that there can be at most
 * N events in a particular class.  A field of k bits can be used for
 * N <= 2^(k-1) - 1.  The mask has the most significant bit of the field
 * set (and the other bits 0), and the value has only the least significant
 * bit of the field set.  In addition, the 'add_fields' and 'test_adder'
 * in the struct power_pmu for this processor come into play.  The
 * add_fields value contains 1 in the LSB of the field, and the
 * test_adder contains 2^(k-1) - 1 - N in the field.
 *
 * NAND field: this expresses the constraint that you may not have events
 * in all of a set of classes.  (For example, on PPC970, you can't select
 * events from the FPU, ISU and IDU simultaneously, although any two are
 * possible.)  For N classes, the field is N+1 bits wide, and each class
 * is assigned one bit from the least-significant N bits.  The mask has
 * only the most-significant bit set, and the value has only the bit
 * for the event_id's class set.  The test_adder has the least significant
 * bit set in the field.
 *
 * If an event_id is not subject to the constraint expressed by a particular
 * field, then it will have 0 in both the mask and value for that field.
 */

extern ssize_t power_events_sysfs_show(struct device *dev,
				struct device_attribute *attr, char *page);

/*
 * EVENT_VAR() is same as PMU_EVENT_VAR with a suffix.
 *
 * Having a suffix allows us to have aliases in sysfs - eg: the generic
 * event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and
 * 'PM_CYC' where the latter is the name by which the event is known in
 * POWER CPU specification.
 */
#define	EVENT_VAR(_id, _suffix)		event_attr_##_id##_suffix
#define	EVENT_PTR(_id, _suffix)		&EVENT_VAR(_id, _suffix).attr.attr

#define	EVENT_ATTR(_name, _id, _suffix)					\
	PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_PM_##_id,	\
			power_events_sysfs_show)

#define	GENERIC_EVENT_ATTR(_name, _id)	EVENT_ATTR(_name, _id, _g)
#define	GENERIC_EVENT_PTR(_id)		EVENT_PTR(_id, _g)

#define	POWER_EVENT_ATTR(_name, _id)	EVENT_ATTR(PM_##_name, _id, _p)
#define	POWER_EVENT_PTR(_id)		EVENT_PTR(_id, _p)
Commit	Line	Data
a1110654 SW	1	/*
	2	* Performance event support - PowerPC classic/server specific definitions.
	3	*
	4	* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <asm/hw_irq.h>
1c53a270	14	#include <linux/device.h>
8d7c55d0	15	#include <uapi/asm/perf_event.h>
a1110654 SW	16
	17	#define MAX_HWEVENTS 8
	18	#define MAX_EVENT_ALTERNATIVES 8
	19	#define MAX_LIMITED_HWCOUNTERS 2
	20
	21	/*
	22	* This struct provides the constants and functions needed to
	23	* describe the PMU on a particular POWER-family CPU.
	24	*/
	25	struct power_pmu {
	26	const char *name;
	27	int n_counter;
	28	int max_alternatives;
	29	unsigned long add_fields;
	30	unsigned long test_adder;
	31	int (*compute_mmcr)(u64 events[], int n_ev,
	32	unsigned int hwc[], unsigned long mmcr[]);
	33	int (get_constraint)(u64 event_id, unsigned long mskp,
	34	unsigned long *valp);
	35	int (*get_alternatives)(u64 event_id, unsigned int flags,
	36	u64 alt[]);
5afc9b52 AK	37	u64 (*bhrb_filter_map)(u64 branch_sample_type);
5afc9b52 AK	38	void (*config_bhrb)(u64 pmu_bhrb_filter);
a1110654 SW	39	void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
	40	int (*limited_pmc_event)(u64 event_id);
	41	u32 flags;
1c53a270	42	const struct attribute_group **attr_groups;
a1110654 SW	43	int n_generic;
	44	int *generic_events;
	45	int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
	46	[PERF_COUNT_HW_CACHE_OP_MAX]
	47	[PERF_COUNT_HW_CACHE_RESULT_MAX];
5afc9b52 AK	48
	49	/* BHRB entries in the PMU */
	50	int bhrb_nr;
a1110654 SW	51	};
	52
	53	/*
	54	* Values for power_pmu.flags
	55	*/
6f79cb81 AK	56	#define PPMU_LIMITED_PMC5_6 0x00000001 /* PMC5/6 have limited function */
	57	#define PPMU_ALT_SIPR 0x00000002 /* uses alternate posn for SIPR/HV */
	58	#define PPMU_NO_SIPR 0x00000004 /* no SIPR/HV in MMCRA at all */
	59	#define PPMU_NO_CONT_SAMPLING 0x00000008 /* no continuous sampling */
	60	#define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */
7a786832	61	#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
8f61aa32	62	#define PPMU_HAS_SIER 0x00000040 /* Has SIER */
5afc9b52	63	#define PPMU_BHRB 0x00000080 /* has BHRB feature enabled */
330a1eb7	64	#define PPMU_EBB 0x00000100 /* supports event based branch */
a1110654 SW	65
	66	/*
	67	* Values for flags to get_alternatives()
	68	*/
	69	#define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */
	70	#define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
	71	#define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */
	72
	73	extern int register_power_pmu(struct power_pmu *);
	74
	75	struct pt_regs;
	76	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	77	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
3925f46b	78	extern unsigned long int read_bhrb(int n);
a1110654	79
a1110654 SW	80	/*
	81	* Only override the default definitions in include/linux/perf_event.h
	82	* if we have hardware PMU support.
	83	*/
	84	#ifdef CONFIG_PPC_PERF_CTRS
	85	#define perf_misc_flags(regs) perf_misc_flags(regs)
	86	#endif
	87
	88	/*
	89	* The power_pmu.get_constraint function returns a 32/64-bit value and
	90	* a 32/64-bit mask that express the constraints between this event_id and
	91	* other events.
	92	*
	93	* The value and mask are divided up into (non-overlapping) bitfields
	94	* of three different types:
	95	*
	96	* Select field: this expresses the constraint that some set of bits
	97	* in MMCR* needs to be set to a specific value for this event_id. For a
	98	* select field, the mask contains 1s in every bit of the field, and
	99	* the value contains a unique value for each possible setting of the
	100	* MMCR* bits. The constraint checking code will ensure that two events
	101	* that set the same field in their masks have the same value in their
	102	* value dwords.
	103	*
	104	* Add field: this expresses the constraint that there can be at most
	105	* N events in a particular class. A field of k bits can be used for
	106	* N <= 2^(k-1) - 1. The mask has the most significant bit of the field
	107	* set (and the other bits 0), and the value has only the least significant
	108	* bit of the field set. In addition, the 'add_fields' and 'test_adder'
	109	* in the struct power_pmu for this processor come into play. The
	110	* add_fields value contains 1 in the LSB of the field, and the
	111	* test_adder contains 2^(k-1) - 1 - N in the field.
	112	*
	113	* NAND field: this expresses the constraint that you may not have events
	114	* in all of a set of classes. (For example, on PPC970, you can't select
	115	* events from the FPU, ISU and IDU simultaneously, although any two are
	116	* possible.) For N classes, the field is N+1 bits wide, and each class
	117	* is assigned one bit from the least-significant N bits. The mask has
	118	* only the most-significant bit set, and the value has only the bit
	119	* for the event_id's class set. The test_adder has the least significant
	120	* bit set in the field.
	121	*
	122	* If an event_id is not subject to the constraint expressed by a particular
	123	* field, then it will have 0 in both the mask and value for that field.
	124	*/
1c53a270 SB	125
	126	extern ssize_t power_events_sysfs_show(struct device *dev,
	127	struct device_attribute attr, char page);
	128
	129	/*
	130	* EVENT_VAR() is same as PMU_EVENT_VAR with a suffix.
	131	*
	132	* Having a suffix allows us to have aliases in sysfs - eg: the generic
	133	* event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and
	134	* 'PM_CYC' where the latter is the name by which the event is known in
	135	* POWER CPU specification.
	136	*/
	137	#define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix
f2b4367a	138	#define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr
1c53a270 SB	139
	140	#define EVENT_ATTR(_name, _id, _suffix) \
	141	PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_PM_##_id, \
	142	power_events_sysfs_show)
	143
	144	#define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
	145	#define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)
886c3b2d SB	146
	147	#define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(PM_##_name, _id, _p)
	148	#define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p)