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16c57b36 KG |
1 | /* |
2 | * Copyright 2009 Freescale Semicondutor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * provides masks and opcode images for use by code generation, emulation | |
10 | * and for instructions that older assemblers might not know about | |
11 | */ | |
12 | #ifndef _ASM_POWERPC_PPC_OPCODE_H | |
13 | #define _ASM_POWERPC_PPC_OPCODE_H | |
14 | ||
15 | #include <linux/stringify.h> | |
16 | #include <asm/asm-compat.h> | |
17 | ||
82fff310 MN |
18 | #define R0 0 |
19 | #define R1 1 | |
20 | #define R2 2 | |
21 | #define R3 3 | |
22 | #define R4 4 | |
23 | #define R5 5 | |
24 | #define R6 6 | |
25 | #define R7 7 | |
26 | #define R8 8 | |
27 | #define R9 9 | |
28 | #define R10 10 | |
29 | #define R11 11 | |
30 | #define R12 12 | |
31 | #define R13 13 | |
32 | #define R14 14 | |
33 | #define R15 15 | |
34 | #define R16 16 | |
35 | #define R17 17 | |
36 | #define R18 18 | |
37 | #define R19 19 | |
38 | #define R20 20 | |
39 | #define R21 21 | |
40 | #define R22 22 | |
41 | #define R23 23 | |
42 | #define R24 24 | |
43 | #define R25 25 | |
44 | #define R26 26 | |
45 | #define R27 27 | |
46 | #define R28 28 | |
47 | #define R29 29 | |
48 | #define R30 30 | |
49 | #define R31 31 | |
50 | ||
0972def4 MN |
51 | #define __REG_R0 0 |
52 | #define __REG_R1 1 | |
53 | #define __REG_R2 2 | |
54 | #define __REG_R3 3 | |
55 | #define __REG_R4 4 | |
56 | #define __REG_R5 5 | |
57 | #define __REG_R6 6 | |
58 | #define __REG_R7 7 | |
59 | #define __REG_R8 8 | |
60 | #define __REG_R9 9 | |
61 | #define __REG_R10 10 | |
62 | #define __REG_R11 11 | |
63 | #define __REG_R12 12 | |
64 | #define __REG_R13 13 | |
65 | #define __REG_R14 14 | |
66 | #define __REG_R15 15 | |
67 | #define __REG_R16 16 | |
68 | #define __REG_R17 17 | |
69 | #define __REG_R18 18 | |
70 | #define __REG_R19 19 | |
71 | #define __REG_R20 20 | |
72 | #define __REG_R21 21 | |
73 | #define __REG_R22 22 | |
74 | #define __REG_R23 23 | |
75 | #define __REG_R24 24 | |
76 | #define __REG_R25 25 | |
77 | #define __REG_R26 26 | |
78 | #define __REG_R27 27 | |
79 | #define __REG_R28 28 | |
80 | #define __REG_R29 29 | |
81 | #define __REG_R30 30 | |
82 | #define __REG_R31 31 | |
83 | ||
16c57b36 KG |
84 | /* sorted alphabetically */ |
85 | #define PPC_INST_DCBA 0x7c0005ec | |
86 | #define PPC_INST_DCBA_MASK 0xfc0007fe | |
87 | #define PPC_INST_DCBAL 0x7c2005ec | |
88 | #define PPC_INST_DCBZL 0x7c2007ec | |
89 | #define PPC_INST_ISEL 0x7c00001e | |
90 | #define PPC_INST_ISEL_MASK 0xfc00003e | |
864b9e6f | 91 | #define PPC_INST_LDARX 0x7c0000a8 |
16c57b36 KG |
92 | #define PPC_INST_LSWI 0x7c0004aa |
93 | #define PPC_INST_LSWX 0x7c00042a | |
d6ccb1f5 | 94 | #define PPC_INST_LWARX 0x7c000028 |
16c57b36 | 95 | #define PPC_INST_LWSYNC 0x7c2004ac |
dfb432cb | 96 | #define PPC_INST_LXVD2X 0x7c000698 |
16c57b36 KG |
97 | #define PPC_INST_MCRXR 0x7c000400 |
98 | #define PPC_INST_MCRXR_MASK 0xfc0007fe | |
99 | #define PPC_INST_MFSPR_PVR 0x7c1f42a6 | |
100 | #define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff | |
101 | #define PPC_INST_MSGSND 0x7c00019c | |
102 | #define PPC_INST_NOP 0x60000000 | |
103 | #define PPC_INST_POPCNTB 0x7c0000f4 | |
104 | #define PPC_INST_POPCNTB_MASK 0xfc0007fe | |
b5f9b666 AB |
105 | #define PPC_INST_POPCNTD 0x7c0003f4 |
106 | #define PPC_INST_POPCNTW 0x7c0002f4 | |
16c57b36 KG |
107 | #define PPC_INST_RFCI 0x4c000066 |
108 | #define PPC_INST_RFDI 0x4c00004e | |
109 | #define PPC_INST_RFMCI 0x4c00004c | |
efcac658 AK |
110 | #define PPC_INST_MFSPR_DSCR 0x7c1102a6 |
111 | #define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff | |
112 | #define PPC_INST_MTSPR_DSCR 0x7c1103a6 | |
113 | #define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff | |
697d3899 | 114 | #define PPC_INST_SLBFEE 0x7c0007a7 |
16c57b36 KG |
115 | |
116 | #define PPC_INST_STRING 0x7c00042a | |
117 | #define PPC_INST_STRING_MASK 0xfc0007fe | |
118 | #define PPC_INST_STRING_GEN_MASK 0xfc00067e | |
119 | ||
120 | #define PPC_INST_STSWI 0x7c0005aa | |
121 | #define PPC_INST_STSWX 0x7c00052a | |
dfb432cb | 122 | #define PPC_INST_STXVD2X 0x7c000798 |
60dbf438 | 123 | #define PPC_INST_TLBIE 0x7c000264 |
7281f5dc | 124 | #define PPC_INST_TLBILX 0x7c000024 |
16c57b36 | 125 | #define PPC_INST_WAIT 0x7c00007c |
29c09e8f BH |
126 | #define PPC_INST_TLBIVAX 0x7c000624 |
127 | #define PPC_INST_TLBSRX_DOT 0x7c0006a5 | |
0016a4cf | 128 | #define PPC_INST_XXLOR 0xf0000510 |
16c57b36 | 129 | |
948cf67c BH |
130 | #define PPC_INST_NAP 0x4c000364 |
131 | #define PPC_INST_SLEEP 0x4c0003a4 | |
132 | ||
931e1241 BH |
133 | /* A2 specific instructions */ |
134 | #define PPC_INST_ERATWE 0x7c0001a6 | |
135 | #define PPC_INST_ERATRE 0x7c000166 | |
136 | #define PPC_INST_ERATILX 0x7c000066 | |
137 | #define PPC_INST_ERATIVAX 0x7c000666 | |
138 | #define PPC_INST_ERATSX 0x7c000126 | |
139 | #define PPC_INST_ERATSX_DOT 0x7c000127 | |
140 | ||
0ca87f05 ME |
141 | /* Misc instructions for BPF compiler */ |
142 | #define PPC_INST_LD 0xe8000000 | |
143 | #define PPC_INST_LHZ 0xa0000000 | |
144 | #define PPC_INST_LWZ 0x80000000 | |
145 | #define PPC_INST_STD 0xf8000000 | |
146 | #define PPC_INST_STDU 0xf8000001 | |
147 | #define PPC_INST_MFLR 0x7c0802a6 | |
148 | #define PPC_INST_MTLR 0x7c0803a6 | |
149 | #define PPC_INST_CMPWI 0x2c000000 | |
150 | #define PPC_INST_CMPDI 0x2c200000 | |
151 | #define PPC_INST_CMPLW 0x7c000040 | |
152 | #define PPC_INST_CMPLWI 0x28000000 | |
153 | #define PPC_INST_ADDI 0x38000000 | |
154 | #define PPC_INST_ADDIS 0x3c000000 | |
155 | #define PPC_INST_ADD 0x7c000214 | |
156 | #define PPC_INST_SUB 0x7c000050 | |
157 | #define PPC_INST_BLR 0x4e800020 | |
158 | #define PPC_INST_BLRL 0x4e800021 | |
159 | #define PPC_INST_MULLW 0x7c0001d6 | |
160 | #define PPC_INST_MULHWU 0x7c000016 | |
161 | #define PPC_INST_MULLI 0x1c000000 | |
162 | #define PPC_INST_DIVWU 0x7c0003d6 | |
163 | #define PPC_INST_RLWINM 0x54000000 | |
164 | #define PPC_INST_RLDICR 0x78000004 | |
165 | #define PPC_INST_SLW 0x7c000030 | |
166 | #define PPC_INST_SRW 0x7c000430 | |
167 | #define PPC_INST_AND 0x7c000038 | |
168 | #define PPC_INST_ANDDOT 0x7c000039 | |
169 | #define PPC_INST_OR 0x7c000378 | |
170 | #define PPC_INST_ANDI 0x70000000 | |
171 | #define PPC_INST_ORI 0x60000000 | |
172 | #define PPC_INST_ORIS 0x64000000 | |
173 | #define PPC_INST_NEG 0x7c0000d0 | |
174 | #define PPC_INST_BRANCH 0x48000000 | |
175 | #define PPC_INST_BRANCH_COND 0x40800000 | |
4404a9f9 MN |
176 | #define PPC_INST_LBZCIX 0x7c0006aa |
177 | #define PPC_INST_STBCIX 0x7c0007aa | |
0ca87f05 | 178 | |
16c57b36 | 179 | /* macros to insert fields into opcodes */ |
55a5db18 MN |
180 | #define ___PPC_RA(a) (((a) & 0x1f) << 16) |
181 | #define ___PPC_RB(b) (((b) & 0x1f) << 11) | |
182 | #define ___PPC_RS(s) (((s) & 0x1f) << 21) | |
183 | #define ___PPC_RT(t) ___PPC_RS(t) | |
da6b43c8 MN |
184 | #define __PPC_RA(a) (((a) & 0x1f) << 16) |
185 | #define __PPC_RB(b) (((b) & 0x1f) << 11) | |
60dbf438 | 186 | #define __PPC_RS(s) (((s) & 0x1f) << 21) |
4e14a4d1 | 187 | #define __PPC_RT(s) __PPC_RS(s) |
0016a4cf PM |
188 | #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3)) |
189 | #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) | |
dfb432cb | 190 | #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) |
0016a4cf | 191 | #define __PPC_XT(s) __PPC_XS(s) |
da6b43c8 MN |
192 | #define __PPC_T_TLB(t) (((t) & 0x3) << 21) |
193 | #define __PPC_WC(w) (((w) & 0x3) << 21) | |
931e1241 | 194 | #define __PPC_WS(w) (((w) & 0x1f) << 11) |
0ca87f05 ME |
195 | #define __PPC_SH(s) __PPC_WS(s) |
196 | #define __PPC_MB(s) (((s) & 0x1f) << 6) | |
197 | #define __PPC_ME(s) (((s) & 0x1f) << 1) | |
198 | #define __PPC_BI(s) (((s) & 0x1f) << 16) | |
931e1241 | 199 | |
4e14a4d1 | 200 | /* |
d6ccb1f5 KG |
201 | * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a |
202 | * larx with EH set as an illegal instruction. | |
4e14a4d1 AB |
203 | */ |
204 | #ifdef CONFIG_PPC64 | |
205 | #define __PPC_EH(eh) (((eh) & 0x1) << 0) | |
206 | #else | |
207 | #define __PPC_EH(eh) 0 | |
208 | #endif | |
16c57b36 KG |
209 | |
210 | /* Deal with instructions that older assemblers aren't aware of */ | |
211 | #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ | |
212 | __PPC_RA(a) | __PPC_RB(b)) | |
213 | #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ | |
214 | __PPC_RA(a) | __PPC_RB(b)) | |
864b9e6f | 215 | #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ |
cdaade71 MN |
216 | ___PPC_RT(t) | ___PPC_RA(a) | \ |
217 | ___PPC_RB(b) | __PPC_EH(eh)) | |
4e14a4d1 | 218 | #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ |
cdaade71 MN |
219 | ___PPC_RT(t) | ___PPC_RA(a) | \ |
220 | ___PPC_RB(b) | __PPC_EH(eh)) | |
16c57b36 | 221 | #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ |
cdaade71 | 222 | ___PPC_RB(b)) |
b5f9b666 AB |
223 | #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ |
224 | __PPC_RA(a) | __PPC_RS(s)) | |
225 | #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ | |
226 | __PPC_RA(a) | __PPC_RS(s)) | |
227 | #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \ | |
228 | __PPC_RA(a) | __PPC_RS(s)) | |
16c57b36 KG |
229 | #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) |
230 | #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) | |
231 | #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) | |
232 | #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ | |
323d23ae | 233 | __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) |
16c57b36 KG |
234 | #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) |
235 | #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) | |
236 | #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) | |
237 | #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ | |
238 | __PPC_WC(w)) | |
60dbf438 | 239 | #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ |
cdaade71 | 240 | ___PPC_RB(a) | ___PPC_RS(lp)) |
29c09e8f BH |
241 | #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ |
242 | __PPC_RA(a) | __PPC_RB(b)) | |
243 | #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ | |
244 | __PPC_RA(a) | __PPC_RB(b)) | |
16c57b36 | 245 | |
931e1241 BH |
246 | #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \ |
247 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) | |
248 | #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \ | |
249 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) | |
250 | #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \ | |
251 | __PPC_T_TLB(t) | __PPC_RA(a) | \ | |
252 | __PPC_RB(b)) | |
253 | #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \ | |
254 | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) | |
255 | #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \ | |
256 | __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b)) | |
257 | #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \ | |
258 | __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b)) | |
697d3899 PM |
259 | #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ |
260 | __PPC_RT(t) | __PPC_RB(b)) | |
4404a9f9 MN |
261 | /* PASemi instructions */ |
262 | #define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \ | |
263 | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b)) | |
264 | #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \ | |
265 | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) | |
931e1241 | 266 | |
dfb432cb MN |
267 | /* |
268 | * Define what the VSX XX1 form instructions will look like, then add | |
269 | * the 128 bit load store instructions based on that. | |
270 | */ | |
271 | #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) | |
0016a4cf | 272 | #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b)) |
dfb432cb | 273 | #define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \ |
178f2ae0 | 274 | VSX_XX1((s), a, b)) |
dfb432cb | 275 | #define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \ |
178f2ae0 | 276 | VSX_XX1((s), a, b)) |
0016a4cf | 277 | #define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \ |
178f2ae0 | 278 | VSX_XX3((t), a, b)) |
dfb432cb | 279 | |
948cf67c BH |
280 | #define PPC_NAP stringify_in_c(.long PPC_INST_NAP) |
281 | #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP) | |
282 | ||
16c57b36 | 283 | #endif /* _ASM_POWERPC_PPC_OPCODE_H */ |