Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. |
1da177e4 | 3 | */ |
5f7c6907 KG |
4 | #ifndef _ASM_POWERPC_PPC_ASM_H |
5 | #define _ASM_POWERPC_PPC_ASM_H | |
6 | ||
9203fc9c | 7 | #include <linux/init.h> |
40ef8cbc | 8 | #include <linux/stringify.h> |
3ddfbcf1 | 9 | #include <asm/asm-compat.h> |
9c75a31c | 10 | #include <asm/processor.h> |
16c57b36 | 11 | #include <asm/ppc-opcode.h> |
cf9efce0 | 12 | #include <asm/firmware.h> |
40ef8cbc | 13 | |
3ddfbcf1 DG |
14 | #ifndef __ASSEMBLY__ |
15 | #error __FILE__ should only be used in assembler files | |
16 | #else | |
17 | ||
18 | #define SZL (BITS_PER_LONG/8) | |
1da177e4 | 19 | |
c6622f63 PM |
20 | /* |
21 | * Stuff for accurate CPU time accounting. | |
22 | * These macros handle transitions between user and system state | |
23 | * in exception entry and exit and accumulate time to the | |
24 | * user_time and system_time fields in the paca. | |
25 | */ | |
26 | ||
abf917cd | 27 | #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE |
c6622f63 PM |
28 | #define ACCOUNT_CPU_USER_ENTRY(ra, rb) |
29 | #define ACCOUNT_CPU_USER_EXIT(ra, rb) | |
cf9efce0 | 30 | #define ACCOUNT_STOLEN_TIME |
c6622f63 PM |
31 | #else |
32 | #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ | |
cf9efce0 PM |
33 | MFTB(ra); /* get timebase */ \ |
34 | ld rb,PACA_STARTTIME_USER(r13); \ | |
35 | std ra,PACA_STARTTIME(r13); \ | |
c6622f63 PM |
36 | subf rb,rb,ra; /* subtract start value */ \ |
37 | ld ra,PACA_USER_TIME(r13); \ | |
38 | add ra,ra,rb; /* add on to user time */ \ | |
39 | std ra,PACA_USER_TIME(r13); \ | |
c6622f63 PM |
40 | |
41 | #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ | |
cf9efce0 PM |
42 | MFTB(ra); /* get timebase */ \ |
43 | ld rb,PACA_STARTTIME(r13); \ | |
44 | std ra,PACA_STARTTIME_USER(r13); \ | |
c6622f63 PM |
45 | subf rb,rb,ra; /* subtract start value */ \ |
46 | ld ra,PACA_SYSTEM_TIME(r13); \ | |
cf9efce0 PM |
47 | add ra,ra,rb; /* add on to system time */ \ |
48 | std ra,PACA_SYSTEM_TIME(r13) | |
49 | ||
50 | #ifdef CONFIG_PPC_SPLPAR | |
51 | #define ACCOUNT_STOLEN_TIME \ | |
52 | BEGIN_FW_FTR_SECTION; \ | |
53 | beq 33f; \ | |
54 | /* from user - see if there are any DTL entries to process */ \ | |
55 | ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ | |
56 | ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ | |
57 | ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \ | |
58 | cmpd cr1,r11,r10; \ | |
59 | beq+ cr1,33f; \ | |
60 | bl .accumulate_stolen_time; \ | |
990118c8 BH |
61 | ld r12,_MSR(r1); \ |
62 | andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ | |
cf9efce0 PM |
63 | 33: \ |
64 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) | |
65 | ||
66 | #else /* CONFIG_PPC_SPLPAR */ | |
67 | #define ACCOUNT_STOLEN_TIME | |
68 | ||
69 | #endif /* CONFIG_PPC_SPLPAR */ | |
70 | ||
abf917cd | 71 | #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ |
c6622f63 | 72 | |
1da177e4 LT |
73 | /* |
74 | * Macros for storing registers into and loading registers from | |
75 | * exception frames. | |
76 | */ | |
5f7c6907 KG |
77 | #ifdef __powerpc64__ |
78 | #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) | |
79 | #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) | |
80 | #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) | |
81 | #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) | |
82 | #else | |
1da177e4 | 83 | #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) |
5f7c6907 KG |
84 | #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) |
85 | #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ | |
86 | SAVE_10GPRS(22, base) | |
87 | #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ | |
88 | REST_10GPRS(22, base) | |
89 | #endif | |
90 | ||
1da177e4 LT |
91 | #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) |
92 | #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) | |
93 | #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) | |
94 | #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) | |
1da177e4 LT |
95 | #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) |
96 | #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) | |
97 | #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) | |
98 | #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) | |
99 | ||
9c75a31c | 100 | #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) |
1da177e4 LT |
101 | #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) |
102 | #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) | |
103 | #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) | |
104 | #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) | |
105 | #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) | |
9c75a31c | 106 | #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) |
1da177e4 LT |
107 | #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) |
108 | #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) | |
109 | #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) | |
110 | #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) | |
111 | #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) | |
112 | ||
23e55f92 | 113 | #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b |
5f7c6907 KG |
114 | #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) |
115 | #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) | |
116 | #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) | |
117 | #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) | |
118 | #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) | |
23e55f92 | 119 | #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b |
5f7c6907 KG |
120 | #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) |
121 | #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) | |
122 | #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) | |
123 | #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) | |
124 | #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) | |
1da177e4 | 125 | |
8b3c34cf MN |
126 | /* Save/restore FPRs, VRs and VSRs from their checkpointed backups in |
127 | * thread_struct: | |
128 | */ | |
129 | #define SAVE_FPR_TRANSACT(n, base) stfd n,THREAD_TRANSACT_FPR0+ \ | |
130 | 8*TS_FPRWIDTH*(n)(base) | |
131 | #define SAVE_2FPRS_TRANSACT(n, base) SAVE_FPR_TRANSACT(n, base); \ | |
132 | SAVE_FPR_TRANSACT(n+1, base) | |
133 | #define SAVE_4FPRS_TRANSACT(n, base) SAVE_2FPRS_TRANSACT(n, base); \ | |
134 | SAVE_2FPRS_TRANSACT(n+2, base) | |
135 | #define SAVE_8FPRS_TRANSACT(n, base) SAVE_4FPRS_TRANSACT(n, base); \ | |
136 | SAVE_4FPRS_TRANSACT(n+4, base) | |
137 | #define SAVE_16FPRS_TRANSACT(n, base) SAVE_8FPRS_TRANSACT(n, base); \ | |
138 | SAVE_8FPRS_TRANSACT(n+8, base) | |
139 | #define SAVE_32FPRS_TRANSACT(n, base) SAVE_16FPRS_TRANSACT(n, base); \ | |
140 | SAVE_16FPRS_TRANSACT(n+16, base) | |
141 | ||
142 | #define REST_FPR_TRANSACT(n, base) lfd n,THREAD_TRANSACT_FPR0+ \ | |
143 | 8*TS_FPRWIDTH*(n)(base) | |
144 | #define REST_2FPRS_TRANSACT(n, base) REST_FPR_TRANSACT(n, base); \ | |
145 | REST_FPR_TRANSACT(n+1, base) | |
146 | #define REST_4FPRS_TRANSACT(n, base) REST_2FPRS_TRANSACT(n, base); \ | |
147 | REST_2FPRS_TRANSACT(n+2, base) | |
148 | #define REST_8FPRS_TRANSACT(n, base) REST_4FPRS_TRANSACT(n, base); \ | |
149 | REST_4FPRS_TRANSACT(n+4, base) | |
150 | #define REST_16FPRS_TRANSACT(n, base) REST_8FPRS_TRANSACT(n, base); \ | |
151 | REST_8FPRS_TRANSACT(n+8, base) | |
152 | #define REST_32FPRS_TRANSACT(n, base) REST_16FPRS_TRANSACT(n, base); \ | |
153 | REST_16FPRS_TRANSACT(n+16, base) | |
154 | ||
155 | ||
156 | #define SAVE_VR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VR0+(16*(n)); \ | |
157 | stvx n,b,base | |
158 | #define SAVE_2VRS_TRANSACT(n,b,base) SAVE_VR_TRANSACT(n,b,base); \ | |
159 | SAVE_VR_TRANSACT(n+1,b,base) | |
160 | #define SAVE_4VRS_TRANSACT(n,b,base) SAVE_2VRS_TRANSACT(n,b,base); \ | |
161 | SAVE_2VRS_TRANSACT(n+2,b,base) | |
162 | #define SAVE_8VRS_TRANSACT(n,b,base) SAVE_4VRS_TRANSACT(n,b,base); \ | |
163 | SAVE_4VRS_TRANSACT(n+4,b,base) | |
164 | #define SAVE_16VRS_TRANSACT(n,b,base) SAVE_8VRS_TRANSACT(n,b,base); \ | |
165 | SAVE_8VRS_TRANSACT(n+8,b,base) | |
166 | #define SAVE_32VRS_TRANSACT(n,b,base) SAVE_16VRS_TRANSACT(n,b,base); \ | |
167 | SAVE_16VRS_TRANSACT(n+16,b,base) | |
168 | ||
169 | #define REST_VR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VR0+(16*(n)); \ | |
170 | lvx n,b,base | |
171 | #define REST_2VRS_TRANSACT(n,b,base) REST_VR_TRANSACT(n,b,base); \ | |
172 | REST_VR_TRANSACT(n+1,b,base) | |
173 | #define REST_4VRS_TRANSACT(n,b,base) REST_2VRS_TRANSACT(n,b,base); \ | |
174 | REST_2VRS_TRANSACT(n+2,b,base) | |
175 | #define REST_8VRS_TRANSACT(n,b,base) REST_4VRS_TRANSACT(n,b,base); \ | |
176 | REST_4VRS_TRANSACT(n+4,b,base) | |
177 | #define REST_16VRS_TRANSACT(n,b,base) REST_8VRS_TRANSACT(n,b,base); \ | |
178 | REST_8VRS_TRANSACT(n+8,b,base) | |
179 | #define REST_32VRS_TRANSACT(n,b,base) REST_16VRS_TRANSACT(n,b,base); \ | |
180 | REST_16VRS_TRANSACT(n+16,b,base) | |
181 | ||
182 | ||
183 | #define SAVE_VSR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VSR0+(16*(n)); \ | |
184 | STXVD2X(n,R##base,R##b) | |
185 | #define SAVE_2VSRS_TRANSACT(n,b,base) SAVE_VSR_TRANSACT(n,b,base); \ | |
186 | SAVE_VSR_TRANSACT(n+1,b,base) | |
187 | #define SAVE_4VSRS_TRANSACT(n,b,base) SAVE_2VSRS_TRANSACT(n,b,base); \ | |
188 | SAVE_2VSRS_TRANSACT(n+2,b,base) | |
189 | #define SAVE_8VSRS_TRANSACT(n,b,base) SAVE_4VSRS_TRANSACT(n,b,base); \ | |
190 | SAVE_4VSRS_TRANSACT(n+4,b,base) | |
191 | #define SAVE_16VSRS_TRANSACT(n,b,base) SAVE_8VSRS_TRANSACT(n,b,base); \ | |
192 | SAVE_8VSRS_TRANSACT(n+8,b,base) | |
193 | #define SAVE_32VSRS_TRANSACT(n,b,base) SAVE_16VSRS_TRANSACT(n,b,base); \ | |
194 | SAVE_16VSRS_TRANSACT(n+16,b,base) | |
195 | ||
196 | #define REST_VSR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VSR0+(16*(n)); \ | |
197 | LXVD2X(n,R##base,R##b) | |
198 | #define REST_2VSRS_TRANSACT(n,b,base) REST_VSR_TRANSACT(n,b,base); \ | |
199 | REST_VSR_TRANSACT(n+1,b,base) | |
200 | #define REST_4VSRS_TRANSACT(n,b,base) REST_2VSRS_TRANSACT(n,b,base); \ | |
201 | REST_2VSRS_TRANSACT(n+2,b,base) | |
202 | #define REST_8VSRS_TRANSACT(n,b,base) REST_4VSRS_TRANSACT(n,b,base); \ | |
203 | REST_4VSRS_TRANSACT(n+4,b,base) | |
204 | #define REST_16VSRS_TRANSACT(n,b,base) REST_8VSRS_TRANSACT(n,b,base); \ | |
205 | REST_8VSRS_TRANSACT(n+8,b,base) | |
206 | #define REST_32VSRS_TRANSACT(n,b,base) REST_16VSRS_TRANSACT(n,b,base); \ | |
207 | REST_16VSRS_TRANSACT(n+16,b,base) | |
208 | ||
72ffff5b | 209 | /* Save the lower 32 VSRs in the thread VSR region */ |
0b7673c3 | 210 | #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b) |
72ffff5b MN |
211 | #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) |
212 | #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) | |
213 | #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) | |
214 | #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) | |
215 | #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) | |
0b7673c3 | 216 | #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b) |
72ffff5b MN |
217 | #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) |
218 | #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) | |
219 | #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) | |
220 | #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) | |
221 | #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) | |
222 | /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ | |
0b7673c3 | 223 | #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b) |
72ffff5b MN |
224 | #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) |
225 | #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) | |
226 | #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) | |
227 | #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) | |
228 | #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) | |
0b7673c3 | 229 | #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b) |
72ffff5b MN |
230 | #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) |
231 | #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) | |
232 | #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) | |
233 | #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) | |
234 | #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) | |
235 | ||
c51584d5 SW |
236 | /* |
237 | * b = base register for addressing, o = base offset from register of 1st EVR | |
238 | * n = first EVR, s = scratch | |
239 | */ | |
240 | #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) | |
241 | #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) | |
242 | #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) | |
243 | #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) | |
244 | #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) | |
245 | #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) | |
246 | #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n | |
247 | #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) | |
248 | #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) | |
249 | #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) | |
250 | #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) | |
251 | #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) | |
5f7c6907 | 252 | |
8c71632f ME |
253 | /* Macros to adjust thread priority for hardware multithreading */ |
254 | #define HMT_VERY_LOW or 31,31,31 # very low priority | |
255 | #define HMT_LOW or 1,1,1 | |
256 | #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority | |
257 | #define HMT_MEDIUM or 2,2,2 | |
258 | #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority | |
259 | #define HMT_HIGH or 3,3,3 | |
50fb8ebe | 260 | #define HMT_EXTRA_HIGH or 7,7,7 # power7 only |
5f7c6907 | 261 | |
d72be892 MN |
262 | #ifdef CONFIG_PPC64 |
263 | #define ULONG_SIZE 8 | |
264 | #else | |
265 | #define ULONG_SIZE 4 | |
266 | #endif | |
0b7673c3 MN |
267 | #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) |
268 | #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) | |
d72be892 | 269 | |
88ced031 | 270 | #ifdef __KERNEL__ |
40ef8cbc PM |
271 | #ifdef CONFIG_PPC64 |
272 | ||
44ce6a5e | 273 | #define STACKFRAMESIZE 256 |
0b7673c3 MN |
274 | #define __STK_REG(i) (112 + ((i)-14)*8) |
275 | #define STK_REG(i) __STK_REG(__REG_##i) | |
44ce6a5e | 276 | |
0b7673c3 MN |
277 | #define __STK_PARAM(i) (48 + ((i)-3)*8) |
278 | #define STK_PARAM(i) __STK_PARAM(__REG_##i) | |
44ce6a5e | 279 | |
40ef8cbc PM |
280 | #define XGLUE(a,b) a##b |
281 | #define GLUE(a,b) XGLUE(a,b) | |
282 | ||
283 | #define _GLOBAL(name) \ | |
284 | .section ".text"; \ | |
285 | .align 2 ; \ | |
286 | .globl name; \ | |
287 | .globl GLUE(.,name); \ | |
288 | .section ".opd","aw"; \ | |
289 | name: \ | |
290 | .quad GLUE(.,name); \ | |
291 | .quad .TOC.@tocbase; \ | |
292 | .quad 0; \ | |
293 | .previous; \ | |
294 | .type GLUE(.,name),@function; \ | |
295 | GLUE(.,name): | |
296 | ||
fc68e869 | 297 | #define _INIT_GLOBAL(name) \ |
9203fc9c | 298 | __REF; \ |
fc68e869 SR |
299 | .align 2 ; \ |
300 | .globl name; \ | |
301 | .globl GLUE(.,name); \ | |
302 | .section ".opd","aw"; \ | |
303 | name: \ | |
304 | .quad GLUE(.,name); \ | |
305 | .quad .TOC.@tocbase; \ | |
306 | .quad 0; \ | |
307 | .previous; \ | |
308 | .type GLUE(.,name),@function; \ | |
309 | GLUE(.,name): | |
310 | ||
40ef8cbc PM |
311 | #define _KPROBE(name) \ |
312 | .section ".kprobes.text","a"; \ | |
313 | .align 2 ; \ | |
314 | .globl name; \ | |
315 | .globl GLUE(.,name); \ | |
316 | .section ".opd","aw"; \ | |
317 | name: \ | |
318 | .quad GLUE(.,name); \ | |
319 | .quad .TOC.@tocbase; \ | |
320 | .quad 0; \ | |
321 | .previous; \ | |
322 | .type GLUE(.,name),@function; \ | |
323 | GLUE(.,name): | |
324 | ||
325 | #define _STATIC(name) \ | |
326 | .section ".text"; \ | |
327 | .align 2 ; \ | |
328 | .section ".opd","aw"; \ | |
329 | name: \ | |
330 | .quad GLUE(.,name); \ | |
331 | .quad .TOC.@tocbase; \ | |
332 | .quad 0; \ | |
333 | .previous; \ | |
334 | .type GLUE(.,name),@function; \ | |
c40b91b5 SR |
335 | GLUE(.,name): |
336 | ||
337 | #define _INIT_STATIC(name) \ | |
9203fc9c | 338 | __REF; \ |
c40b91b5 SR |
339 | .align 2 ; \ |
340 | .section ".opd","aw"; \ | |
341 | name: \ | |
342 | .quad GLUE(.,name); \ | |
343 | .quad .TOC.@tocbase; \ | |
344 | .quad 0; \ | |
345 | .previous; \ | |
346 | .type GLUE(.,name),@function; \ | |
40ef8cbc PM |
347 | GLUE(.,name): |
348 | ||
349 | #else /* 32-bit */ | |
350 | ||
748a7683 KG |
351 | #define _ENTRY(n) \ |
352 | .globl n; \ | |
353 | n: | |
354 | ||
40ef8cbc PM |
355 | #define _GLOBAL(n) \ |
356 | .text; \ | |
357 | .stabs __stringify(n:F-1),N_FUN,0,0,n;\ | |
358 | .globl n; \ | |
359 | n: | |
360 | ||
361 | #define _KPROBE(n) \ | |
362 | .section ".kprobes.text","a"; \ | |
363 | .globl n; \ | |
364 | n: | |
365 | ||
366 | #endif | |
367 | ||
5f7c6907 | 368 | /* |
e58c3495 DG |
369 | * LOAD_REG_IMMEDIATE(rn, expr) |
370 | * Loads the value of the constant expression 'expr' into register 'rn' | |
371 | * using immediate instructions only. Use this when it's important not | |
372 | * to reference other data (i.e. on ppc64 when the TOC pointer is not | |
e31aa453 | 373 | * valid) and when 'expr' is a constant or absolute address. |
5f7c6907 | 374 | * |
e58c3495 DG |
375 | * LOAD_REG_ADDR(rn, name) |
376 | * Loads the address of label 'name' into register 'rn'. Use this when | |
377 | * you don't particularly need immediate instructions only, but you need | |
378 | * the whole address in one register (e.g. it's a structure address and | |
379 | * you want to access various offsets within it). On ppc32 this is | |
380 | * identical to LOAD_REG_IMMEDIATE. | |
381 | * | |
382 | * LOAD_REG_ADDRBASE(rn, name) | |
383 | * ADDROFF(name) | |
384 | * LOAD_REG_ADDRBASE loads part of the address of label 'name' into | |
385 | * register 'rn'. ADDROFF(name) returns the remainder of the address as | |
386 | * a constant expression. ADDROFF(name) is a signed expression < 16 bits | |
387 | * in size, so is suitable for use directly as an offset in load and store | |
388 | * instructions. Use this when loading/storing a single word or less as: | |
389 | * LOAD_REG_ADDRBASE(rX, name) | |
390 | * ld rY,ADDROFF(name)(rX) | |
5f7c6907 KG |
391 | */ |
392 | #ifdef __powerpc64__ | |
e58c3495 | 393 | #define LOAD_REG_IMMEDIATE(reg,expr) \ |
564aa5cf MN |
394 | lis reg,(expr)@highest; \ |
395 | ori reg,reg,(expr)@higher; \ | |
396 | rldicr reg,reg,32,31; \ | |
397 | oris reg,reg,(expr)@h; \ | |
398 | ori reg,reg,(expr)@l; | |
e58c3495 DG |
399 | |
400 | #define LOAD_REG_ADDR(reg,name) \ | |
564aa5cf | 401 | ld reg,name@got(r2) |
e58c3495 DG |
402 | |
403 | #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) | |
404 | #define ADDROFF(name) 0 | |
b85a046a | 405 | |
f78541dc PM |
406 | /* offsets for stack frame layout */ |
407 | #define LRSAVE 16 | |
b85a046a PM |
408 | |
409 | #else /* 32-bit */ | |
70620186 | 410 | |
e58c3495 | 411 | #define LOAD_REG_IMMEDIATE(reg,expr) \ |
564aa5cf MN |
412 | lis reg,(expr)@ha; \ |
413 | addi reg,reg,(expr)@l; | |
e58c3495 DG |
414 | |
415 | #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) | |
b85a046a | 416 | |
564aa5cf | 417 | #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha |
e58c3495 | 418 | #define ADDROFF(name) name@l |
b85a046a | 419 | |
f78541dc PM |
420 | /* offsets for stack frame layout */ |
421 | #define LRSAVE 4 | |
b85a046a | 422 | |
5f7c6907 | 423 | #endif |
1da177e4 | 424 | |
5f7c6907 | 425 | /* various errata or part fixups */ |
1da177e4 LT |
426 | #ifdef CONFIG_PPC601_SYNC_FIX |
427 | #define SYNC \ | |
428 | BEGIN_FTR_SECTION \ | |
429 | sync; \ | |
430 | isync; \ | |
431 | END_FTR_SECTION_IFSET(CPU_FTR_601) | |
432 | #define SYNC_601 \ | |
433 | BEGIN_FTR_SECTION \ | |
434 | sync; \ | |
435 | END_FTR_SECTION_IFSET(CPU_FTR_601) | |
436 | #define ISYNC_601 \ | |
437 | BEGIN_FTR_SECTION \ | |
438 | isync; \ | |
439 | END_FTR_SECTION_IFSET(CPU_FTR_601) | |
440 | #else | |
441 | #define SYNC | |
442 | #define SYNC_601 | |
443 | #define ISYNC_601 | |
444 | #endif | |
445 | ||
859deea9 BH |
446 | #ifdef CONFIG_PPC_CELL |
447 | #define MFTB(dest) \ | |
448 | 90: mftb dest; \ | |
449 | BEGIN_FTR_SECTION_NESTED(96); \ | |
450 | cmpwi dest,0; \ | |
451 | beq- 90b; \ | |
452 | END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) | |
453 | #else | |
454 | #define MFTB(dest) mftb dest | |
455 | #endif | |
5f7c6907 | 456 | |
1da177e4 LT |
457 | #ifndef CONFIG_SMP |
458 | #define TLBSYNC | |
459 | #else /* CONFIG_SMP */ | |
460 | /* tlbsync is not implemented on 601 */ | |
461 | #define TLBSYNC \ | |
462 | BEGIN_FTR_SECTION \ | |
463 | tlbsync; \ | |
464 | sync; \ | |
465 | END_FTR_SECTION_IFCLR(CPU_FTR_601) | |
466 | #endif | |
467 | ||
694caf02 AB |
468 | #ifdef CONFIG_PPC64 |
469 | #define MTOCRF(FXM, RS) \ | |
470 | BEGIN_FTR_SECTION_NESTED(848); \ | |
86e32fdc | 471 | mtcrf (FXM), RS; \ |
694caf02 | 472 | FTR_SECTION_ELSE_NESTED(848); \ |
86e32fdc | 473 | mtocrf (FXM), RS; \ |
694caf02 | 474 | ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) |
13e7a8e8 HM |
475 | |
476 | /* | |
477 | * PPR restore macros used in entry_64.S | |
478 | * Used for P7 or later processors | |
479 | */ | |
480 | #define HMT_MEDIUM_LOW_HAS_PPR \ | |
481 | BEGIN_FTR_SECTION_NESTED(944) \ | |
482 | HMT_MEDIUM_LOW; \ | |
483 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944) | |
484 | ||
485 | #define SET_DEFAULT_THREAD_PPR(ra, rb) \ | |
486 | BEGIN_FTR_SECTION_NESTED(945) \ | |
487 | lis ra,INIT_PPR@highest; /* default ppr=3 */ \ | |
488 | ld rb,PACACURRENT(r13); \ | |
489 | sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \ | |
490 | std ra,TASKTHREADPPR(rb); \ | |
491 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945) | |
492 | ||
493 | #define RESTORE_PPR(ra, rb) \ | |
494 | BEGIN_FTR_SECTION_NESTED(946) \ | |
495 | ld ra,PACACURRENT(r13); \ | |
496 | ld rb,TASKTHREADPPR(ra); \ | |
497 | mtspr SPRN_PPR,rb; /* Restore PPR */ \ | |
498 | END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946) | |
499 | ||
694caf02 AB |
500 | #endif |
501 | ||
1da177e4 LT |
502 | /* |
503 | * This instruction is not implemented on the PPC 603 or 601; however, on | |
504 | * the 403GCX and 405GP tlbia IS defined and tlbie is not. | |
505 | * All of these instructions exist in the 8xx, they have magical powers, | |
506 | * and they must be used. | |
507 | */ | |
508 | ||
509 | #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) | |
510 | #define tlbia \ | |
511 | li r4,1024; \ | |
512 | mtctr r4; \ | |
513 | lis r4,KERNELBASE@h; \ | |
514 | 0: tlbie r4; \ | |
515 | addi r4,r4,0x1000; \ | |
516 | bdnz 0b | |
517 | #endif | |
518 | ||
5f7c6907 | 519 | |
5f7c6907 KG |
520 | #ifdef CONFIG_IBM440EP_ERR42 |
521 | #define PPC440EP_ERR42 isync | |
522 | #else | |
523 | #define PPC440EP_ERR42 | |
524 | #endif | |
525 | ||
a515348f MN |
526 | /* The following stops all load and store data streams associated with stream |
527 | * ID (ie. streams created explicitly). The embedded and server mnemonics for | |
528 | * dcbt are different so we use machine "power4" here explicitly. | |
529 | */ | |
530 | #define DCBT_STOP_ALL_STREAM_IDS(scratch) \ | |
531 | .machine push ; \ | |
532 | .machine "power4" ; \ | |
533 | lis scratch,0x60000000@h; \ | |
534 | dcbt r0,scratch,0b01010; \ | |
535 | .machine pop | |
536 | ||
44c58ccc BH |
537 | /* |
538 | * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them | |
539 | * keep the address intact to be compatible with code shared with | |
540 | * 32-bit classic. | |
541 | * | |
542 | * On the other hand, I find it useful to have them behave as expected | |
543 | * by their name (ie always do the addition) on 64-bit BookE | |
544 | */ | |
545 | #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) | |
6316222e PM |
546 | #define toreal(rd) |
547 | #define fromreal(rd) | |
548 | ||
2ca7633d RM |
549 | /* |
550 | * We use addis to ensure compatibility with the "classic" ppc versions of | |
551 | * these macros, which use rs = 0 to get the tophys offset in rd, rather than | |
552 | * converting the address in r0, and so this version has to do that too | |
553 | * (i.e. set register rd to 0 when rs == 0). | |
554 | */ | |
1da177e4 LT |
555 | #define tophys(rd,rs) \ |
556 | addis rd,rs,0 | |
557 | ||
558 | #define tovirt(rd,rs) \ | |
559 | addis rd,rs,0 | |
560 | ||
5f7c6907 | 561 | #elif defined(CONFIG_PPC64) |
6316222e PM |
562 | #define toreal(rd) /* we can access c000... in real mode */ |
563 | #define fromreal(rd) | |
564 | ||
5f7c6907 | 565 | #define tophys(rd,rs) \ |
6316222e | 566 | clrldi rd,rs,2 |
5f7c6907 KG |
567 | |
568 | #define tovirt(rd,rs) \ | |
6316222e PM |
569 | rotldi rd,rs,16; \ |
570 | ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ | |
571 | rotldi rd,rd,48 | |
5f7c6907 | 572 | #else |
1da177e4 LT |
573 | /* |
574 | * On APUS (Amiga PowerPC cpu upgrade board), we don't know the | |
575 | * physical base address of RAM at compile time. | |
576 | */ | |
6316222e PM |
577 | #define toreal(rd) tophys(rd,rd) |
578 | #define fromreal(rd) tovirt(rd,rd) | |
579 | ||
1da177e4 | 580 | #define tophys(rd,rs) \ |
ccdcef72 | 581 | 0: addis rd,rs,-PAGE_OFFSET@h; \ |
1da177e4 LT |
582 | .section ".vtop_fixup","aw"; \ |
583 | .align 1; \ | |
584 | .long 0b; \ | |
585 | .previous | |
586 | ||
587 | #define tovirt(rd,rs) \ | |
ccdcef72 | 588 | 0: addis rd,rs,PAGE_OFFSET@h; \ |
1da177e4 LT |
589 | .section ".ptov_fixup","aw"; \ |
590 | .align 1; \ | |
591 | .long 0b; \ | |
592 | .previous | |
5f7c6907 | 593 | #endif |
1da177e4 | 594 | |
44c58ccc | 595 | #ifdef CONFIG_PPC_BOOK3S_64 |
40ef8cbc PM |
596 | #define RFI rfid |
597 | #define MTMSRD(r) mtmsrd r | |
b38c77d8 | 598 | #define MTMSR_EERI(reg) mtmsrd reg,1 |
1da177e4 LT |
599 | #else |
600 | #define FIX_SRR1(ra, rb) | |
601 | #ifndef CONFIG_40x | |
602 | #define RFI rfi | |
603 | #else | |
604 | #define RFI rfi; b . /* Prevent prefetch past rfi */ | |
605 | #endif | |
606 | #define MTMSRD(r) mtmsr r | |
b38c77d8 | 607 | #define MTMSR_EERI(reg) mtmsr reg |
1da177e4 | 608 | #define CLR_TOP32(r) |
c9cf73ae MP |
609 | #endif |
610 | ||
88ced031 AB |
611 | #endif /* __KERNEL__ */ |
612 | ||
1da177e4 LT |
613 | /* The boring bits... */ |
614 | ||
615 | /* Condition Register Bit Fields */ | |
616 | ||
617 | #define cr0 0 | |
618 | #define cr1 1 | |
619 | #define cr2 2 | |
620 | #define cr3 3 | |
621 | #define cr4 4 | |
622 | #define cr5 5 | |
623 | #define cr6 6 | |
624 | #define cr7 7 | |
625 | ||
626 | ||
9a13a524 MN |
627 | /* |
628 | * General Purpose Registers (GPRs) | |
629 | * | |
630 | * The lower case r0-r31 should be used in preference to the upper | |
631 | * case R0-R31 as they provide more error checking in the assembler. | |
632 | * Use R0-31 only when really nessesary. | |
633 | */ | |
634 | ||
635 | #define r0 %r0 | |
636 | #define r1 %r1 | |
637 | #define r2 %r2 | |
638 | #define r3 %r3 | |
639 | #define r4 %r4 | |
640 | #define r5 %r5 | |
641 | #define r6 %r6 | |
642 | #define r7 %r7 | |
643 | #define r8 %r8 | |
644 | #define r9 %r9 | |
645 | #define r10 %r10 | |
646 | #define r11 %r11 | |
647 | #define r12 %r12 | |
648 | #define r13 %r13 | |
649 | #define r14 %r14 | |
650 | #define r15 %r15 | |
651 | #define r16 %r16 | |
652 | #define r17 %r17 | |
653 | #define r18 %r18 | |
654 | #define r19 %r19 | |
655 | #define r20 %r20 | |
656 | #define r21 %r21 | |
657 | #define r22 %r22 | |
658 | #define r23 %r23 | |
659 | #define r24 %r24 | |
660 | #define r25 %r25 | |
661 | #define r26 %r26 | |
662 | #define r27 %r27 | |
663 | #define r28 %r28 | |
664 | #define r29 %r29 | |
665 | #define r30 %r30 | |
666 | #define r31 %r31 | |
1da177e4 LT |
667 | |
668 | ||
669 | /* Floating Point Registers (FPRs) */ | |
670 | ||
671 | #define fr0 0 | |
672 | #define fr1 1 | |
673 | #define fr2 2 | |
674 | #define fr3 3 | |
675 | #define fr4 4 | |
676 | #define fr5 5 | |
677 | #define fr6 6 | |
678 | #define fr7 7 | |
679 | #define fr8 8 | |
680 | #define fr9 9 | |
681 | #define fr10 10 | |
682 | #define fr11 11 | |
683 | #define fr12 12 | |
684 | #define fr13 13 | |
685 | #define fr14 14 | |
686 | #define fr15 15 | |
687 | #define fr16 16 | |
688 | #define fr17 17 | |
689 | #define fr18 18 | |
690 | #define fr19 19 | |
691 | #define fr20 20 | |
692 | #define fr21 21 | |
693 | #define fr22 22 | |
694 | #define fr23 23 | |
695 | #define fr24 24 | |
696 | #define fr25 25 | |
697 | #define fr26 26 | |
698 | #define fr27 27 | |
699 | #define fr28 28 | |
700 | #define fr29 29 | |
701 | #define fr30 30 | |
702 | #define fr31 31 | |
703 | ||
5f7c6907 KG |
704 | /* AltiVec Registers (VPRs) */ |
705 | ||
1da177e4 LT |
706 | #define vr0 0 |
707 | #define vr1 1 | |
708 | #define vr2 2 | |
709 | #define vr3 3 | |
710 | #define vr4 4 | |
711 | #define vr5 5 | |
712 | #define vr6 6 | |
713 | #define vr7 7 | |
714 | #define vr8 8 | |
715 | #define vr9 9 | |
716 | #define vr10 10 | |
717 | #define vr11 11 | |
718 | #define vr12 12 | |
719 | #define vr13 13 | |
720 | #define vr14 14 | |
721 | #define vr15 15 | |
722 | #define vr16 16 | |
723 | #define vr17 17 | |
724 | #define vr18 18 | |
725 | #define vr19 19 | |
726 | #define vr20 20 | |
727 | #define vr21 21 | |
728 | #define vr22 22 | |
729 | #define vr23 23 | |
730 | #define vr24 24 | |
731 | #define vr25 25 | |
732 | #define vr26 26 | |
733 | #define vr27 27 | |
734 | #define vr28 28 | |
735 | #define vr29 29 | |
736 | #define vr30 30 | |
737 | #define vr31 31 | |
738 | ||
72ffff5b MN |
739 | /* VSX Registers (VSRs) */ |
740 | ||
741 | #define vsr0 0 | |
742 | #define vsr1 1 | |
743 | #define vsr2 2 | |
744 | #define vsr3 3 | |
745 | #define vsr4 4 | |
746 | #define vsr5 5 | |
747 | #define vsr6 6 | |
748 | #define vsr7 7 | |
749 | #define vsr8 8 | |
750 | #define vsr9 9 | |
751 | #define vsr10 10 | |
752 | #define vsr11 11 | |
753 | #define vsr12 12 | |
754 | #define vsr13 13 | |
755 | #define vsr14 14 | |
756 | #define vsr15 15 | |
757 | #define vsr16 16 | |
758 | #define vsr17 17 | |
759 | #define vsr18 18 | |
760 | #define vsr19 19 | |
761 | #define vsr20 20 | |
762 | #define vsr21 21 | |
763 | #define vsr22 22 | |
764 | #define vsr23 23 | |
765 | #define vsr24 24 | |
766 | #define vsr25 25 | |
767 | #define vsr26 26 | |
768 | #define vsr27 27 | |
769 | #define vsr28 28 | |
770 | #define vsr29 29 | |
771 | #define vsr30 30 | |
772 | #define vsr31 31 | |
773 | #define vsr32 32 | |
774 | #define vsr33 33 | |
775 | #define vsr34 34 | |
776 | #define vsr35 35 | |
777 | #define vsr36 36 | |
778 | #define vsr37 37 | |
779 | #define vsr38 38 | |
780 | #define vsr39 39 | |
781 | #define vsr40 40 | |
782 | #define vsr41 41 | |
783 | #define vsr42 42 | |
784 | #define vsr43 43 | |
785 | #define vsr44 44 | |
786 | #define vsr45 45 | |
787 | #define vsr46 46 | |
788 | #define vsr47 47 | |
789 | #define vsr48 48 | |
790 | #define vsr49 49 | |
791 | #define vsr50 50 | |
792 | #define vsr51 51 | |
793 | #define vsr52 52 | |
794 | #define vsr53 53 | |
795 | #define vsr54 54 | |
796 | #define vsr55 55 | |
797 | #define vsr56 56 | |
798 | #define vsr57 57 | |
799 | #define vsr58 58 | |
800 | #define vsr59 59 | |
801 | #define vsr60 60 | |
802 | #define vsr61 61 | |
803 | #define vsr62 62 | |
804 | #define vsr63 63 | |
805 | ||
5f7c6907 KG |
806 | /* SPE Registers (EVPRs) */ |
807 | ||
1da177e4 LT |
808 | #define evr0 0 |
809 | #define evr1 1 | |
810 | #define evr2 2 | |
811 | #define evr3 3 | |
812 | #define evr4 4 | |
813 | #define evr5 5 | |
814 | #define evr6 6 | |
815 | #define evr7 7 | |
816 | #define evr8 8 | |
817 | #define evr9 9 | |
818 | #define evr10 10 | |
819 | #define evr11 11 | |
820 | #define evr12 12 | |
821 | #define evr13 13 | |
822 | #define evr14 14 | |
823 | #define evr15 15 | |
824 | #define evr16 16 | |
825 | #define evr17 17 | |
826 | #define evr18 18 | |
827 | #define evr19 19 | |
828 | #define evr20 20 | |
829 | #define evr21 21 | |
830 | #define evr22 22 | |
831 | #define evr23 23 | |
832 | #define evr24 24 | |
833 | #define evr25 25 | |
834 | #define evr26 26 | |
835 | #define evr27 27 | |
836 | #define evr28 28 | |
837 | #define evr29 29 | |
838 | #define evr30 30 | |
839 | #define evr31 31 | |
840 | ||
841 | /* some stab codes */ | |
842 | #define N_FUN 36 | |
843 | #define N_RSYM 64 | |
844 | #define N_SLINE 68 | |
845 | #define N_SO 100 | |
5f7c6907 | 846 | |
5f7c6907 KG |
847 | #endif /* __ASSEMBLY__ */ |
848 | ||
849 | #endif /* _ASM_POWERPC_PPC_ASM_H */ |