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powerpc: Define ppr in thread_struct
[deliverable/linux.git] / arch / powerpc / include / asm / ppc_asm.h
CommitLineData
1da177e4 1/*
1da177e4 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
1da177e4 3 */
5f7c6907
KG		 4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
9203fc9c 7#include <linux/init.h>
40ef8cbc 8#include <linux/stringify.h>
3ddfbcf1 9#include <asm/asm-compat.h>
9c75a31c 10#include <asm/processor.h>
16c57b36 11#include <asm/ppc-opcode.h>
cf9efce0 12#include <asm/firmware.h>
40ef8cbc 13
3ddfbcf1
DG		 14#ifndef __ASSEMBLY__
15#error __FILE__ should only be used in assembler files
16#else
17
18#define SZL (BITS_PER_LONG/8)
1da177e4 19
c6622f63
PM		 20/*
21 * Stuff for accurate CPU time accounting.
22 * These macros handle transitions between user and system state
23 * in exception entry and exit and accumulate time to the
24 * user_time and system_time fields in the paca.
25 */
26
27#ifndef CONFIG_VIRT_CPU_ACCOUNTING
28#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
29#define ACCOUNT_CPU_USER_EXIT(ra, rb)
cf9efce0 30#define ACCOUNT_STOLEN_TIME
c6622f63
PM		 31#else
32#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
cf9efce0
PM		 33 MFTB(ra); /* get timebase */ \
34 ld rb,PACA_STARTTIME_USER(r13); \
35 std ra,PACA_STARTTIME(r13); \
c6622f63
PM		 36 subf rb,rb,ra; /* subtract start value */ \
37 ld ra,PACA_USER_TIME(r13); \
38 add ra,ra,rb; /* add on to user time */ \
39 std ra,PACA_USER_TIME(r13); \
c6622f63
PM		 40
41#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
cf9efce0
PM		 42 MFTB(ra); /* get timebase */ \
43 ld rb,PACA_STARTTIME(r13); \
44 std ra,PACA_STARTTIME_USER(r13); \
c6622f63
PM		 45 subf rb,rb,ra; /* subtract start value */ \
46 ld ra,PACA_SYSTEM_TIME(r13); \
cf9efce0
PM		 47 add ra,ra,rb; /* add on to system time */ \
48 std ra,PACA_SYSTEM_TIME(r13)
49
50#ifdef CONFIG_PPC_SPLPAR
51#define ACCOUNT_STOLEN_TIME \
52BEGIN_FW_FTR_SECTION; \
53 beq 33f; \
54 /* from user - see if there are any DTL entries to process */ \
55 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
56 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
57 ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \
58 cmpd cr1,r11,r10; \
59 beq+ cr1,33f; \
60 bl .accumulate_stolen_time; \
990118c8
BH		 61 ld r12,_MSR(r1); \
62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
cf9efce0
PM		 6333: \
64END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
65
66#else /* CONFIG_PPC_SPLPAR */
67#define ACCOUNT_STOLEN_TIME
68
69#endif /* CONFIG_PPC_SPLPAR */
70
71#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
c6622f63 72
1da177e4
LT		 73/*
74 * Macros for storing registers into and loading registers from
75 * exception frames.
76 */
5f7c6907
KG		 77#ifdef __powerpc64__
78#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
79#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
80#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
81#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
82#else
1da177e4 83#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
5f7c6907
KG		 84#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
85#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
86 SAVE_10GPRS(22, base)
87#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
88 REST_10GPRS(22, base)
89#endif
90
1da177e4
LT		 91#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
92#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
93#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
94#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
1da177e4
LT		 95#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
96#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
97#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
98#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
99
9c75a31c 100#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
1da177e4
LT		 101#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
102#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
103#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
104#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
105#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
9c75a31c 106#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
1da177e4
LT		 107#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
108#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
109#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
110#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
111#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
112
23e55f92 113#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b
5f7c6907
KG		 114#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
115#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
116#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
117#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
118#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
23e55f92 119#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b
5f7c6907
KG		 120#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
121#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
122#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
123#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
124#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
1da177e4 125
72ffff5b 126/* Save the lower 32 VSRs in the thread VSR region */
0b7673c3 127#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b)
72ffff5b
MN		 128#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
129#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
130#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
131#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
132#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
0b7673c3 133#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b)
72ffff5b
MN		 134#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
135#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
136#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
137#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
138#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
139/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
0b7673c3 140#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b)
72ffff5b
MN		 141#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
142#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
143#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
144#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
145#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
0b7673c3 146#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b)
72ffff5b
MN		 147#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
148#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
149#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
150#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
151#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
152
c51584d5
SW		 153/*
154 * b = base register for addressing, o = base offset from register of 1st EVR
155 * n = first EVR, s = scratch
156 */
157#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
158#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
159#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
160#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
161#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
162#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
163#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
164#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
165#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
166#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
167#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
168#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
5f7c6907 169
8c71632f
ME		 170/* Macros to adjust thread priority for hardware multithreading */
171#define HMT_VERY_LOW or 31,31,31 # very low priority
172#define HMT_LOW or 1,1,1
173#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
174#define HMT_MEDIUM or 2,2,2
175#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
176#define HMT_HIGH or 3,3,3
50fb8ebe 177#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
5f7c6907 178
d72be892
MN		 179#ifdef CONFIG_PPC64
180#define ULONG_SIZE 8
181#else
182#define ULONG_SIZE 4
183#endif
0b7673c3
MN		 184#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
185#define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
d72be892 186
88ced031 187#ifdef __KERNEL__
40ef8cbc
PM		 188#ifdef CONFIG_PPC64
189
44ce6a5e 190#define STACKFRAMESIZE 256
0b7673c3
MN		 191#define __STK_REG(i) (112 + ((i)-14)*8)
192#define STK_REG(i) __STK_REG(__REG_##i)
44ce6a5e 193
0b7673c3
MN		 194#define __STK_PARAM(i) (48 + ((i)-3)*8)
195#define STK_PARAM(i) __STK_PARAM(__REG_##i)
44ce6a5e 196
40ef8cbc
PM		 197#define XGLUE(a,b) a##b
198#define GLUE(a,b) XGLUE(a,b)
199
200#define _GLOBAL(name) \
201 .section ".text"; \
202 .align 2 ; \
203 .globl name; \
204 .globl GLUE(.,name); \
205 .section ".opd","aw"; \
206name: \
207 .quad GLUE(.,name); \
208 .quad .TOC.@tocbase; \
209 .quad 0; \
210 .previous; \
211 .type GLUE(.,name),@function; \
212GLUE(.,name):
213
fc68e869 214#define _INIT_GLOBAL(name) \
9203fc9c 215 __REF; \
fc68e869
SR		 216 .align 2 ; \
217 .globl name; \
218 .globl GLUE(.,name); \
219 .section ".opd","aw"; \
220name: \
221 .quad GLUE(.,name); \
222 .quad .TOC.@tocbase; \
223 .quad 0; \
224 .previous; \
225 .type GLUE(.,name),@function; \
226GLUE(.,name):
227
40ef8cbc
PM		 228#define _KPROBE(name) \
229 .section ".kprobes.text","a"; \
230 .align 2 ; \
231 .globl name; \
232 .globl GLUE(.,name); \
233 .section ".opd","aw"; \
234name: \
235 .quad GLUE(.,name); \
236 .quad .TOC.@tocbase; \
237 .quad 0; \
238 .previous; \
239 .type GLUE(.,name),@function; \
240GLUE(.,name):
241
242#define _STATIC(name) \
243 .section ".text"; \
244 .align 2 ; \
245 .section ".opd","aw"; \
246name: \
247 .quad GLUE(.,name); \
248 .quad .TOC.@tocbase; \
249 .quad 0; \
250 .previous; \
251 .type GLUE(.,name),@function; \
c40b91b5
SR		 252GLUE(.,name):
253
254#define _INIT_STATIC(name) \
9203fc9c 255 __REF; \
c40b91b5
SR		 256 .align 2 ; \
257 .section ".opd","aw"; \
258name: \
259 .quad GLUE(.,name); \
260 .quad .TOC.@tocbase; \
261 .quad 0; \
262 .previous; \
263 .type GLUE(.,name),@function; \
40ef8cbc
PM		 264GLUE(.,name):
265
266#else /* 32-bit */
267
748a7683
KG		 268#define _ENTRY(n) \
269 .globl n; \
270n:
271
40ef8cbc
PM		 272#define _GLOBAL(n) \
273 .text; \
274 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
275 .globl n; \
276n:
277
278#define _KPROBE(n) \
279 .section ".kprobes.text","a"; \
280 .globl n; \
281n:
282
283#endif
284
5f7c6907 285/*
e58c3495
DG		 286 * LOAD_REG_IMMEDIATE(rn, expr)
287 * Loads the value of the constant expression 'expr' into register 'rn'
288 * using immediate instructions only. Use this when it's important not
289 * to reference other data (i.e. on ppc64 when the TOC pointer is not
e31aa453 290 * valid) and when 'expr' is a constant or absolute address.
5f7c6907 291 *
e58c3495
DG		 292 * LOAD_REG_ADDR(rn, name)
293 * Loads the address of label 'name' into register 'rn'. Use this when
294 * you don't particularly need immediate instructions only, but you need
295 * the whole address in one register (e.g. it's a structure address and
296 * you want to access various offsets within it). On ppc32 this is
297 * identical to LOAD_REG_IMMEDIATE.
298 *
299 * LOAD_REG_ADDRBASE(rn, name)
300 * ADDROFF(name)
301 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
302 * register 'rn'. ADDROFF(name) returns the remainder of the address as
303 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
304 * in size, so is suitable for use directly as an offset in load and store
305 * instructions. Use this when loading/storing a single word or less as:
306 * LOAD_REG_ADDRBASE(rX, name)
307 * ld rY,ADDROFF(name)(rX)
5f7c6907
KG		 308 */
309#ifdef __powerpc64__
e58c3495 310#define LOAD_REG_IMMEDIATE(reg,expr) \
564aa5cf
MN		 311 lis reg,(expr)@highest; \
312 ori reg,reg,(expr)@higher; \
313 rldicr reg,reg,32,31; \
314 oris reg,reg,(expr)@h; \
315 ori reg,reg,(expr)@l;
e58c3495
DG		 316
317#define LOAD_REG_ADDR(reg,name) \
564aa5cf 318 ld reg,name@got(r2)
e58c3495
DG		 319
320#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
321#define ADDROFF(name) 0
b85a046a 322
f78541dc
PM		 323/* offsets for stack frame layout */
324#define LRSAVE 16
b85a046a
PM		 325
326#else /* 32-bit */
70620186 327
e58c3495 328#define LOAD_REG_IMMEDIATE(reg,expr) \
564aa5cf
MN		 329 lis reg,(expr)@ha; \
330 addi reg,reg,(expr)@l;
e58c3495
DG		 331
332#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
b85a046a 333
564aa5cf 334#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
e58c3495 335#define ADDROFF(name) name@l
b85a046a 336
f78541dc
PM		 337/* offsets for stack frame layout */
338#define LRSAVE 4
b85a046a 339
5f7c6907 340#endif
1da177e4 341
5f7c6907 342/* various errata or part fixups */
1da177e4
LT		 343#ifdef CONFIG_PPC601_SYNC_FIX
344#define SYNC \
345BEGIN_FTR_SECTION \
346 sync; \
347 isync; \
348END_FTR_SECTION_IFSET(CPU_FTR_601)
349#define SYNC_601 \
350BEGIN_FTR_SECTION \
351 sync; \
352END_FTR_SECTION_IFSET(CPU_FTR_601)
353#define ISYNC_601 \
354BEGIN_FTR_SECTION \
355 isync; \
356END_FTR_SECTION_IFSET(CPU_FTR_601)
357#else
358#define SYNC
359#define SYNC_601
360#define ISYNC_601
361#endif
362
859deea9
BH		 363#ifdef CONFIG_PPC_CELL
364#define MFTB(dest) \
36590: mftb dest; \
366BEGIN_FTR_SECTION_NESTED(96); \
367 cmpwi dest,0; \
368 beq- 90b; \
369END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
370#else
371#define MFTB(dest) mftb dest
372#endif
5f7c6907 373
1da177e4
LT		 374#ifndef CONFIG_SMP
375#define TLBSYNC
376#else /* CONFIG_SMP */
377/* tlbsync is not implemented on 601 */
378#define TLBSYNC \
379BEGIN_FTR_SECTION \
380 tlbsync; \
381 sync; \
382END_FTR_SECTION_IFCLR(CPU_FTR_601)
383#endif
384
694caf02
AB		 385#ifdef CONFIG_PPC64
386#define MTOCRF(FXM, RS) \
387 BEGIN_FTR_SECTION_NESTED(848); \
86e32fdc 388 mtcrf (FXM), RS; \
694caf02 389 FTR_SECTION_ELSE_NESTED(848); \
86e32fdc 390 mtocrf (FXM), RS; \
694caf02
AB		 391 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
392#endif
393
1da177e4
LT		 394/*
395 * This instruction is not implemented on the PPC 603 or 601; however, on
396 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
397 * All of these instructions exist in the 8xx, they have magical powers,
398 * and they must be used.
399 */
400
401#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
402#define tlbia \
403 li r4,1024; \
404 mtctr r4; \
405 lis r4,KERNELBASE@h; \
4060: tlbie r4; \
407 addi r4,r4,0x1000; \
408 bdnz 0b
409#endif
410
5f7c6907 411
5f7c6907
KG		 412#ifdef CONFIG_IBM440EP_ERR42
413#define PPC440EP_ERR42 isync
414#else
415#define PPC440EP_ERR42
416#endif
417
44c58ccc
BH		 418/*
419 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
420 * keep the address intact to be compatible with code shared with
421 * 32-bit classic.
422 *
423 * On the other hand, I find it useful to have them behave as expected
424 * by their name (ie always do the addition) on 64-bit BookE
425 */
426#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
6316222e
PM		 427#define toreal(rd)
428#define fromreal(rd)
429
2ca7633d
RM		 430/*
431 * We use addis to ensure compatibility with the "classic" ppc versions of
432 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
433 * converting the address in r0, and so this version has to do that too
434 * (i.e. set register rd to 0 when rs == 0).
435 */
1da177e4
LT		 436#define tophys(rd,rs) \
437 addis rd,rs,0
438
439#define tovirt(rd,rs) \
440 addis rd,rs,0
441
5f7c6907 442#elif defined(CONFIG_PPC64)
6316222e
PM		 443#define toreal(rd) /* we can access c000... in real mode */
444#define fromreal(rd)
445
5f7c6907 446#define tophys(rd,rs) \
6316222e 447 clrldi rd,rs,2
5f7c6907
KG		 448
449#define tovirt(rd,rs) \
6316222e
PM		 450 rotldi rd,rs,16; \
451 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
452 rotldi rd,rd,48
5f7c6907 453#else
1da177e4
LT		 454/*
455 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
456 * physical base address of RAM at compile time.
457 */
6316222e
PM		 458#define toreal(rd) tophys(rd,rd)
459#define fromreal(rd) tovirt(rd,rd)
460
1da177e4 461#define tophys(rd,rs) \
ccdcef72 4620: addis rd,rs,-PAGE_OFFSET@h; \
1da177e4
LT		 463 .section ".vtop_fixup","aw"; \
464 .align 1; \
465 .long 0b; \
466 .previous
467
468#define tovirt(rd,rs) \
ccdcef72 4690: addis rd,rs,PAGE_OFFSET@h; \
1da177e4
LT		 470 .section ".ptov_fixup","aw"; \
471 .align 1; \
472 .long 0b; \
473 .previous
5f7c6907 474#endif
1da177e4 475
44c58ccc 476#ifdef CONFIG_PPC_BOOK3S_64
40ef8cbc
PM		 477#define RFI rfid
478#define MTMSRD(r) mtmsrd r
b38c77d8 479#define MTMSR_EERI(reg) mtmsrd reg,1
1da177e4
LT		 480#else
481#define FIX_SRR1(ra, rb)
482#ifndef CONFIG_40x
483#define RFI rfi
484#else
485#define RFI rfi; b . /* Prevent prefetch past rfi */
486#endif
487#define MTMSRD(r) mtmsr r
b38c77d8 488#define MTMSR_EERI(reg) mtmsr reg
1da177e4 489#define CLR_TOP32(r)
c9cf73ae
MP		 490#endif
491
88ced031
AB		 492#endif /* __KERNEL__ */
493
1da177e4
LT		 494/* The boring bits... */
495
496/* Condition Register Bit Fields */
497
498#define cr0 0
499#define cr1 1
500#define cr2 2
501#define cr3 3
502#define cr4 4
503#define cr5 5
504#define cr6 6
505#define cr7 7
506
507
9a13a524
MN		 508/*
509 * General Purpose Registers (GPRs)
510 *
511 * The lower case r0-r31 should be used in preference to the upper
512 * case R0-R31 as they provide more error checking in the assembler.
513 * Use R0-31 only when really nessesary.
514 */
515
516#define r0 %r0
517#define r1 %r1
518#define r2 %r2
519#define r3 %r3
520#define r4 %r4
521#define r5 %r5
522#define r6 %r6
523#define r7 %r7
524#define r8 %r8
525#define r9 %r9
526#define r10 %r10
527#define r11 %r11
528#define r12 %r12
529#define r13 %r13
530#define r14 %r14
531#define r15 %r15
532#define r16 %r16
533#define r17 %r17
534#define r18 %r18
535#define r19 %r19
536#define r20 %r20
537#define r21 %r21
538#define r22 %r22
539#define r23 %r23
540#define r24 %r24
541#define r25 %r25
542#define r26 %r26
543#define r27 %r27
544#define r28 %r28
545#define r29 %r29
546#define r30 %r30
547#define r31 %r31
1da177e4
LT		 548
549
550/* Floating Point Registers (FPRs) */
551
552#define fr0 0
553#define fr1 1
554#define fr2 2
555#define fr3 3
556#define fr4 4
557#define fr5 5
558#define fr6 6
559#define fr7 7
560#define fr8 8
561#define fr9 9
562#define fr10 10
563#define fr11 11
564#define fr12 12
565#define fr13 13
566#define fr14 14
567#define fr15 15
568#define fr16 16
569#define fr17 17
570#define fr18 18
571#define fr19 19
572#define fr20 20
573#define fr21 21
574#define fr22 22
575#define fr23 23
576#define fr24 24
577#define fr25 25
578#define fr26 26
579#define fr27 27
580#define fr28 28
581#define fr29 29
582#define fr30 30
583#define fr31 31
584
5f7c6907
KG		 585/* AltiVec Registers (VPRs) */
586
1da177e4
LT		 587#define vr0 0
588#define vr1 1
589#define vr2 2
590#define vr3 3
591#define vr4 4
592#define vr5 5
593#define vr6 6
594#define vr7 7
595#define vr8 8
596#define vr9 9
597#define vr10 10
598#define vr11 11
599#define vr12 12
600#define vr13 13
601#define vr14 14
602#define vr15 15
603#define vr16 16
604#define vr17 17
605#define vr18 18
606#define vr19 19
607#define vr20 20
608#define vr21 21
609#define vr22 22
610#define vr23 23
611#define vr24 24
612#define vr25 25
613#define vr26 26
614#define vr27 27
615#define vr28 28
616#define vr29 29
617#define vr30 30
618#define vr31 31
619
72ffff5b
MN		 620/* VSX Registers (VSRs) */
621
622#define vsr0 0
623#define vsr1 1
624#define vsr2 2
625#define vsr3 3
626#define vsr4 4
627#define vsr5 5
628#define vsr6 6
629#define vsr7 7
630#define vsr8 8
631#define vsr9 9
632#define vsr10 10
633#define vsr11 11
634#define vsr12 12
635#define vsr13 13
636#define vsr14 14
637#define vsr15 15
638#define vsr16 16
639#define vsr17 17
640#define vsr18 18
641#define vsr19 19
642#define vsr20 20
643#define vsr21 21
644#define vsr22 22
645#define vsr23 23
646#define vsr24 24
647#define vsr25 25
648#define vsr26 26
649#define vsr27 27
650#define vsr28 28
651#define vsr29 29
652#define vsr30 30
653#define vsr31 31
654#define vsr32 32
655#define vsr33 33
656#define vsr34 34
657#define vsr35 35
658#define vsr36 36
659#define vsr37 37
660#define vsr38 38
661#define vsr39 39
662#define vsr40 40
663#define vsr41 41
664#define vsr42 42
665#define vsr43 43
666#define vsr44 44
667#define vsr45 45
668#define vsr46 46
669#define vsr47 47
670#define vsr48 48
671#define vsr49 49
672#define vsr50 50
673#define vsr51 51
674#define vsr52 52
675#define vsr53 53
676#define vsr54 54
677#define vsr55 55
678#define vsr56 56
679#define vsr57 57
680#define vsr58 58
681#define vsr59 59
682#define vsr60 60
683#define vsr61 61
684#define vsr62 62
685#define vsr63 63
686
5f7c6907
KG		 687/* SPE Registers (EVPRs) */
688
1da177e4
LT		 689#define evr0 0
690#define evr1 1
691#define evr2 2
692#define evr3 3
693#define evr4 4
694#define evr5 5
695#define evr6 6
696#define evr7 7
697#define evr8 8
698#define evr9 9
699#define evr10 10
700#define evr11 11
701#define evr12 12
702#define evr13 13
703#define evr14 14
704#define evr15 15
705#define evr16 16
706#define evr17 17
707#define evr18 18
708#define evr19 19
709#define evr20 20
710#define evr21 21
711#define evr22 22
712#define evr23 23
713#define evr24 24
714#define evr25 25
715#define evr26 26
716#define evr27 27
717#define evr28 28
718#define evr29 29
719#define evr30 30
720#define evr31 31
721
722/* some stab codes */
723#define N_FUN 36
724#define N_RSYM 64
725#define N_SLINE 68
726#define N_SO 100
5f7c6907 727
5f7c6907
KG		 728#endif /* __ASSEMBLY__ */
729
730#endif /* _ASM_POWERPC_PPC_ASM_H */
Linux kernel - Deliverables
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