[deliverable/linux.git] / arch / powerpc / kernel / cpu_setup_power.S

/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include <asm/book3s/64/mmu-hash.h>

/* Entry: r3 = crap, r4 = ptr to cputable entry
 *
 * Note that we can be called twice for pseudo-PVRs
 */
_GLOBAL(__setup_cpu_power7)
	mflr	r11
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	bl	__init_LPCR
	bl	__init_tlb_power7
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power7)
	mflr	r11
	mfmsr	r3
	rldicl.	r0,r3,4,63
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	bl	__init_LPCR
	bl	__init_tlb_power7
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	bl	__init_LPCR
	bl	__init_HFSCR
	bl	__init_tlb_power8
	bl	__init_PMU_HV
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr   r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	bl	__init_LPCR
	bl	__init_HFSCR
	bl	__init_tlb_power8
	bl	__init_PMU_HV
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	bl	__init_LPCR
	bl	__init_HFSCR
	bl	__init_tlb_power9
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr   r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	bl	__init_LPCR
	bl	__init_HFSCR
	bl	__init_tlb_power9
	mtlr	r11
	blr

__init_hvmode_206:
	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
	mfmsr	r3
	rldicl.	r0,r3,4,63
	bnelr
	ld	r5,CPU_SPEC_FEATURES(r4)
	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
	xor	r5,r5,r6
	std	r5,CPU_SPEC_FEATURES(r4)
	blr

__init_LPCR:
	/* Setup a sane LPCR:
	 *   Called with initial LPCR in R3
	 *
	 *   LPES = 0b01 (HSRR0/1 used for 0x500)
	 *   PECE = 0b111
	 *   DPFD = 4
	 *   HDICE = 0
	 *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	 *   VRMASD = 0b10000 (L=1, LP=00)
	 *
	 * Other bits untouched for now
	 */
	li	r5,1
	rldimi	r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
	ori	r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
	li	r5,4
	rldimi	r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	clrrdi	r3,r3,1		/* clear HDICE */
	li	r5,4
	rldimi	r3,r5, LPCR_VC_SH, 0
	li	r5,0x10
	rldimi	r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
	mtspr	SPRN_LPCR,r3
	isync
	blr

__init_FSCR:
	mfspr	r3,SPRN_FSCR
	ori	r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
	mtspr	SPRN_FSCR,r3
	blr

__init_HFSCR:
	mfspr	r3,SPRN_HFSCR
	ori	r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
		      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
	mtspr	SPRN_HFSCR,r3
	blr

/*
 * Clear the TLB using the specified IS form of tlbiel instruction
 * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
 */
__init_tlb_power7:
	li	r6,POWER7_TLB_SETS
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	ptesync
2:	tlbiel	r7
	addi	r7,r7,0x1000
	bdnz	2b
	ptesync
1:	blr

__init_tlb_power8:
	li	r6,POWER8_TLB_SETS
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	ptesync
2:	tlbiel	r7
	addi	r7,r7,0x1000
	bdnz	2b
	ptesync
1:	blr

__init_tlb_power9:
	li	r6,POWER9_TLB_SETS_HASH
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	ptesync
2:	tlbiel	r7
	addi	r7,r7,0x1000
	bdnz	2b
	ptesync
1:	blr

__init_PMU_HV:
	li	r5,0
	mtspr	SPRN_MMCRC,r5
	mtspr	SPRN_MMCRH,r5
	blr

__init_PMU:
	li	r5,0
	mtspr	SPRN_MMCRS,r5
	mtspr	SPRN_MMCRA,r5
	mtspr	SPRN_MMCR0,r5
	mtspr	SPRN_MMCR1,r5
	mtspr	SPRN_MMCR2,r5
	blr
Commit	Line	Data
24cc67de BH	1	/*
	2	* This file contains low level CPU setup functions.
	3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*
	10	*/
	11
	12	#include <asm/processor.h>
	13	#include <asm/page.h>
	14	#include <asm/cputable.h>
	15	#include <asm/ppc_asm.h>
	16	#include <asm/asm-offsets.h>
	17	#include <asm/cache.h>
f64e8084	18	#include <asm/book3s/64/mmu-hash.h>
24cc67de BH	19
	20	/* Entry: r3 = crap, r4 = ptr to cputable entry
	21	*
	22	* Note that we can be called twice for pseudo-PVRs
	23	*/
	24	_GLOBAL(__setup_cpu_power7)
	25	mflr r11
	26	bl __init_hvmode_206
	27	mtlr r11
	28	beqlr
b144871c BH	29	li r0,0
b144871c BH	30	mtspr SPRN_LPID,r0
f7c32c24	31	mfspr r3,SPRN_LPCR
24cc67de	32	bl __init_LPCR
04407050	33	bl __init_tlb_power7
24cc67de BH	34	mtlr r11
	35	blr
	36
	37	_GLOBAL(__restore_cpu_power7)
	38	mflr r11
	39	mfmsr r3
	40	rldicl. r0,r3,4,63
	41	beqlr
b144871c BH	42	li r0,0
b144871c BH	43	mtspr SPRN_LPID,r0
f7c32c24	44	mfspr r3,SPRN_LPCR
24cc67de	45	bl __init_LPCR
04407050	46	bl __init_tlb_power7
aec937b1 MN	47	mtlr r11
	48	blr
	49
	50	_GLOBAL(__setup_cpu_power8)
	51	mflr r11
57d23167	52	bl __init_FSCR
240686c1	53	bl __init_PMU
aec937b1 MN	54	bl __init_hvmode_206
	55	mtlr r11
	56	beqlr
	57	li r0,0
	58	mtspr SPRN_LPID,r0
f7c32c24	59	mfspr r3,SPRN_LPCR
d4e58e59	60	ori r3, r3, LPCR_PECEDH
aec937b1	61	bl __init_LPCR
2a3563b0	62	bl __init_HFSCR
04407050	63	bl __init_tlb_power8
240686c1	64	bl __init_PMU_HV
aec937b1 MN	65	mtlr r11
	66	blr
	67
	68	_GLOBAL(__restore_cpu_power8)
	69	mflr r11
57d23167	70	bl __init_FSCR
240686c1	71	bl __init_PMU
aec937b1 MN	72	mfmsr r3
aec937b1 MN	73	rldicl. r0,r3,4,63
8c2a3817	74	mtlr r11
aec937b1 MN	75	beqlr
	76	li r0,0
	77	mtspr SPRN_LPID,r0
f7c32c24	78	mfspr r3,SPRN_LPCR
d4e58e59	79	ori r3, r3, LPCR_PECEDH
aec937b1	80	bl __init_LPCR
2a3563b0	81	bl __init_HFSCR
04407050	82	bl __init_tlb_power8
240686c1	83	bl __init_PMU_HV
24cc67de BH	84	mtlr r11
	85	blr
	86
c3ab300e MN	87	_GLOBAL(__setup_cpu_power9)
	88	mflr r11
	89	bl __init_FSCR
	90	bl __init_hvmode_206
	91	mtlr r11
	92	beqlr
	93	li r0,0
	94	mtspr SPRN_LPID,r0
	95	mfspr r3,SPRN_LPCR
	96	ori r3, r3, LPCR_PECEDH
	97	bl __init_LPCR
	98	bl __init_HFSCR
	99	bl __init_tlb_power9
	100	mtlr r11
	101	blr
	102
	103	_GLOBAL(__restore_cpu_power9)
	104	mflr r11
	105	bl __init_FSCR
	106	mfmsr r3
	107	rldicl. r0,r3,4,63
	108	mtlr r11
	109	beqlr
	110	li r0,0
	111	mtspr SPRN_LPID,r0
	112	mfspr r3,SPRN_LPCR
	113	ori r3, r3, LPCR_PECEDH
	114	bl __init_LPCR
	115	bl __init_HFSCR
	116	bl __init_tlb_power9
	117	mtlr r11
	118	blr
	119
24cc67de	120	__init_hvmode_206:
969391c5	121	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
24cc67de BH	122	mfmsr r3
	123	rldicl. r0,r3,4,63
	124	bnelr
	125	ld r5,CPU_SPEC_FEATURES(r4)
969391c5	126	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
24cc67de BH	127	xor r5,r5,r6
	128	std r5,CPU_SPEC_FEATURES(r4)
	129	blr
	130
	131	__init_LPCR:
	132	/* Setup a sane LPCR:
f7c32c24	133	* Called with initial LPCR in R3
24cc67de	134	*
a5d4f3ad	135	* LPES = 0b01 (HSRR0/1 used for 0x500)
24cc67de	136	* PECE = 0b111
895796a8	137	* DPFD = 4
923c53ca PM	138	* HDICE = 0
	139	* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	140	* VRMASD = 0b10000 (L=1, LP=00)
24cc67de BH	141	*
	142	* Other bits untouched for now
	143	*/
923c53ca PM	144	li r5,1
923c53ca PM	145	rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
24cc67de	146	ori r3,r3,(LPCR_PECE0\|LPCR_PECE1\|LPCR_PECE2)
895796a8	147	li r5,4
923c53ca PM	148	rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	149	clrrdi r3,r3,1 /* clear HDICE */
	150	li r5,4
	151	rldimi r3,r5, LPCR_VC_SH, 0
	152	li r5,0x10
	153	rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
24cc67de BH	154	mtspr SPRN_LPCR,r3
	155	isync
	156	blr
b144871c	157
2468dcf6 IM	158	__init_FSCR:
2468dcf6 IM	159	mfspr r3,SPRN_FSCR
1ddf499e	160	ori r3,r3,FSCR_TAR\|FSCR_DSCR\|FSCR_EBB
2468dcf6 IM	161	mtspr SPRN_FSCR,r3
	162	blr
	163
2a3563b0 MN	164	__init_HFSCR:
2a3563b0 MN	165	mfspr r3,SPRN_HFSCR
53b56ca0	166	ori r3,r3,HFSCR_TAR\|HFSCR_TM\|HFSCR_BHRB\|HFSCR_PM\|\
1ddf499e	167	HFSCR_DSCR\|HFSCR_VECVSX\|HFSCR_FP\|HFSCR_EBB
2a3563b0 MN	168	mtspr SPRN_HFSCR,r3
	169	blr
	170
04407050 MS	171	/*
	172	* Clear the TLB using the specified IS form of tlbiel instruction
	173	* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
04407050 MS	174	*/
04407050 MS	175	__init_tlb_power7:
15b1624b	176	li r6,POWER7_TLB_SETS
04407050	177	mtctr r6
45706bb5	178	li r7,0xc00 /* IS field = 0b11 */
04407050 MS	179	ptesync
	180	2: tlbiel r7
	181	addi r7,r7,0x1000
	182	bdnz 2b
	183	ptesync
	184	1: blr
	185
	186	__init_tlb_power8:
15b1624b	187	li r6,POWER8_TLB_SETS
b144871c	188	mtctr r6
45706bb5	189	li r7,0xc00 /* IS field = 0b11 */
b144871c BH	190	ptesync
	191	2: tlbiel r7
	192	addi r7,r7,0x1000
	193	bdnz 2b
	194	ptesync
	195	1: blr
240686c1	196
c3ab300e MN	197	__init_tlb_power9:
	198	li r6,POWER9_TLB_SETS_HASH
	199	mtctr r6
	200	li r7,0xc00 /* IS field = 0b11 */
	201	ptesync
	202	2: tlbiel r7
	203	addi r7,r7,0x1000
	204	bdnz 2b
	205	ptesync
	206	1: blr
	207
240686c1 ME	208	__init_PMU_HV:
	209	li r5,0
	210	mtspr SPRN_MMCRC,r5
	211	mtspr SPRN_MMCRH,r5
	212	blr
	213
	214	__init_PMU:
	215	li r5,0
	216	mtspr SPRN_MMCRS,r5
	217	mtspr SPRN_MMCRA,r5
	218	mtspr SPRN_MMCR0,r5
	219	mtspr SPRN_MMCR1,r5
	220	mtspr SPRN_MMCR2,r5
	221	blr