Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
cb3bc9d0 | 25 | #include <linux/sched.h> |
1da177e4 LT |
26 | #include <linux/init.h> |
27 | #include <linux/list.h> | |
1da177e4 LT |
28 | #include <linux/pci.h> |
29 | #include <linux/proc_fs.h> | |
30 | #include <linux/rbtree.h> | |
31 | #include <linux/seq_file.h> | |
32 | #include <linux/spinlock.h> | |
66b15db6 | 33 | #include <linux/export.h> |
acaa6176 SR |
34 | #include <linux/of.h> |
35 | ||
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <asm/eeh.h> |
172ca926 | 38 | #include <asm/eeh_event.h> |
1da177e4 LT |
39 | #include <asm/io.h> |
40 | #include <asm/machdep.h> | |
172ca926 | 41 | #include <asm/ppc-pci.h> |
1da177e4 | 42 | #include <asm/rtas.h> |
1da177e4 | 43 | |
1da177e4 LT |
44 | |
45 | /** Overview: | |
46 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
47 | * dealing with PCI bus errors that can't be dealt with within the | |
48 | * usual PCI framework, except by check-stopping the CPU. Systems | |
49 | * that are designed for high-availability/reliability cannot afford | |
50 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
51 | * An EEH-capable bridge operates by converting a detected error | |
52 | * into a "slot freeze", taking the PCI adapter off-line, making | |
53 | * the slot behave, from the OS'es point of view, as if the slot | |
54 | * were "empty": all reads return 0xff's and all writes are silently | |
55 | * ignored. EEH slot isolation events can be triggered by parity | |
56 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
57 | * which in turn might be caused by low voltage on the bus, dust, |
58 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
59 | * |
60 | * Note, however, that one of the leading causes of EEH slot | |
61 | * freeze events are buggy device drivers, buggy device microcode, | |
62 | * or buggy device hardware. This is because any attempt by the | |
63 | * device to bus-master data to a memory address that is not | |
64 | * assigned to the device will trigger a slot freeze. (The idea | |
65 | * is to prevent devices-gone-wild from corrupting system memory). | |
66 | * Buggy hardware/drivers will have a miserable time co-existing | |
67 | * with EEH. | |
68 | * | |
69 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 70 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
71 | * whether this is the case, and then take appropriate steps to |
72 | * reset the PCI slot, the PCI device, and then resume operations. | |
73 | * However, until that day, the checking is done here, with the | |
74 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
75 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
76 | * and sent out for processing. | |
77 | */ | |
78 | ||
5c1344e9 | 79 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
80 | * handler after a slot isolation event, it might be broken. |
81 | * This sets the threshold for how many read attempts we allow | |
82 | * before printing an error message. | |
1da177e4 | 83 | */ |
2fd30be8 | 84 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 85 | |
17213c3b | 86 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
87 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
88 | ||
aa1e6374 GS |
89 | /* Platform dependent EEH operations */ |
90 | struct eeh_ops *eeh_ops = NULL; | |
91 | ||
1e28a7dd DW |
92 | int eeh_subsystem_enabled; |
93 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 94 | |
d7bb8862 GS |
95 | /* |
96 | * EEH probe mode support. The intention is to support multiple | |
97 | * platforms for EEH. Some platforms like pSeries do PCI emunation | |
98 | * based on device tree. However, other platforms like powernv probe | |
99 | * PCI devices from hardware. The flag is used to distinguish that. | |
100 | * In addition, struct eeh_ops::probe would be invoked for particular | |
101 | * OF node or PCI device so that the corresponding PE would be created | |
102 | * there. | |
103 | */ | |
104 | int eeh_probe_mode; | |
105 | ||
fd761fd8 | 106 | /* Lock to avoid races due to multiple reports of an error */ |
4907581d | 107 | DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 108 | |
17213c3b LV |
109 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
110 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
111 | * can access it. | |
112 | */ | |
d99bb1db LV |
113 | #define EEH_PCI_REGS_LOG_LEN 4096 |
114 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
115 | ||
e575f8db GS |
116 | /* |
117 | * The struct is used to maintain the EEH global statistic | |
118 | * information. Besides, the EEH global statistics will be | |
119 | * exported to user space through procfs | |
120 | */ | |
121 | struct eeh_stats { | |
122 | u64 no_device; /* PCI device not found */ | |
123 | u64 no_dn; /* OF node not found */ | |
124 | u64 no_cfg_addr; /* Config address not found */ | |
125 | u64 ignored_check; /* EEH check skipped */ | |
126 | u64 total_mmio_ffs; /* Total EEH checks */ | |
127 | u64 false_positives; /* Unnecessary EEH checks */ | |
128 | u64 slot_resets; /* PE reset */ | |
129 | }; | |
130 | ||
131 | static struct eeh_stats eeh_stats; | |
1da177e4 | 132 | |
7684b40c LV |
133 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
134 | ||
d99bb1db | 135 | /** |
cce4b2d2 | 136 | * eeh_gather_pci_data - Copy assorted PCI config space registers to buff |
f631acd3 | 137 | * @edev: device to report data for |
d99bb1db LV |
138 | * @buf: point to buffer in which to log |
139 | * @len: amount of room in buffer | |
140 | * | |
141 | * This routine captures assorted PCI configuration space data, | |
142 | * and puts them into a buffer for RTAS error logging. | |
143 | */ | |
f631acd3 | 144 | static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) |
d99bb1db | 145 | { |
f631acd3 GS |
146 | struct device_node *dn = eeh_dev_to_of_node(edev); |
147 | struct pci_dev *dev = eeh_dev_to_pci_dev(edev); | |
d99bb1db | 148 | u32 cfg; |
fcf9892b | 149 | int cap, i; |
d99bb1db LV |
150 | int n = 0; |
151 | ||
f631acd3 GS |
152 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
153 | printk(KERN_WARNING "EEH: of node=%s\n", dn->full_name); | |
fcf9892b | 154 | |
3780444c | 155 | eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
156 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
157 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
158 | ||
3780444c | 159 | eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg); |
d99bb1db | 160 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
fcf9892b LV |
161 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
162 | ||
b37ceefe LV |
163 | if (!dev) { |
164 | printk(KERN_WARNING "EEH: no PCI device for this of node\n"); | |
165 | return n; | |
166 | } | |
167 | ||
0b9369f4 LV |
168 | /* Gather bridge-specific registers */ |
169 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
3780444c | 170 | eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 LV |
171 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
172 | printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg); | |
173 | ||
3780444c | 174 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 LV |
175 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
176 | printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg); | |
177 | } | |
178 | ||
fcf9892b | 179 | /* Dump out the PCI-X command and status regs */ |
b37ceefe | 180 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
fcf9892b | 181 | if (cap) { |
3780444c | 182 | eeh_ops->read_config(dn, cap, 4, &cfg); |
fcf9892b LV |
183 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
184 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
185 | ||
3780444c | 186 | eeh_ops->read_config(dn, cap+4, 4, &cfg); |
fcf9892b LV |
187 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
188 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
189 | } | |
190 | ||
191 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
b37ceefe | 192 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
fcf9892b LV |
193 | if (cap) { |
194 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
195 | printk(KERN_WARNING | |
196 | "EEH: PCI-E capabilities and status follow:\n"); | |
197 | ||
198 | for (i=0; i<=8; i++) { | |
3780444c | 199 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b LV |
200 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
201 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
202 | } | |
203 | ||
b37ceefe | 204 | cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
fcf9892b LV |
205 | if (cap) { |
206 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
207 | printk(KERN_WARNING | |
208 | "EEH: PCI-E AER capability register set follows:\n"); | |
209 | ||
210 | for (i=0; i<14; i++) { | |
3780444c | 211 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b LV |
212 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
213 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
214 | } | |
215 | } | |
216 | } | |
0b9369f4 | 217 | |
d99bb1db LV |
218 | return n; |
219 | } | |
220 | ||
cb3bc9d0 GS |
221 | /** |
222 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
ff477966 | 223 | * @pe: EEH PE |
cb3bc9d0 GS |
224 | * @severity: temporary or permanent error log |
225 | * | |
226 | * This routine should be called to generate the combined log, which | |
227 | * is comprised of driver log and error log. The driver log is figured | |
228 | * out from the config space of the corresponding PCI device, while | |
229 | * the error log is fetched through platform dependent function call. | |
230 | */ | |
ff477966 | 231 | void eeh_slot_error_detail(struct eeh_pe *pe, int severity) |
d99bb1db LV |
232 | { |
233 | size_t loglen = 0; | |
9feed42e | 234 | struct eeh_dev *edev, *tmp; |
c35ae179 | 235 | bool valid_cfg_log = true; |
d99bb1db | 236 | |
c35ae179 GS |
237 | /* |
238 | * When the PHB is fenced or dead, it's pointless to collect | |
239 | * the data from PCI config space because it should return | |
240 | * 0xFF's. For ER, we still retrieve the data from the PCI | |
241 | * config space. | |
242 | */ | |
243 | if (eeh_probe_mode_dev() && | |
244 | (pe->type & EEH_PE_PHB) && | |
245 | (pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD))) | |
246 | valid_cfg_log = false; | |
247 | ||
248 | if (valid_cfg_log) { | |
249 | eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); | |
250 | eeh_ops->configure_bridge(pe); | |
251 | eeh_pe_restore_bars(pe); | |
252 | ||
253 | pci_regs_buf[0] = 0; | |
9feed42e | 254 | eeh_pe_for_each_dev(pe, edev, tmp) { |
c35ae179 GS |
255 | loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen, |
256 | EEH_PCI_REGS_LOG_LEN - loglen); | |
257 | } | |
258 | } | |
ff477966 GS |
259 | |
260 | eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); | |
d99bb1db LV |
261 | } |
262 | ||
1da177e4 | 263 | /** |
cb3bc9d0 GS |
264 | * eeh_token_to_phys - Convert EEH address token to phys address |
265 | * @token: I/O token, should be address in the form 0xA.... | |
266 | * | |
267 | * This routine should be called to convert virtual I/O address | |
268 | * to physical one. | |
1da177e4 LT |
269 | */ |
270 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
271 | { | |
272 | pte_t *ptep; | |
273 | unsigned long pa; | |
12bc9f6f | 274 | int hugepage_shift; |
1da177e4 | 275 | |
12bc9f6f AK |
276 | /* |
277 | * We won't find hugepages here, iomem | |
278 | */ | |
279 | ptep = find_linux_pte_or_hugepte(init_mm.pgd, token, &hugepage_shift); | |
1da177e4 LT |
280 | if (!ptep) |
281 | return token; | |
12bc9f6f | 282 | WARN_ON(hugepage_shift); |
1da177e4 LT |
283 | pa = pte_pfn(*ptep) << PAGE_SHIFT; |
284 | ||
285 | return pa | (token & (PAGE_SIZE-1)); | |
286 | } | |
287 | ||
b95cd2cd GS |
288 | /* |
289 | * On PowerNV platform, we might already have fenced PHB there. | |
290 | * For that case, it's meaningless to recover frozen PE. Intead, | |
291 | * We have to handle fenced PHB firstly. | |
292 | */ | |
293 | static int eeh_phb_check_failure(struct eeh_pe *pe) | |
294 | { | |
295 | struct eeh_pe *phb_pe; | |
296 | unsigned long flags; | |
297 | int ret; | |
298 | ||
299 | if (!eeh_probe_mode_dev()) | |
300 | return -EPERM; | |
301 | ||
302 | /* Find the PHB PE */ | |
303 | phb_pe = eeh_phb_pe_get(pe->phb); | |
304 | if (!phb_pe) { | |
305 | pr_warning("%s Can't find PE for PHB#%d\n", | |
306 | __func__, pe->phb->global_number); | |
307 | return -EEXIST; | |
308 | } | |
309 | ||
310 | /* If the PHB has been in problematic state */ | |
311 | eeh_serialize_lock(&flags); | |
312 | if (phb_pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)) { | |
313 | ret = 0; | |
314 | goto out; | |
315 | } | |
316 | ||
317 | /* Check PHB state */ | |
318 | ret = eeh_ops->get_state(phb_pe, NULL); | |
319 | if ((ret < 0) || | |
320 | (ret == EEH_STATE_NOT_SUPPORT) || | |
321 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
322 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
323 | ret = 0; | |
324 | goto out; | |
325 | } | |
326 | ||
327 | /* Isolate the PHB and send event */ | |
328 | eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED); | |
329 | eeh_serialize_unlock(flags); | |
b95cd2cd | 330 | |
56ca4fde GS |
331 | pr_err("EEH: PHB#%x failure detected\n", |
332 | phb_pe->phb->global_number); | |
333 | dump_stack(); | |
5293bf97 | 334 | eeh_send_failure_event(phb_pe); |
b95cd2cd GS |
335 | |
336 | return 1; | |
337 | out: | |
338 | eeh_serialize_unlock(flags); | |
339 | return ret; | |
340 | } | |
341 | ||
1da177e4 | 342 | /** |
f8f7d63f GS |
343 | * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze |
344 | * @edev: eeh device | |
1da177e4 LT |
345 | * |
346 | * Check for an EEH failure for the given device node. Call this | |
347 | * routine if the result of a read was all 0xff's and you want to | |
348 | * find out if this is due to an EEH slot freeze. This routine | |
349 | * will query firmware for the EEH status. | |
350 | * | |
351 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 352 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
353 | * |
354 | * It is safe to call this routine in an interrupt context. | |
355 | */ | |
f8f7d63f | 356 | int eeh_dev_check_failure(struct eeh_dev *edev) |
1da177e4 LT |
357 | { |
358 | int ret; | |
1da177e4 | 359 | unsigned long flags; |
f8f7d63f GS |
360 | struct device_node *dn; |
361 | struct pci_dev *dev; | |
66523d9f | 362 | struct eeh_pe *pe; |
fd761fd8 | 363 | int rc = 0; |
f36c5227 | 364 | const char *location; |
1da177e4 | 365 | |
e575f8db | 366 | eeh_stats.total_mmio_ffs++; |
1da177e4 LT |
367 | |
368 | if (!eeh_subsystem_enabled) | |
369 | return 0; | |
370 | ||
f8f7d63f | 371 | if (!edev) { |
e575f8db | 372 | eeh_stats.no_dn++; |
1da177e4 | 373 | return 0; |
177bc936 | 374 | } |
f8f7d63f GS |
375 | dn = eeh_dev_to_of_node(edev); |
376 | dev = eeh_dev_to_pci_dev(edev); | |
66523d9f | 377 | pe = edev->pe; |
1da177e4 LT |
378 | |
379 | /* Access to IO BARs might get this far and still not want checking. */ | |
66523d9f | 380 | if (!pe) { |
e575f8db | 381 | eeh_stats.ignored_check++; |
66523d9f GS |
382 | pr_debug("EEH: Ignored check for %s %s\n", |
383 | eeh_pci_name(dev), dn->full_name); | |
1da177e4 LT |
384 | return 0; |
385 | } | |
386 | ||
66523d9f | 387 | if (!pe->addr && !pe->config_addr) { |
e575f8db | 388 | eeh_stats.no_cfg_addr++; |
1da177e4 LT |
389 | return 0; |
390 | } | |
391 | ||
b95cd2cd GS |
392 | /* |
393 | * On PowerNV platform, we might already have fenced PHB | |
394 | * there and we need take care of that firstly. | |
395 | */ | |
396 | ret = eeh_phb_check_failure(pe); | |
397 | if (ret > 0) | |
398 | return ret; | |
399 | ||
fd761fd8 LV |
400 | /* If we already have a pending isolation event for this |
401 | * slot, we know it's bad already, we don't need to check. | |
402 | * Do this checking under a lock; as multiple PCI devices | |
403 | * in one slot might report errors simultaneously, and we | |
404 | * only want one error recovery routine running. | |
1da177e4 | 405 | */ |
4907581d | 406 | eeh_serialize_lock(&flags); |
fd761fd8 | 407 | rc = 1; |
66523d9f GS |
408 | if (pe->state & EEH_PE_ISOLATED) { |
409 | pe->check_count++; | |
410 | if (pe->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 411 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 412 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 413 | "location=%s driver=%s pci addr=%s\n", |
66523d9f | 414 | pe->check_count, location, |
778a785f | 415 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 416 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 417 | eeh_driver_name(dev)); |
5c1344e9 | 418 | dump_stack(); |
1da177e4 | 419 | } |
fd761fd8 | 420 | goto dn_unlock; |
1da177e4 LT |
421 | } |
422 | ||
423 | /* | |
424 | * Now test for an EEH failure. This is VERY expensive. | |
425 | * Note that the eeh_config_addr may be a parent device | |
426 | * in the case of a device behind a bridge, or it may be | |
427 | * function zero of a multi-function device. | |
428 | * In any case they must share a common PHB. | |
429 | */ | |
66523d9f | 430 | ret = eeh_ops->get_state(pe, NULL); |
76e6faf7 | 431 | |
39d16e29 | 432 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 433 | * they are empty when they don't have children. |
eb594a47 GS |
434 | * We will punt with the following conditions: Failure to get |
435 | * PE's state, EEH not support and Permanently unavailable | |
436 | * state, PE is in good state. | |
cb3bc9d0 | 437 | */ |
eb594a47 GS |
438 | if ((ret < 0) || |
439 | (ret == EEH_STATE_NOT_SUPPORT) || | |
440 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
441 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
e575f8db | 442 | eeh_stats.false_positives++; |
66523d9f | 443 | pe->false_positives++; |
fd761fd8 LV |
444 | rc = 0; |
445 | goto dn_unlock; | |
76e6faf7 LV |
446 | } |
447 | ||
e575f8db | 448 | eeh_stats.slot_resets++; |
a84f273c | 449 | |
fd761fd8 LV |
450 | /* Avoid repeated reports of this failure, including problems |
451 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
452 | * bridges. |
453 | */ | |
66523d9f | 454 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); |
4907581d | 455 | eeh_serialize_unlock(flags); |
1da177e4 | 456 | |
1da177e4 LT |
457 | /* Most EEH events are due to device driver bugs. Having |
458 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
459 | * out what happened. So print that out. |
460 | */ | |
56ca4fde GS |
461 | pr_err("EEH: Frozen PE#%x detected on PHB#%x\n", |
462 | pe->addr, pe->phb->global_number); | |
463 | dump_stack(); | |
464 | ||
5293bf97 GS |
465 | eeh_send_failure_event(pe); |
466 | ||
fd761fd8 LV |
467 | return 1; |
468 | ||
469 | dn_unlock: | |
4907581d | 470 | eeh_serialize_unlock(flags); |
fd761fd8 | 471 | return rc; |
1da177e4 LT |
472 | } |
473 | ||
f8f7d63f | 474 | EXPORT_SYMBOL_GPL(eeh_dev_check_failure); |
1da177e4 LT |
475 | |
476 | /** | |
cb3bc9d0 GS |
477 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
478 | * @token: I/O token, should be address in the form 0xA.... | |
479 | * @val: value, should be all 1's (XXX why do we need this arg??) | |
1da177e4 | 480 | * |
1da177e4 LT |
481 | * Check for an EEH failure at the given token address. Call this |
482 | * routine if the result of a read was all 0xff's and you want to | |
483 | * find out if this is due to an EEH slot freeze event. This routine | |
484 | * will query firmware for the EEH status. | |
485 | * | |
486 | * Note this routine is safe to call in an interrupt context. | |
487 | */ | |
488 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
489 | { | |
490 | unsigned long addr; | |
f8f7d63f | 491 | struct eeh_dev *edev; |
1da177e4 LT |
492 | |
493 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
494 | addr = eeh_token_to_phys((unsigned long __force) token); | |
3ab96a02 | 495 | edev = eeh_addr_cache_get_dev(addr); |
f8f7d63f | 496 | if (!edev) { |
e575f8db | 497 | eeh_stats.no_device++; |
1da177e4 | 498 | return val; |
177bc936 | 499 | } |
1da177e4 | 500 | |
f8f7d63f | 501 | eeh_dev_check_failure(edev); |
1da177e4 LT |
502 | return val; |
503 | } | |
504 | ||
505 | EXPORT_SYMBOL(eeh_check_failure); | |
506 | ||
6dee3fb9 | 507 | |
47b5c838 | 508 | /** |
cce4b2d2 | 509 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
ff477966 | 510 | * @pe: EEH PE |
cb3bc9d0 GS |
511 | * |
512 | * This routine should be called to reenable frozen MMIO or DMA | |
513 | * so that it would work correctly again. It's useful while doing | |
514 | * recovery or log collection on the indicated device. | |
47b5c838 | 515 | */ |
ff477966 | 516 | int eeh_pci_enable(struct eeh_pe *pe, int function) |
47b5c838 | 517 | { |
47b5c838 LV |
518 | int rc; |
519 | ||
ff477966 | 520 | rc = eeh_ops->set_option(pe, function); |
47b5c838 | 521 | if (rc) |
ff477966 GS |
522 | pr_warning("%s: Unexpected state change %d on PHB#%d-PE#%x, err=%d\n", |
523 | __func__, function, pe->phb->global_number, pe->addr, rc); | |
47b5c838 | 524 | |
ff477966 | 525 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
eb594a47 GS |
526 | if (rc > 0 && (rc & EEH_STATE_MMIO_ENABLED) && |
527 | (function == EEH_OPT_THAW_MMIO)) | |
fa1be476 LV |
528 | return 0; |
529 | ||
47b5c838 LV |
530 | return rc; |
531 | } | |
532 | ||
00c2ae35 BK |
533 | /** |
534 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
535 | * @dev: pci device struct |
536 | * @state: reset state to enter | |
00c2ae35 BK |
537 | * |
538 | * Return value: | |
539 | * 0 if success | |
cb3bc9d0 | 540 | */ |
00c2ae35 BK |
541 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
542 | { | |
c270a24c GS |
543 | struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); |
544 | struct eeh_pe *pe = edev->pe; | |
545 | ||
546 | if (!pe) { | |
547 | pr_err("%s: No PE found on PCI device %s\n", | |
548 | __func__, pci_name(dev)); | |
549 | return -EINVAL; | |
550 | } | |
00c2ae35 BK |
551 | |
552 | switch (state) { | |
553 | case pcie_deassert_reset: | |
c270a24c | 554 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
00c2ae35 BK |
555 | break; |
556 | case pcie_hot_reset: | |
c270a24c | 557 | eeh_ops->reset(pe, EEH_RESET_HOT); |
00c2ae35 BK |
558 | break; |
559 | case pcie_warm_reset: | |
c270a24c | 560 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
561 | break; |
562 | default: | |
563 | return -EINVAL; | |
564 | }; | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
cb5b5624 | 569 | /** |
c270a24c GS |
570 | * eeh_set_pe_freset - Check the required reset for the indicated device |
571 | * @data: EEH device | |
572 | * @flag: return value | |
cb3bc9d0 GS |
573 | * |
574 | * Each device might have its preferred reset type: fundamental or | |
575 | * hot reset. The routine is used to collected the information for | |
576 | * the indicated device and its children so that the bunch of the | |
577 | * devices could be reset properly. | |
578 | */ | |
c270a24c | 579 | static void *eeh_set_dev_freset(void *data, void *flag) |
cb3bc9d0 GS |
580 | { |
581 | struct pci_dev *dev; | |
c270a24c GS |
582 | unsigned int *freset = (unsigned int *)flag; |
583 | struct eeh_dev *edev = (struct eeh_dev *)data; | |
6dee3fb9 | 584 | |
c270a24c | 585 | dev = eeh_dev_to_pci_dev(edev); |
cb3bc9d0 GS |
586 | if (dev) |
587 | *freset |= dev->needs_freset; | |
588 | ||
c270a24c | 589 | return NULL; |
cb3bc9d0 GS |
590 | } |
591 | ||
592 | /** | |
cce4b2d2 | 593 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
c270a24c | 594 | * @pe: EEH PE |
cb3bc9d0 GS |
595 | * |
596 | * Assert the PCI #RST line for 1/4 second. | |
597 | */ | |
c270a24c | 598 | static void eeh_reset_pe_once(struct eeh_pe *pe) |
6dee3fb9 | 599 | { |
308fc4f8 | 600 | unsigned int freset = 0; |
6e19314c | 601 | |
308fc4f8 RL |
602 | /* Determine type of EEH reset required for |
603 | * Partitionable Endpoint, a hot-reset (1) | |
604 | * or a fundamental reset (3). | |
605 | * A fundamental reset required by any device under | |
606 | * Partitionable Endpoint trumps hot-reset. | |
a84f273c | 607 | */ |
c270a24c | 608 | eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); |
308fc4f8 RL |
609 | |
610 | if (freset) | |
c270a24c | 611 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
6e19314c | 612 | else |
c270a24c | 613 | eeh_ops->reset(pe, EEH_RESET_HOT); |
6dee3fb9 LV |
614 | |
615 | /* The PCI bus requires that the reset be held high for at least | |
cb3bc9d0 GS |
616 | * a 100 milliseconds. We wait a bit longer 'just in case'. |
617 | */ | |
6dee3fb9 | 618 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 |
cb3bc9d0 | 619 | msleep(PCI_BUS_RST_HOLD_TIME_MSEC); |
a84f273c GS |
620 | |
621 | /* We might get hit with another EEH freeze as soon as the | |
d9564ad1 | 622 | * pci slot reset line is dropped. Make sure we don't miss |
cb3bc9d0 GS |
623 | * these, and clear the flag now. |
624 | */ | |
dbbceee1 | 625 | eeh_pe_state_clear(pe, EEH_PE_ISOLATED); |
d9564ad1 | 626 | |
c270a24c | 627 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
6dee3fb9 LV |
628 | |
629 | /* After a PCI slot has been reset, the PCI Express spec requires | |
630 | * a 1.5 second idle time for the bus to stabilize, before starting | |
cb3bc9d0 GS |
631 | * up traffic. |
632 | */ | |
6dee3fb9 | 633 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 |
cb3bc9d0 | 634 | msleep(PCI_BUS_SETTLE_TIME_MSEC); |
e1029263 LV |
635 | } |
636 | ||
cb3bc9d0 | 637 | /** |
cce4b2d2 | 638 | * eeh_reset_pe - Reset the indicated PE |
c270a24c | 639 | * @pe: EEH PE |
cb3bc9d0 GS |
640 | * |
641 | * This routine should be called to reset indicated device, including | |
642 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
643 | * might be involved as well. | |
644 | */ | |
c270a24c | 645 | int eeh_reset_pe(struct eeh_pe *pe) |
e1029263 | 646 | { |
326a98ea | 647 | int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
e1029263 LV |
648 | int i, rc; |
649 | ||
9c547768 LV |
650 | /* Take three shots at resetting the bus */ |
651 | for (i=0; i<3; i++) { | |
c270a24c | 652 | eeh_reset_pe_once(pe); |
6dee3fb9 | 653 | |
c270a24c | 654 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
326a98ea | 655 | if ((rc & flags) == flags) |
b6495c0c | 656 | return 0; |
e1029263 | 657 | |
e1029263 | 658 | if (rc < 0) { |
c270a24c GS |
659 | pr_err("%s: Unrecoverable slot failure on PHB#%d-PE#%x", |
660 | __func__, pe->phb->global_number, pe->addr); | |
b6495c0c | 661 | return -1; |
e1029263 | 662 | } |
c270a24c GS |
663 | pr_err("EEH: bus reset %d failed on PHB#%d-PE#%x, rc=%d\n", |
664 | i+1, pe->phb->global_number, pe->addr, rc); | |
6dee3fb9 | 665 | } |
b6495c0c | 666 | |
9c547768 | 667 | return -1; |
6dee3fb9 LV |
668 | } |
669 | ||
8b553f32 | 670 | /** |
cb3bc9d0 | 671 | * eeh_save_bars - Save device bars |
f631acd3 | 672 | * @edev: PCI device associated EEH device |
8b553f32 LV |
673 | * |
674 | * Save the values of the device bars. Unlike the restore | |
675 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 676 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
677 | * an entire slot is reset at a time. |
678 | */ | |
d7bb8862 | 679 | void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
680 | { |
681 | int i; | |
f631acd3 | 682 | struct device_node *dn; |
8b553f32 | 683 | |
f631acd3 | 684 | if (!edev) |
8b553f32 | 685 | return; |
f631acd3 | 686 | dn = eeh_dev_to_of_node(edev); |
a84f273c | 687 | |
8b553f32 | 688 | for (i = 0; i < 16; i++) |
3780444c | 689 | eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]); |
8b553f32 LV |
690 | } |
691 | ||
aa1e6374 GS |
692 | /** |
693 | * eeh_ops_register - Register platform dependent EEH operations | |
694 | * @ops: platform dependent EEH operations | |
695 | * | |
696 | * Register the platform dependent EEH operation callback | |
697 | * functions. The platform should call this function before | |
698 | * any other EEH operations. | |
699 | */ | |
700 | int __init eeh_ops_register(struct eeh_ops *ops) | |
701 | { | |
702 | if (!ops->name) { | |
703 | pr_warning("%s: Invalid EEH ops name for %p\n", | |
704 | __func__, ops); | |
705 | return -EINVAL; | |
706 | } | |
707 | ||
708 | if (eeh_ops && eeh_ops != ops) { | |
709 | pr_warning("%s: EEH ops of platform %s already existing (%s)\n", | |
710 | __func__, eeh_ops->name, ops->name); | |
711 | return -EEXIST; | |
712 | } | |
713 | ||
714 | eeh_ops = ops; | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
719 | /** | |
720 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
721 | * @name: name of EEH platform operations | |
722 | * | |
723 | * Unregister the platform dependent EEH operation callback | |
724 | * functions. | |
725 | */ | |
726 | int __exit eeh_ops_unregister(const char *name) | |
727 | { | |
728 | if (!name || !strlen(name)) { | |
729 | pr_warning("%s: Invalid EEH ops name\n", | |
730 | __func__); | |
731 | return -EINVAL; | |
732 | } | |
733 | ||
734 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
735 | eeh_ops = NULL; | |
736 | return 0; | |
737 | } | |
738 | ||
739 | return -EEXIST; | |
740 | } | |
741 | ||
cb3bc9d0 GS |
742 | /** |
743 | * eeh_init - EEH initialization | |
744 | * | |
1da177e4 LT |
745 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
746 | * As a side effect we can determine here if eeh is supported at all. | |
747 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
748 | * check. If a user turns off EEH for a particular adapter they are really | |
749 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
750 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
751 | * EEH for all slots/all devices. | |
752 | * | |
753 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
754 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
755 | * newer systems can boot. | |
756 | */ | |
eeb6361f | 757 | int eeh_init(void) |
1da177e4 | 758 | { |
1a5c2e63 GS |
759 | struct pci_controller *hose, *tmp; |
760 | struct device_node *phb; | |
51fb5f56 GS |
761 | static int cnt = 0; |
762 | int ret = 0; | |
763 | ||
764 | /* | |
765 | * We have to delay the initialization on PowerNV after | |
766 | * the PCI hierarchy tree has been built because the PEs | |
767 | * are figured out based on PCI devices instead of device | |
768 | * tree nodes | |
769 | */ | |
770 | if (machine_is(powernv) && cnt++ <= 0) | |
771 | return ret; | |
e2af155c GS |
772 | |
773 | /* call platform initialization function */ | |
774 | if (!eeh_ops) { | |
775 | pr_warning("%s: Platform EEH operation not found\n", | |
776 | __func__); | |
35e5cfe2 | 777 | return -EEXIST; |
e2af155c GS |
778 | } else if ((ret = eeh_ops->init())) { |
779 | pr_warning("%s: Failed to call platform init function (%d)\n", | |
780 | __func__, ret); | |
35e5cfe2 | 781 | return ret; |
e2af155c | 782 | } |
1da177e4 | 783 | |
c8608558 GS |
784 | /* Initialize EEH event */ |
785 | ret = eeh_event_init(); | |
786 | if (ret) | |
787 | return ret; | |
788 | ||
1a5c2e63 | 789 | /* Enable EEH for all adapters */ |
d7bb8862 GS |
790 | if (eeh_probe_mode_devtree()) { |
791 | list_for_each_entry_safe(hose, tmp, | |
792 | &hose_list, list_node) { | |
793 | phb = hose->dn; | |
794 | traverse_pci_devices(phb, eeh_ops->of_probe, NULL); | |
795 | } | |
51fb5f56 GS |
796 | } else if (eeh_probe_mode_dev()) { |
797 | list_for_each_entry_safe(hose, tmp, | |
798 | &hose_list, list_node) | |
799 | pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL); | |
800 | } else { | |
801 | pr_warning("%s: Invalid probe mode %d\n", | |
802 | __func__, eeh_probe_mode); | |
803 | return -EINVAL; | |
1da177e4 LT |
804 | } |
805 | ||
21fd21f5 GS |
806 | /* |
807 | * Call platform post-initialization. Actually, It's good chance | |
808 | * to inform platform that EEH is ready to supply service if the | |
809 | * I/O cache stuff has been built up. | |
810 | */ | |
811 | if (eeh_ops->post_init) { | |
812 | ret = eeh_ops->post_init(); | |
813 | if (ret) | |
814 | return ret; | |
815 | } | |
816 | ||
1da177e4 | 817 | if (eeh_subsystem_enabled) |
d7bb8862 | 818 | pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n"); |
1da177e4 | 819 | else |
d7bb8862 | 820 | pr_warning("EEH: No capable adapters found\n"); |
35e5cfe2 GS |
821 | |
822 | return ret; | |
1da177e4 LT |
823 | } |
824 | ||
35e5cfe2 GS |
825 | core_initcall_sync(eeh_init); |
826 | ||
1da177e4 | 827 | /** |
cb3bc9d0 | 828 | * eeh_add_device_early - Enable EEH for the indicated device_node |
1da177e4 LT |
829 | * @dn: device node for which to set up EEH |
830 | * | |
831 | * This routine must be used to perform EEH initialization for PCI | |
832 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
833 | * This routine must be called before any i/o is performed to the | |
834 | * adapter (inluding any config-space i/o). | |
835 | * Whether this actually enables EEH or not for this device depends | |
836 | * on the CEC architecture, type of the device, on earlier boot | |
837 | * command-line arguments & etc. | |
838 | */ | |
f2856491 | 839 | void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
840 | { |
841 | struct pci_controller *phb; | |
1da177e4 | 842 | |
26a74850 GS |
843 | /* |
844 | * If we're doing EEH probe based on PCI device, we | |
845 | * would delay the probe until late stage because | |
846 | * the PCI device isn't available this moment. | |
847 | */ | |
848 | if (!eeh_probe_mode_devtree()) | |
849 | return; | |
850 | ||
1e38b714 | 851 | if (!of_node_to_eeh_dev(dn)) |
1da177e4 | 852 | return; |
f631acd3 | 853 | phb = of_node_to_eeh_dev(dn)->phb; |
f751f841 LV |
854 | |
855 | /* USB Bus children of PCI devices will not have BUID's */ | |
856 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 857 | return; |
1da177e4 | 858 | |
d7bb8862 | 859 | eeh_ops->of_probe(dn, NULL); |
1da177e4 | 860 | } |
1da177e4 | 861 | |
cb3bc9d0 GS |
862 | /** |
863 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
864 | * @dn: device node | |
865 | * | |
866 | * This routine must be used to perform EEH initialization for the | |
867 | * indicated PCI device that was added after system boot (e.g. | |
868 | * hotplug, dlpar). | |
869 | */ | |
e2a296ee LV |
870 | void eeh_add_device_tree_early(struct device_node *dn) |
871 | { | |
872 | struct device_node *sib; | |
acaa6176 SR |
873 | |
874 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
875 | eeh_add_device_tree_early(sib); |
876 | eeh_add_device_early(dn); | |
877 | } | |
878 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
879 | ||
1da177e4 | 880 | /** |
cb3bc9d0 | 881 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
882 | * @dev: pci device for which to set up EEH |
883 | * | |
884 | * This routine must be used to complete EEH initialization for PCI | |
885 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
886 | */ | |
f2856491 | 887 | void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 888 | { |
56b0fca3 | 889 | struct device_node *dn; |
f631acd3 | 890 | struct eeh_dev *edev; |
56b0fca3 | 891 | |
1da177e4 LT |
892 | if (!dev || !eeh_subsystem_enabled) |
893 | return; | |
894 | ||
57b066ff | 895 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 896 | |
56b0fca3 | 897 | dn = pci_device_to_OF_node(dev); |
2ef822c5 | 898 | edev = of_node_to_eeh_dev(dn); |
f631acd3 | 899 | if (edev->pdev == dev) { |
57b066ff BH |
900 | pr_debug("EEH: Already referenced !\n"); |
901 | return; | |
902 | } | |
f5c57710 GS |
903 | |
904 | /* | |
905 | * The EEH cache might not be removed correctly because of | |
906 | * unbalanced kref to the device during unplug time, which | |
907 | * relies on pcibios_release_device(). So we have to remove | |
908 | * that here explicitly. | |
909 | */ | |
910 | if (edev->pdev) { | |
911 | eeh_rmv_from_parent_pe(edev); | |
912 | eeh_addr_cache_rmv_dev(edev->pdev); | |
913 | eeh_sysfs_remove_device(edev->pdev); | |
ab55d218 | 914 | edev->mode &= ~EEH_DEV_SYSFS; |
f5c57710 GS |
915 | |
916 | edev->pdev = NULL; | |
917 | dev->dev.archdata.edev = NULL; | |
918 | } | |
57b066ff | 919 | |
f631acd3 GS |
920 | edev->pdev = dev; |
921 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 922 | |
26a74850 GS |
923 | /* |
924 | * We have to do the EEH probe here because the PCI device | |
925 | * hasn't been created yet in the early stage. | |
926 | */ | |
927 | if (eeh_probe_mode_dev()) | |
928 | eeh_ops->dev_probe(dev, NULL); | |
929 | ||
3ab96a02 | 930 | eeh_addr_cache_insert_dev(dev); |
1da177e4 | 931 | } |
794e085e | 932 | |
cb3bc9d0 GS |
933 | /** |
934 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
935 | * @bus: PCI bus | |
936 | * | |
937 | * This routine must be used to perform EEH initialization for PCI | |
938 | * devices which are attached to the indicated PCI bus. The PCI bus | |
939 | * is added after system boot through hotplug or dlpar. | |
940 | */ | |
794e085e NF |
941 | void eeh_add_device_tree_late(struct pci_bus *bus) |
942 | { | |
943 | struct pci_dev *dev; | |
944 | ||
945 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
a84f273c GS |
946 | eeh_add_device_late(dev); |
947 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
948 | struct pci_bus *subbus = dev->subordinate; | |
949 | if (subbus) | |
950 | eeh_add_device_tree_late(subbus); | |
951 | } | |
794e085e NF |
952 | } |
953 | } | |
954 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 | 955 | |
6a040ce7 TLSC |
956 | /** |
957 | * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus | |
958 | * @bus: PCI bus | |
959 | * | |
960 | * This routine must be used to add EEH sysfs files for PCI | |
961 | * devices which are attached to the indicated PCI bus. The PCI bus | |
962 | * is added after system boot through hotplug or dlpar. | |
963 | */ | |
964 | void eeh_add_sysfs_files(struct pci_bus *bus) | |
965 | { | |
966 | struct pci_dev *dev; | |
967 | ||
968 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
969 | eeh_sysfs_add_device(dev); | |
970 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
971 | struct pci_bus *subbus = dev->subordinate; | |
972 | if (subbus) | |
973 | eeh_add_sysfs_files(subbus); | |
974 | } | |
975 | } | |
976 | } | |
977 | EXPORT_SYMBOL_GPL(eeh_add_sysfs_files); | |
978 | ||
1da177e4 | 979 | /** |
cb3bc9d0 | 980 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
981 | * @dev: pci device to be removed |
982 | * | |
794e085e NF |
983 | * This routine should be called when a device is removed from |
984 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
985 | * the PCI device from the EEH subsystem. I/O errors affecting | |
986 | * this device will no longer be detected after this call; thus, | |
987 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 988 | */ |
807a827d | 989 | void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 990 | { |
f631acd3 GS |
991 | struct eeh_dev *edev; |
992 | ||
1da177e4 LT |
993 | if (!dev || !eeh_subsystem_enabled) |
994 | return; | |
f631acd3 | 995 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
996 | |
997 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 998 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 999 | |
f5c57710 | 1000 | if (!edev || !edev->pdev || !edev->pe) { |
57b066ff BH |
1001 | pr_debug("EEH: Not referenced !\n"); |
1002 | return; | |
b055a9e1 | 1003 | } |
f5c57710 GS |
1004 | |
1005 | /* | |
1006 | * During the hotplug for EEH error recovery, we need the EEH | |
1007 | * device attached to the parent PE in order for BAR restore | |
1008 | * a bit later. So we keep it for BAR restore and remove it | |
1009 | * from the parent PE during the BAR resotre. | |
1010 | */ | |
f631acd3 GS |
1011 | edev->pdev = NULL; |
1012 | dev->dev.archdata.edev = NULL; | |
f5c57710 GS |
1013 | if (!(edev->pe->state & EEH_PE_KEEP)) |
1014 | eeh_rmv_from_parent_pe(edev); | |
1015 | else | |
1016 | edev->mode |= EEH_DEV_DISCONNECTED; | |
57b066ff | 1017 | |
3ab96a02 | 1018 | eeh_addr_cache_rmv_dev(dev); |
57b066ff | 1019 | eeh_sysfs_remove_device(dev); |
ab55d218 | 1020 | edev->mode &= ~EEH_DEV_SYSFS; |
1da177e4 | 1021 | } |
1da177e4 LT |
1022 | |
1023 | static int proc_eeh_show(struct seq_file *m, void *v) | |
1024 | { | |
1da177e4 LT |
1025 | if (0 == eeh_subsystem_enabled) { |
1026 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
e575f8db | 1027 | seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); |
1da177e4 LT |
1028 | } else { |
1029 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 | 1030 | seq_printf(m, |
e575f8db GS |
1031 | "no device=%llu\n" |
1032 | "no device node=%llu\n" | |
1033 | "no config address=%llu\n" | |
1034 | "check not wanted=%llu\n" | |
1035 | "eeh_total_mmio_ffs=%llu\n" | |
1036 | "eeh_false_positives=%llu\n" | |
1037 | "eeh_slot_resets=%llu\n", | |
1038 | eeh_stats.no_device, | |
1039 | eeh_stats.no_dn, | |
1040 | eeh_stats.no_cfg_addr, | |
1041 | eeh_stats.ignored_check, | |
1042 | eeh_stats.total_mmio_ffs, | |
1043 | eeh_stats.false_positives, | |
1044 | eeh_stats.slot_resets); | |
1da177e4 LT |
1045 | } |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1051 | { | |
1052 | return single_open(file, proc_eeh_show, NULL); | |
1053 | } | |
1054 | ||
5dfe4c96 | 1055 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1056 | .open = proc_eeh_open, |
1057 | .read = seq_read, | |
1058 | .llseek = seq_lseek, | |
1059 | .release = single_release, | |
1060 | }; | |
1061 | ||
1062 | static int __init eeh_init_proc(void) | |
1063 | { | |
144136dd | 1064 | if (machine_is(pseries) || machine_is(powernv)) |
8feaa434 | 1065 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
1da177e4 LT |
1066 | return 0; |
1067 | } | |
1068 | __initcall(eeh_init_proc); |