Commit | Line | Data |
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55037d17 GS |
1 | /* |
2 | * The file intends to implement PE based on the information from | |
3 | * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device. | |
4 | * All the PEs should be organized as hierarchy tree. The first level | |
5 | * of the tree will be associated to existing PHBs since the particular | |
6 | * PE is only meaningful in one PHB domain. | |
7 | * | |
8 | * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
652defed | 25 | #include <linux/delay.h> |
55037d17 GS |
26 | #include <linux/export.h> |
27 | #include <linux/gfp.h> | |
55037d17 GS |
28 | #include <linux/kernel.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/string.h> | |
31 | ||
32 | #include <asm/pci-bridge.h> | |
33 | #include <asm/ppc-pci.h> | |
34 | ||
bb593c00 | 35 | static int eeh_pe_aux_size = 0; |
55037d17 GS |
36 | static LIST_HEAD(eeh_phb_pe); |
37 | ||
bb593c00 GS |
38 | /** |
39 | * eeh_set_pe_aux_size - Set PE auxillary data size | |
40 | * @size: PE auxillary data size | |
41 | * | |
42 | * Set PE auxillary data size | |
43 | */ | |
44 | void eeh_set_pe_aux_size(int size) | |
45 | { | |
46 | if (size < 0) | |
47 | return; | |
48 | ||
49 | eeh_pe_aux_size = size; | |
50 | } | |
51 | ||
55037d17 GS |
52 | /** |
53 | * eeh_pe_alloc - Allocate PE | |
54 | * @phb: PCI controller | |
55 | * @type: PE type | |
56 | * | |
57 | * Allocate PE instance dynamically. | |
58 | */ | |
59 | static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type) | |
60 | { | |
61 | struct eeh_pe *pe; | |
bb593c00 GS |
62 | size_t alloc_size; |
63 | ||
64 | alloc_size = sizeof(struct eeh_pe); | |
65 | if (eeh_pe_aux_size) { | |
66 | alloc_size = ALIGN(alloc_size, cache_line_size()); | |
67 | alloc_size += eeh_pe_aux_size; | |
68 | } | |
55037d17 GS |
69 | |
70 | /* Allocate PHB PE */ | |
bb593c00 | 71 | pe = kzalloc(alloc_size, GFP_KERNEL); |
55037d17 GS |
72 | if (!pe) return NULL; |
73 | ||
74 | /* Initialize PHB PE */ | |
75 | pe->type = type; | |
76 | pe->phb = phb; | |
77 | INIT_LIST_HEAD(&pe->child_list); | |
78 | INIT_LIST_HEAD(&pe->child); | |
79 | INIT_LIST_HEAD(&pe->edevs); | |
80 | ||
bb593c00 GS |
81 | pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe), |
82 | cache_line_size()); | |
55037d17 GS |
83 | return pe; |
84 | } | |
85 | ||
86 | /** | |
87 | * eeh_phb_pe_create - Create PHB PE | |
88 | * @phb: PCI controller | |
89 | * | |
90 | * The function should be called while the PHB is detected during | |
91 | * system boot or PCI hotplug in order to create PHB PE. | |
92 | */ | |
cad5cef6 | 93 | int eeh_phb_pe_create(struct pci_controller *phb) |
55037d17 GS |
94 | { |
95 | struct eeh_pe *pe; | |
96 | ||
97 | /* Allocate PHB PE */ | |
98 | pe = eeh_pe_alloc(phb, EEH_PE_PHB); | |
99 | if (!pe) { | |
100 | pr_err("%s: out of memory!\n", __func__); | |
101 | return -ENOMEM; | |
102 | } | |
103 | ||
104 | /* Put it into the list */ | |
55037d17 | 105 | list_add_tail(&pe->child, &eeh_phb_pe); |
55037d17 GS |
106 | |
107 | pr_debug("EEH: Add PE for PHB#%d\n", phb->global_number); | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
112 | /** | |
113 | * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB | |
114 | * @phb: PCI controller | |
115 | * | |
116 | * The overall PEs form hierarchy tree. The first layer of the | |
117 | * hierarchy tree is composed of PHB PEs. The function is used | |
118 | * to retrieve the corresponding PHB PE according to the given PHB. | |
119 | */ | |
9ff67433 | 120 | struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb) |
55037d17 GS |
121 | { |
122 | struct eeh_pe *pe; | |
123 | ||
55037d17 GS |
124 | list_for_each_entry(pe, &eeh_phb_pe, child) { |
125 | /* | |
126 | * Actually, we needn't check the type since | |
127 | * the PE for PHB has been determined when that | |
128 | * was created. | |
129 | */ | |
7844663a | 130 | if ((pe->type & EEH_PE_PHB) && pe->phb == phb) |
55037d17 | 131 | return pe; |
55037d17 GS |
132 | } |
133 | ||
55037d17 GS |
134 | return NULL; |
135 | } | |
22f4ab12 GS |
136 | |
137 | /** | |
138 | * eeh_pe_next - Retrieve the next PE in the tree | |
139 | * @pe: current PE | |
140 | * @root: root PE | |
141 | * | |
142 | * The function is used to retrieve the next PE in the | |
143 | * hierarchy PE tree. | |
144 | */ | |
145 | static struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, | |
146 | struct eeh_pe *root) | |
147 | { | |
148 | struct list_head *next = pe->child_list.next; | |
149 | ||
150 | if (next == &pe->child_list) { | |
151 | while (1) { | |
152 | if (pe == root) | |
153 | return NULL; | |
154 | next = pe->child.next; | |
155 | if (next != &pe->parent->child_list) | |
156 | break; | |
157 | pe = pe->parent; | |
158 | } | |
159 | } | |
160 | ||
161 | return list_entry(next, struct eeh_pe, child); | |
162 | } | |
163 | ||
164 | /** | |
165 | * eeh_pe_traverse - Traverse PEs in the specified PHB | |
166 | * @root: root PE | |
167 | * @fn: callback | |
168 | * @flag: extra parameter to callback | |
169 | * | |
170 | * The function is used to traverse the specified PE and its | |
171 | * child PEs. The traversing is to be terminated once the | |
172 | * callback returns something other than NULL, or no more PEs | |
173 | * to be traversed. | |
174 | */ | |
f5c57710 GS |
175 | void *eeh_pe_traverse(struct eeh_pe *root, |
176 | eeh_traverse_func fn, void *flag) | |
22f4ab12 GS |
177 | { |
178 | struct eeh_pe *pe; | |
179 | void *ret; | |
180 | ||
181 | for (pe = root; pe; pe = eeh_pe_next(pe, root)) { | |
182 | ret = fn(pe, flag); | |
183 | if (ret) return ret; | |
184 | } | |
185 | ||
186 | return NULL; | |
187 | } | |
188 | ||
9e6d2cf6 GS |
189 | /** |
190 | * eeh_pe_dev_traverse - Traverse the devices from the PE | |
191 | * @root: EEH PE | |
192 | * @fn: function callback | |
193 | * @flag: extra parameter to callback | |
194 | * | |
195 | * The function is used to traverse the devices of the specified | |
196 | * PE and its child PEs. | |
197 | */ | |
198 | void *eeh_pe_dev_traverse(struct eeh_pe *root, | |
199 | eeh_traverse_func fn, void *flag) | |
200 | { | |
201 | struct eeh_pe *pe; | |
9feed42e | 202 | struct eeh_dev *edev, *tmp; |
9e6d2cf6 GS |
203 | void *ret; |
204 | ||
205 | if (!root) { | |
0dae2743 GS |
206 | pr_warn("%s: Invalid PE %p\n", |
207 | __func__, root); | |
9e6d2cf6 GS |
208 | return NULL; |
209 | } | |
210 | ||
211 | /* Traverse root PE */ | |
212 | for (pe = root; pe; pe = eeh_pe_next(pe, root)) { | |
9feed42e | 213 | eeh_pe_for_each_dev(pe, edev, tmp) { |
9e6d2cf6 | 214 | ret = fn(edev, flag); |
ef6a2857 | 215 | if (ret) |
ea81245c | 216 | return ret; |
9e6d2cf6 GS |
217 | } |
218 | } | |
219 | ||
220 | return NULL; | |
221 | } | |
222 | ||
22f4ab12 GS |
223 | /** |
224 | * __eeh_pe_get - Check the PE address | |
225 | * @data: EEH PE | |
226 | * @flag: EEH device | |
227 | * | |
228 | * For one particular PE, it can be identified by PE address | |
229 | * or tranditional BDF address. BDF address is composed of | |
230 | * Bus/Device/Function number. The extra data referred by flag | |
231 | * indicates which type of address should be used. | |
232 | */ | |
233 | static void *__eeh_pe_get(void *data, void *flag) | |
234 | { | |
235 | struct eeh_pe *pe = (struct eeh_pe *)data; | |
236 | struct eeh_dev *edev = (struct eeh_dev *)flag; | |
237 | ||
238 | /* Unexpected PHB PE */ | |
5efc3ad7 | 239 | if (pe->type & EEH_PE_PHB) |
22f4ab12 GS |
240 | return NULL; |
241 | ||
2aa5cf9e GS |
242 | /* |
243 | * We prefer PE address. For most cases, we should | |
244 | * have non-zero PE address | |
245 | */ | |
246 | if (eeh_has_flag(EEH_VALID_PE_ZERO)) { | |
247 | if (edev->pe_config_addr == pe->addr) | |
248 | return pe; | |
249 | } else { | |
250 | if (edev->pe_config_addr && | |
251 | (edev->pe_config_addr == pe->addr)) | |
22f4ab12 | 252 | return pe; |
2aa5cf9e | 253 | } |
22f4ab12 GS |
254 | |
255 | /* Try BDF address */ | |
01566808 | 256 | if (edev->config_addr && |
22f4ab12 GS |
257 | (edev->config_addr == pe->config_addr)) |
258 | return pe; | |
259 | ||
260 | return NULL; | |
261 | } | |
262 | ||
263 | /** | |
264 | * eeh_pe_get - Search PE based on the given address | |
265 | * @edev: EEH device | |
266 | * | |
267 | * Search the corresponding PE based on the specified address which | |
268 | * is included in the eeh device. The function is used to check if | |
269 | * the associated PE has been created against the PE address. It's | |
270 | * notable that the PE address has 2 format: traditional PE address | |
271 | * which is composed of PCI bus/device/function number, or unified | |
272 | * PE address. | |
273 | */ | |
01566808 | 274 | struct eeh_pe *eeh_pe_get(struct eeh_dev *edev) |
22f4ab12 GS |
275 | { |
276 | struct eeh_pe *root = eeh_phb_pe_get(edev->phb); | |
277 | struct eeh_pe *pe; | |
278 | ||
22f4ab12 | 279 | pe = eeh_pe_traverse(root, __eeh_pe_get, edev); |
22f4ab12 GS |
280 | |
281 | return pe; | |
282 | } | |
283 | ||
284 | /** | |
285 | * eeh_pe_get_parent - Retrieve the parent PE | |
286 | * @edev: EEH device | |
287 | * | |
288 | * The whole PEs existing in the system are organized as hierarchy | |
289 | * tree. The function is used to retrieve the parent PE according | |
290 | * to the parent EEH device. | |
291 | */ | |
292 | static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev) | |
293 | { | |
294 | struct device_node *dn; | |
295 | struct eeh_dev *parent; | |
296 | ||
297 | /* | |
298 | * It might have the case for the indirect parent | |
299 | * EEH device already having associated PE, but | |
300 | * the direct parent EEH device doesn't have yet. | |
301 | */ | |
302 | dn = edev->dn->parent; | |
303 | while (dn) { | |
304 | /* We're poking out of PCI territory */ | |
305 | if (!PCI_DN(dn)) return NULL; | |
306 | ||
307 | parent = of_node_to_eeh_dev(dn); | |
308 | /* We're poking out of PCI territory */ | |
309 | if (!parent) return NULL; | |
310 | ||
311 | if (parent->pe) | |
312 | return parent->pe; | |
313 | ||
314 | dn = dn->parent; | |
315 | } | |
316 | ||
317 | return NULL; | |
318 | } | |
9b84348c GS |
319 | |
320 | /** | |
321 | * eeh_add_to_parent_pe - Add EEH device to parent PE | |
322 | * @edev: EEH device | |
323 | * | |
324 | * Add EEH device to the parent PE. If the parent PE already | |
325 | * exists, the PE type will be changed to EEH_PE_BUS. Otherwise, | |
326 | * we have to create new PE to hold the EEH device and the new | |
327 | * PE will be linked to its parent PE as well. | |
328 | */ | |
329 | int eeh_add_to_parent_pe(struct eeh_dev *edev) | |
330 | { | |
331 | struct eeh_pe *pe, *parent; | |
332 | ||
333 | /* | |
334 | * Search the PE has been existing or not according | |
335 | * to the PE address. If that has been existing, the | |
336 | * PE should be composed of PCI bus and its subordinate | |
337 | * components. | |
338 | */ | |
339 | pe = eeh_pe_get(edev); | |
5efc3ad7 | 340 | if (pe && !(pe->type & EEH_PE_INVALID)) { |
9b84348c GS |
341 | if (!edev->pe_config_addr) { |
342 | pr_err("%s: PE with addr 0x%x already exists\n", | |
343 | __func__, edev->config_addr); | |
344 | return -EEXIST; | |
345 | } | |
346 | ||
347 | /* Mark the PE as type of PCI bus */ | |
348 | pe->type = EEH_PE_BUS; | |
349 | edev->pe = pe; | |
350 | ||
351 | /* Put the edev to PE */ | |
352 | list_add_tail(&edev->list, &pe->edevs); | |
353 | pr_debug("EEH: Add %s to Bus PE#%x\n", | |
354 | edev->dn->full_name, pe->addr); | |
355 | ||
5efc3ad7 GS |
356 | return 0; |
357 | } else if (pe && (pe->type & EEH_PE_INVALID)) { | |
358 | list_add_tail(&edev->list, &pe->edevs); | |
359 | edev->pe = pe; | |
360 | /* | |
361 | * We're running to here because of PCI hotplug caused by | |
362 | * EEH recovery. We need clear EEH_PE_INVALID until the top. | |
363 | */ | |
364 | parent = pe; | |
365 | while (parent) { | |
366 | if (!(parent->type & EEH_PE_INVALID)) | |
367 | break; | |
807a827d | 368 | parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP); |
5efc3ad7 GS |
369 | parent = parent->parent; |
370 | } | |
371 | pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n", | |
372 | edev->dn->full_name, pe->addr, pe->parent->addr); | |
373 | ||
9b84348c GS |
374 | return 0; |
375 | } | |
376 | ||
377 | /* Create a new EEH PE */ | |
378 | pe = eeh_pe_alloc(edev->phb, EEH_PE_DEVICE); | |
379 | if (!pe) { | |
380 | pr_err("%s: out of memory!\n", __func__); | |
381 | return -ENOMEM; | |
382 | } | |
383 | pe->addr = edev->pe_config_addr; | |
384 | pe->config_addr = edev->config_addr; | |
385 | ||
386 | /* | |
387 | * Put the new EEH PE into hierarchy tree. If the parent | |
388 | * can't be found, the newly created PE will be attached | |
389 | * to PHB directly. Otherwise, we have to associate the | |
390 | * PE with its parent. | |
391 | */ | |
392 | parent = eeh_pe_get_parent(edev); | |
393 | if (!parent) { | |
394 | parent = eeh_phb_pe_get(edev->phb); | |
395 | if (!parent) { | |
396 | pr_err("%s: No PHB PE is found (PHB Domain=%d)\n", | |
397 | __func__, edev->phb->global_number); | |
398 | edev->pe = NULL; | |
399 | kfree(pe); | |
400 | return -EEXIST; | |
401 | } | |
402 | } | |
403 | pe->parent = parent; | |
404 | ||
405 | /* | |
406 | * Put the newly created PE into the child list and | |
407 | * link the EEH device accordingly. | |
408 | */ | |
409 | list_add_tail(&pe->child, &parent->child_list); | |
410 | list_add_tail(&edev->list, &pe->edevs); | |
411 | edev->pe = pe; | |
412 | pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n", | |
413 | edev->dn->full_name, pe->addr, pe->parent->addr); | |
414 | ||
415 | return 0; | |
416 | } | |
82e8882f GS |
417 | |
418 | /** | |
419 | * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE | |
420 | * @edev: EEH device | |
421 | * | |
422 | * The PE hierarchy tree might be changed when doing PCI hotplug. | |
423 | * Also, the PCI devices or buses could be removed from the system | |
424 | * during EEH recovery. So we have to call the function remove the | |
425 | * corresponding PE accordingly if necessary. | |
426 | */ | |
807a827d | 427 | int eeh_rmv_from_parent_pe(struct eeh_dev *edev) |
82e8882f | 428 | { |
5efc3ad7 GS |
429 | struct eeh_pe *pe, *parent, *child; |
430 | int cnt; | |
82e8882f GS |
431 | |
432 | if (!edev->pe) { | |
f5c57710 GS |
433 | pr_debug("%s: No PE found for EEH device %s\n", |
434 | __func__, edev->dn->full_name); | |
82e8882f GS |
435 | return -EEXIST; |
436 | } | |
437 | ||
438 | /* Remove the EEH device */ | |
2a58222f | 439 | pe = eeh_dev_to_pe(edev); |
82e8882f GS |
440 | edev->pe = NULL; |
441 | list_del(&edev->list); | |
442 | ||
443 | /* | |
444 | * Check if the parent PE includes any EEH devices. | |
445 | * If not, we should delete that. Also, we should | |
446 | * delete the parent PE if it doesn't have associated | |
447 | * child PEs and EEH devices. | |
448 | */ | |
449 | while (1) { | |
450 | parent = pe->parent; | |
5efc3ad7 | 451 | if (pe->type & EEH_PE_PHB) |
82e8882f GS |
452 | break; |
453 | ||
807a827d | 454 | if (!(pe->state & EEH_PE_KEEP)) { |
20ee6a97 GS |
455 | if (list_empty(&pe->edevs) && |
456 | list_empty(&pe->child_list)) { | |
457 | list_del(&pe->child); | |
458 | kfree(pe); | |
459 | } else { | |
460 | break; | |
5efc3ad7 | 461 | } |
20ee6a97 GS |
462 | } else { |
463 | if (list_empty(&pe->edevs)) { | |
464 | cnt = 0; | |
465 | list_for_each_entry(child, &pe->child_list, child) { | |
e716e014 | 466 | if (!(child->type & EEH_PE_INVALID)) { |
20ee6a97 GS |
467 | cnt++; |
468 | break; | |
469 | } | |
470 | } | |
5efc3ad7 | 471 | |
20ee6a97 GS |
472 | if (!cnt) |
473 | pe->type |= EEH_PE_INVALID; | |
474 | else | |
475 | break; | |
476 | } | |
82e8882f GS |
477 | } |
478 | ||
479 | pe = parent; | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
5b663529 | 484 | |
5a71978e GS |
485 | /** |
486 | * eeh_pe_update_time_stamp - Update PE's frozen time stamp | |
487 | * @pe: EEH PE | |
488 | * | |
489 | * We have time stamp for each PE to trace its time of getting | |
490 | * frozen in last hour. The function should be called to update | |
491 | * the time stamp on first error of the specific PE. On the other | |
492 | * handle, we needn't account for errors happened in last hour. | |
493 | */ | |
494 | void eeh_pe_update_time_stamp(struct eeh_pe *pe) | |
495 | { | |
496 | struct timeval tstamp; | |
497 | ||
498 | if (!pe) return; | |
499 | ||
500 | if (pe->freeze_count <= 0) { | |
501 | pe->freeze_count = 0; | |
502 | do_gettimeofday(&pe->tstamp); | |
503 | } else { | |
504 | do_gettimeofday(&tstamp); | |
505 | if (tstamp.tv_sec - pe->tstamp.tv_sec > 3600) { | |
506 | pe->tstamp = tstamp; | |
507 | pe->freeze_count = 0; | |
508 | } | |
509 | } | |
510 | } | |
511 | ||
5b663529 GS |
512 | /** |
513 | * __eeh_pe_state_mark - Mark the state for the PE | |
514 | * @data: EEH PE | |
515 | * @flag: state | |
516 | * | |
517 | * The function is used to mark the indicated state for the given | |
518 | * PE. Also, the associated PCI devices will be put into IO frozen | |
519 | * state as well. | |
520 | */ | |
521 | static void *__eeh_pe_state_mark(void *data, void *flag) | |
522 | { | |
523 | struct eeh_pe *pe = (struct eeh_pe *)data; | |
524 | int state = *((int *)flag); | |
9feed42e | 525 | struct eeh_dev *edev, *tmp; |
5b663529 GS |
526 | struct pci_dev *pdev; |
527 | ||
d2b0f6f7 | 528 | /* Keep the state of permanently removed PE intact */ |
432227e9 | 529 | if (pe->state & EEH_PE_REMOVED) |
d2b0f6f7 GS |
530 | return NULL; |
531 | ||
5b663529 | 532 | pe->state |= state; |
d2b0f6f7 GS |
533 | |
534 | /* Offline PCI devices if applicable */ | |
8315070c | 535 | if (!(state & EEH_PE_ISOLATED)) |
d2b0f6f7 GS |
536 | return NULL; |
537 | ||
9feed42e GS |
538 | eeh_pe_for_each_dev(pe, edev, tmp) { |
539 | pdev = eeh_dev_to_pci_dev(edev); | |
5b663529 GS |
540 | if (pdev) |
541 | pdev->error_state = pci_channel_io_frozen; | |
542 | } | |
543 | ||
b6541db1 GS |
544 | /* Block PCI config access if required */ |
545 | if (pe->state & EEH_PE_CFG_RESTRICTED) | |
546 | pe->state |= EEH_PE_CFG_BLOCKED; | |
547 | ||
5b663529 GS |
548 | return NULL; |
549 | } | |
550 | ||
551 | /** | |
552 | * eeh_pe_state_mark - Mark specified state for PE and its associated device | |
553 | * @pe: EEH PE | |
554 | * | |
555 | * EEH error affects the current PE and its child PEs. The function | |
556 | * is used to mark appropriate state for the affected PEs and the | |
557 | * associated devices. | |
558 | */ | |
559 | void eeh_pe_state_mark(struct eeh_pe *pe, int state) | |
560 | { | |
561 | eeh_pe_traverse(pe, __eeh_pe_state_mark, &state); | |
562 | } | |
563 | ||
d2b0f6f7 GS |
564 | static void *__eeh_pe_dev_mode_mark(void *data, void *flag) |
565 | { | |
566 | struct eeh_dev *edev = data; | |
567 | int mode = *((int *)flag); | |
568 | ||
569 | edev->mode |= mode; | |
570 | ||
571 | return NULL; | |
572 | } | |
573 | ||
574 | /** | |
575 | * eeh_pe_dev_state_mark - Mark state for all device under the PE | |
576 | * @pe: EEH PE | |
577 | * | |
578 | * Mark specific state for all child devices of the PE. | |
579 | */ | |
580 | void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode) | |
581 | { | |
582 | eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode); | |
583 | } | |
584 | ||
5b663529 GS |
585 | /** |
586 | * __eeh_pe_state_clear - Clear state for the PE | |
587 | * @data: EEH PE | |
588 | * @flag: state | |
589 | * | |
590 | * The function is used to clear the indicated state from the | |
591 | * given PE. Besides, we also clear the check count of the PE | |
592 | * as well. | |
593 | */ | |
594 | static void *__eeh_pe_state_clear(void *data, void *flag) | |
595 | { | |
596 | struct eeh_pe *pe = (struct eeh_pe *)data; | |
597 | int state = *((int *)flag); | |
22fca179 GS |
598 | struct eeh_dev *edev, *tmp; |
599 | struct pci_dev *pdev; | |
5b663529 | 600 | |
d2b0f6f7 | 601 | /* Keep the state of permanently removed PE intact */ |
432227e9 | 602 | if (pe->state & EEH_PE_REMOVED) |
d2b0f6f7 GS |
603 | return NULL; |
604 | ||
5b663529 | 605 | pe->state &= ~state; |
d2b0f6f7 | 606 | |
22fca179 GS |
607 | /* |
608 | * Special treatment on clearing isolated state. Clear | |
609 | * check count since last isolation and put all affected | |
610 | * devices to normal state. | |
611 | */ | |
612 | if (!(state & EEH_PE_ISOLATED)) | |
613 | return NULL; | |
614 | ||
615 | pe->check_count = 0; | |
616 | eeh_pe_for_each_dev(pe, edev, tmp) { | |
617 | pdev = eeh_dev_to_pci_dev(edev); | |
618 | if (!pdev) | |
619 | continue; | |
620 | ||
621 | pdev->error_state = pci_channel_io_normal; | |
622 | } | |
5b663529 | 623 | |
b6541db1 GS |
624 | /* Unblock PCI config access if required */ |
625 | if (pe->state & EEH_PE_CFG_RESTRICTED) | |
626 | pe->state &= ~EEH_PE_CFG_BLOCKED; | |
627 | ||
5b663529 GS |
628 | return NULL; |
629 | } | |
630 | ||
631 | /** | |
632 | * eeh_pe_state_clear - Clear state for the PE and its children | |
633 | * @pe: PE | |
634 | * @state: state to be cleared | |
635 | * | |
636 | * When the PE and its children has been recovered from error, | |
637 | * we need clear the error state for that. The function is used | |
638 | * for the purpose. | |
639 | */ | |
640 | void eeh_pe_state_clear(struct eeh_pe *pe, int state) | |
641 | { | |
642 | eeh_pe_traverse(pe, __eeh_pe_state_clear, &state); | |
643 | } | |
9e6d2cf6 | 644 | |
652defed GS |
645 | /* |
646 | * Some PCI bridges (e.g. PLX bridges) have primary/secondary | |
647 | * buses assigned explicitly by firmware, and we probably have | |
648 | * lost that after reset. So we have to delay the check until | |
649 | * the PCI-CFG registers have been restored for the parent | |
650 | * bridge. | |
9e6d2cf6 | 651 | * |
652defed GS |
652 | * Don't use normal PCI-CFG accessors, which probably has been |
653 | * blocked on normal path during the stage. So we need utilize | |
654 | * eeh operations, which is always permitted. | |
9e6d2cf6 | 655 | */ |
4b83bd45 | 656 | static void eeh_bridge_check_link(struct eeh_dev *edev, |
652defed GS |
657 | struct device_node *dn) |
658 | { | |
659 | int cap; | |
660 | uint32_t val; | |
661 | int timeout = 0; | |
662 | ||
663 | /* | |
664 | * We only check root port and downstream ports of | |
665 | * PCIe switches | |
666 | */ | |
4b83bd45 | 667 | if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT))) |
652defed GS |
668 | return; |
669 | ||
4b83bd45 GS |
670 | pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n", |
671 | __func__, edev->phb->global_number, | |
672 | edev->config_addr >> 8, | |
673 | PCI_SLOT(edev->config_addr & 0xFF), | |
674 | PCI_FUNC(edev->config_addr & 0xFF)); | |
652defed GS |
675 | |
676 | /* Check slot status */ | |
4b83bd45 | 677 | cap = edev->pcie_cap; |
652defed GS |
678 | eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val); |
679 | if (!(val & PCI_EXP_SLTSTA_PDS)) { | |
680 | pr_debug(" No card in the slot (0x%04x) !\n", val); | |
681 | return; | |
682 | } | |
683 | ||
684 | /* Check power status if we have the capability */ | |
685 | eeh_ops->read_config(dn, cap + PCI_EXP_SLTCAP, 2, &val); | |
686 | if (val & PCI_EXP_SLTCAP_PCP) { | |
687 | eeh_ops->read_config(dn, cap + PCI_EXP_SLTCTL, 2, &val); | |
688 | if (val & PCI_EXP_SLTCTL_PCC) { | |
689 | pr_debug(" In power-off state, power it on ...\n"); | |
690 | val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC); | |
691 | val |= (0x0100 & PCI_EXP_SLTCTL_PIC); | |
692 | eeh_ops->write_config(dn, cap + PCI_EXP_SLTCTL, 2, val); | |
693 | msleep(2 * 1000); | |
694 | } | |
695 | } | |
696 | ||
697 | /* Enable link */ | |
698 | eeh_ops->read_config(dn, cap + PCI_EXP_LNKCTL, 2, &val); | |
699 | val &= ~PCI_EXP_LNKCTL_LD; | |
700 | eeh_ops->write_config(dn, cap + PCI_EXP_LNKCTL, 2, val); | |
701 | ||
702 | /* Check link */ | |
703 | eeh_ops->read_config(dn, cap + PCI_EXP_LNKCAP, 4, &val); | |
704 | if (!(val & PCI_EXP_LNKCAP_DLLLARC)) { | |
705 | pr_debug(" No link reporting capability (0x%08x) \n", val); | |
706 | msleep(1000); | |
707 | return; | |
708 | } | |
709 | ||
710 | /* Wait the link is up until timeout (5s) */ | |
711 | timeout = 0; | |
712 | while (timeout < 5000) { | |
713 | msleep(20); | |
714 | timeout += 20; | |
715 | ||
716 | eeh_ops->read_config(dn, cap + PCI_EXP_LNKSTA, 2, &val); | |
717 | if (val & PCI_EXP_LNKSTA_DLLLA) | |
718 | break; | |
719 | } | |
720 | ||
721 | if (val & PCI_EXP_LNKSTA_DLLLA) | |
722 | pr_debug(" Link up (%s)\n", | |
723 | (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB"); | |
724 | else | |
725 | pr_debug(" Link not ready (0x%04x)\n", val); | |
726 | } | |
727 | ||
728 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
729 | #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)]) | |
730 | ||
4b83bd45 | 731 | static void eeh_restore_bridge_bars(struct eeh_dev *edev, |
652defed GS |
732 | struct device_node *dn) |
733 | { | |
734 | int i; | |
735 | ||
736 | /* | |
737 | * Device BARs: 0x10 - 0x18 | |
738 | * Bus numbers and windows: 0x18 - 0x30 | |
739 | */ | |
740 | for (i = 4; i < 13; i++) | |
741 | eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]); | |
742 | /* Rom: 0x38 */ | |
743 | eeh_ops->write_config(dn, 14*4, 4, edev->config_space[14]); | |
744 | ||
745 | /* Cache line & Latency timer: 0xC 0xD */ | |
746 | eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1, | |
747 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); | |
748 | eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1, | |
749 | SAVED_BYTE(PCI_LATENCY_TIMER)); | |
750 | /* Max latency, min grant, interrupt ping and line: 0x3C */ | |
751 | eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]); | |
752 | ||
753 | /* PCI Command: 0x4 */ | |
754 | eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]); | |
755 | ||
756 | /* Check the PCIe link is ready */ | |
4b83bd45 | 757 | eeh_bridge_check_link(edev, dn); |
652defed GS |
758 | } |
759 | ||
760 | static void eeh_restore_device_bars(struct eeh_dev *edev, | |
761 | struct device_node *dn) | |
9e6d2cf6 GS |
762 | { |
763 | int i; | |
764 | u32 cmd; | |
9e6d2cf6 GS |
765 | |
766 | for (i = 4; i < 10; i++) | |
767 | eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]); | |
768 | /* 12 == Expansion ROM Address */ | |
769 | eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]); | |
770 | ||
9e6d2cf6 GS |
771 | eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1, |
772 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); | |
773 | eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1, | |
774 | SAVED_BYTE(PCI_LATENCY_TIMER)); | |
775 | ||
776 | /* max latency, min grant, interrupt pin and line */ | |
777 | eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]); | |
778 | ||
779 | /* | |
780 | * Restore PERR & SERR bits, some devices require it, | |
781 | * don't touch the other command bits | |
782 | */ | |
783 | eeh_ops->read_config(dn, PCI_COMMAND, 4, &cmd); | |
784 | if (edev->config_space[1] & PCI_COMMAND_PARITY) | |
785 | cmd |= PCI_COMMAND_PARITY; | |
786 | else | |
787 | cmd &= ~PCI_COMMAND_PARITY; | |
788 | if (edev->config_space[1] & PCI_COMMAND_SERR) | |
789 | cmd |= PCI_COMMAND_SERR; | |
790 | else | |
791 | cmd &= ~PCI_COMMAND_SERR; | |
792 | eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd); | |
652defed GS |
793 | } |
794 | ||
795 | /** | |
796 | * eeh_restore_one_device_bars - Restore the Base Address Registers for one device | |
797 | * @data: EEH device | |
798 | * @flag: Unused | |
799 | * | |
800 | * Loads the PCI configuration space base address registers, | |
801 | * the expansion ROM base address, the latency timer, and etc. | |
802 | * from the saved values in the device node. | |
803 | */ | |
804 | static void *eeh_restore_one_device_bars(void *data, void *flag) | |
805 | { | |
652defed GS |
806 | struct eeh_dev *edev = (struct eeh_dev *)data; |
807 | struct device_node *dn = eeh_dev_to_of_node(edev); | |
808 | ||
f5c57710 | 809 | /* Do special restore for bridges */ |
4b83bd45 GS |
810 | if (edev->mode & EEH_DEV_BRIDGE) |
811 | eeh_restore_bridge_bars(edev, dn); | |
652defed GS |
812 | else |
813 | eeh_restore_device_bars(edev, dn); | |
9e6d2cf6 | 814 | |
1d350544 GS |
815 | if (eeh_ops->restore_config) |
816 | eeh_ops->restore_config(dn); | |
817 | ||
9e6d2cf6 GS |
818 | return NULL; |
819 | } | |
820 | ||
821 | /** | |
822 | * eeh_pe_restore_bars - Restore the PCI config space info | |
823 | * @pe: EEH PE | |
824 | * | |
825 | * This routine performs a recursive walk to the children | |
826 | * of this device as well. | |
827 | */ | |
828 | void eeh_pe_restore_bars(struct eeh_pe *pe) | |
829 | { | |
ea81245c GS |
830 | /* |
831 | * We needn't take the EEH lock since eeh_pe_dev_traverse() | |
832 | * will take that. | |
833 | */ | |
9e6d2cf6 GS |
834 | eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL); |
835 | } | |
9b3c76f0 | 836 | |
357b2f3d GS |
837 | /** |
838 | * eeh_pe_loc_get - Retrieve location code binding to the given PE | |
839 | * @pe: EEH PE | |
840 | * | |
841 | * Retrieve the location code of the given PE. If the primary PE bus | |
842 | * is root bus, we will grab location code from PHB device tree node | |
843 | * or root port. Otherwise, the upstream bridge's device tree node | |
844 | * of the primary PE bus will be checked for the location code. | |
845 | */ | |
846 | const char *eeh_pe_loc_get(struct eeh_pe *pe) | |
847 | { | |
357b2f3d | 848 | struct pci_bus *bus = eeh_pe_bus_get(pe); |
9e5c6e5a MQ |
849 | struct device_node *dn = pci_bus_to_OF_node(bus); |
850 | const char *loc = NULL; | |
357b2f3d | 851 | |
9e5c6e5a MQ |
852 | if (!dn) |
853 | goto out; | |
357b2f3d GS |
854 | |
855 | /* PHB PE or root PE ? */ | |
856 | if (pci_is_root_bus(bus)) { | |
9e5c6e5a MQ |
857 | loc = of_get_property(dn, "ibm,loc-code", NULL); |
858 | if (!loc) | |
859 | loc = of_get_property(dn, "ibm,io-base-loc-code", NULL); | |
357b2f3d | 860 | if (loc) |
9e5c6e5a | 861 | goto out; |
357b2f3d | 862 | |
9e5c6e5a MQ |
863 | /* Check the root port */ |
864 | dn = dn->child; | |
865 | if (!dn) | |
866 | goto out; | |
357b2f3d GS |
867 | } |
868 | ||
869 | loc = of_get_property(dn, "ibm,loc-code", NULL); | |
870 | if (!loc) | |
871 | loc = of_get_property(dn, "ibm,slot-location-code", NULL); | |
357b2f3d GS |
872 | |
873 | out: | |
9e5c6e5a | 874 | return loc ? loc : "N/A"; |
357b2f3d GS |
875 | } |
876 | ||
9b3c76f0 GS |
877 | /** |
878 | * eeh_pe_bus_get - Retrieve PCI bus according to the given PE | |
879 | * @pe: EEH PE | |
880 | * | |
881 | * Retrieve the PCI bus according to the given PE. Basically, | |
882 | * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the | |
883 | * primary PCI bus will be retrieved. The parent bus will be | |
884 | * returned for BUS PE. However, we don't have associated PCI | |
885 | * bus for DEVICE PE. | |
886 | */ | |
887 | struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe) | |
888 | { | |
889 | struct pci_bus *bus = NULL; | |
890 | struct eeh_dev *edev; | |
891 | struct pci_dev *pdev; | |
892 | ||
5efc3ad7 | 893 | if (pe->type & EEH_PE_PHB) { |
9b3c76f0 | 894 | bus = pe->phb->bus; |
5fb62169 GS |
895 | } else if (pe->type & EEH_PE_BUS || |
896 | pe->type & EEH_PE_DEVICE) { | |
8cdb2833 GS |
897 | if (pe->bus) { |
898 | bus = pe->bus; | |
899 | goto out; | |
900 | } | |
901 | ||
9b3c76f0 GS |
902 | edev = list_first_entry(&pe->edevs, struct eeh_dev, list); |
903 | pdev = eeh_dev_to_pci_dev(edev); | |
904 | if (pdev) | |
905 | bus = pdev->bus; | |
906 | } | |
907 | ||
8cdb2833 | 908 | out: |
9b3c76f0 GS |
909 | return bus; |
910 | } |