Commit | Line | Data |
---|---|---|
14cf11af PM |
1 | /* |
2 | * FPU support code, moved here from head.S so that it can be used | |
3 | * by chips which use other head-whatever.S files. | |
4 | * | |
fea23bfe PM |
5 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Copyright (C) 1996 Paul Mackerras. | |
8 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
9 | * | |
14cf11af PM |
10 | * This program is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | */ | |
16 | ||
b3b8dc6c | 17 | #include <asm/reg.h> |
14cf11af PM |
18 | #include <asm/page.h> |
19 | #include <asm/mmu.h> | |
20 | #include <asm/pgtable.h> | |
21 | #include <asm/cputable.h> | |
22 | #include <asm/cache.h> | |
23 | #include <asm/thread_info.h> | |
24 | #include <asm/ppc_asm.h> | |
25 | #include <asm/asm-offsets.h> | |
46f52210 | 26 | #include <asm/ptrace.h> |
14cf11af | 27 | |
72ffff5b | 28 | #ifdef CONFIG_VSX |
0b7673c3 | 29 | #define __REST_32FPVSRS(n,c,base) \ |
72ffff5b MN |
30 | BEGIN_FTR_SECTION \ |
31 | b 2f; \ | |
32 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
33 | REST_32FPRS(n,base); \ | |
34 | b 3f; \ | |
35 | 2: REST_32VSRS(n,c,base); \ | |
36 | 3: | |
37 | ||
0b7673c3 | 38 | #define __SAVE_32FPVSRS(n,c,base) \ |
72ffff5b MN |
39 | BEGIN_FTR_SECTION \ |
40 | b 2f; \ | |
41 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
42 | SAVE_32FPRS(n,base); \ | |
43 | b 3f; \ | |
44 | 2: SAVE_32VSRS(n,c,base); \ | |
45 | 3: | |
46 | #else | |
0b7673c3 MN |
47 | #define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) |
48 | #define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) | |
72ffff5b | 49 | #endif |
0b7673c3 MN |
50 | #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) |
51 | #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) | |
72ffff5b | 52 | |
a2dcbb32 | 53 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
a2dcbb32 MN |
54 | /* void do_load_up_transact_fpu(struct thread_struct *thread) |
55 | * | |
56 | * This is similar to load_up_fpu but for the transactional version of the FP | |
57 | * register set. It doesn't mess with the task MSR or valid flags. | |
58 | * Furthermore, we don't do lazy FP with TM currently. | |
59 | */ | |
60 | _GLOBAL(do_load_up_transact_fpu) | |
61 | mfmsr r6 | |
62 | ori r5,r6,MSR_FP | |
63 | #ifdef CONFIG_VSX | |
64 | BEGIN_FTR_SECTION | |
65 | oris r5,r5,MSR_VSX@h | |
66 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
67 | #endif | |
68 | SYNC | |
69 | MTMSRD(r5) | |
70 | ||
de79f7b9 PM |
71 | addi r7,r3,THREAD_TRANSACT_FPSTATE |
72 | lfd fr0,FPSTATE_FPSCR(r7) | |
a2dcbb32 | 73 | MTFSF_L(fr0) |
de79f7b9 | 74 | REST_32FPVSRS(0, R4, R7) |
a2dcbb32 | 75 | |
a2dcbb32 MN |
76 | blr |
77 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
78 | ||
18461960 PM |
79 | /* |
80 | * Load state from memory into FP registers including FPSCR. | |
81 | * Assumes the caller has enabled FP in the MSR. | |
82 | */ | |
83 | _GLOBAL(load_fp_state) | |
84 | lfd fr0,FPSTATE_FPSCR(r3) | |
85 | MTFSF_L(fr0) | |
86 | REST_32FPVSRS(0, R4, R3) | |
87 | blr | |
88 | ||
89 | /* | |
90 | * Store FP state into memory, including FPSCR | |
91 | * Assumes the caller has enabled FP in the MSR. | |
92 | */ | |
93 | _GLOBAL(store_fp_state) | |
94 | SAVE_32FPVSRS(0, R4, R3) | |
95 | mffs fr0 | |
96 | stfd fr0,FPSTATE_FPSCR(r3) | |
97 | blr | |
98 | ||
14cf11af PM |
99 | /* |
100 | * This task wants to use the FPU now. | |
101 | * On UP, disable FP for the task which had the FPU previously, | |
102 | * and save its floating-point registers in its thread_struct. | |
103 | * Load up this task's FP registers from its thread_struct, | |
104 | * enable the FPU for the current task and return to the task. | |
955c1cab PM |
105 | * Note that on 32-bit this can only use registers that will be |
106 | * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. | |
14cf11af | 107 | */ |
b85a046a | 108 | _GLOBAL(load_up_fpu) |
14cf11af PM |
109 | mfmsr r5 |
110 | ori r5,r5,MSR_FP | |
ce48b210 MN |
111 | #ifdef CONFIG_VSX |
112 | BEGIN_FTR_SECTION | |
113 | oris r5,r5,MSR_VSX@h | |
114 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
115 | #endif | |
14cf11af PM |
116 | SYNC |
117 | MTMSRD(r5) /* enable use of fpu now */ | |
118 | isync | |
14cf11af | 119 | /* enable use of FP after return */ |
b85a046a | 120 | #ifdef CONFIG_PPC32 |
de79f7b9 | 121 | mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
14cf11af PM |
122 | lwz r4,THREAD_FPEXC_MODE(r5) |
123 | ori r9,r9,MSR_FP /* enable FP for current */ | |
124 | or r9,r9,r4 | |
b85a046a PM |
125 | #else |
126 | ld r4,PACACURRENT(r13) | |
127 | addi r5,r4,THREAD /* Get THREAD */ | |
e2f5a3c1 | 128 | lwz r4,THREAD_FPEXC_MODE(r5) |
b85a046a PM |
129 | ori r12,r12,MSR_FP |
130 | or r12,r12,r4 | |
131 | std r12,_MSR(r1) | |
132 | #endif | |
70fe3d98 CB |
133 | /* Don't care if r4 overflows, this is desired behaviour */ |
134 | lbz r4,THREAD_LOAD_FP(r5) | |
135 | addi r4,r4,1 | |
136 | stb r4,THREAD_LOAD_FP(r5) | |
955c1cab PM |
137 | addi r10,r5,THREAD_FPSTATE |
138 | lfd fr0,FPSTATE_FPSCR(r10) | |
3a2c48cf | 139 | MTFSF_L(fr0) |
955c1cab | 140 | REST_32FPVSRS(0, R4, R10) |
14cf11af PM |
141 | /* restore registers and return */ |
142 | /* we haven't used ctr or xer or lr */ | |
6f3d8e69 | 143 | blr |
14cf11af | 144 | |
14cf11af | 145 | /* |
8792468d CB |
146 | * save_fpu(tsk) |
147 | * Save the floating-point registers in its thread_struct. | |
14cf11af PM |
148 | * Enables the FPU for use in the kernel on return. |
149 | */ | |
8792468d | 150 | _GLOBAL(save_fpu) |
14cf11af | 151 | addi r3,r3,THREAD /* want THREAD of task */ |
18461960 | 152 | PPC_LL r6,THREAD_FPSAVEAREA(r3) |
3ddfbcf1 | 153 | PPC_LL r5,PT_REGS(r3) |
18461960 PM |
154 | PPC_LCMPI 0,r6,0 |
155 | bne 2f | |
de79f7b9 | 156 | addi r6,r3,THREAD_FPSTATE |
8792468d | 157 | 2: SAVE_32FPVSRS(0, R4, R6) |
14cf11af | 158 | mffs fr0 |
de79f7b9 | 159 | stfd fr0,FPSTATE_FPSCR(r6) |
14cf11af | 160 | blr |
25c8a78b DG |
161 | |
162 | /* | |
163 | * These are used in the alignment trap handler when emulating | |
164 | * single-precision loads and stores. | |
25c8a78b DG |
165 | */ |
166 | ||
167 | _GLOBAL(cvt_fd) | |
25c8a78b DG |
168 | lfs 0,0(r3) |
169 | stfd 0,0(r4) | |
25c8a78b DG |
170 | blr |
171 | ||
172 | _GLOBAL(cvt_df) | |
25c8a78b DG |
173 | lfd 0,0(r3) |
174 | stfs 0,0(r4) | |
25c8a78b | 175 | blr |