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14cf11af PM |
1 | /* |
2 | * FPU support code, moved here from head.S so that it can be used | |
3 | * by chips which use other head-whatever.S files. | |
4 | * | |
fea23bfe PM |
5 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Copyright (C) 1996 Paul Mackerras. | |
8 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
9 | * | |
14cf11af PM |
10 | * This program is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | */ | |
16 | ||
b3b8dc6c | 17 | #include <asm/reg.h> |
14cf11af PM |
18 | #include <asm/page.h> |
19 | #include <asm/mmu.h> | |
20 | #include <asm/pgtable.h> | |
21 | #include <asm/cputable.h> | |
22 | #include <asm/cache.h> | |
23 | #include <asm/thread_info.h> | |
24 | #include <asm/ppc_asm.h> | |
25 | #include <asm/asm-offsets.h> | |
26 | ||
72ffff5b MN |
27 | #ifdef CONFIG_VSX |
28 | #define REST_32FPVSRS(n,c,base) \ | |
29 | BEGIN_FTR_SECTION \ | |
30 | b 2f; \ | |
31 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
32 | REST_32FPRS(n,base); \ | |
33 | b 3f; \ | |
34 | 2: REST_32VSRS(n,c,base); \ | |
35 | 3: | |
36 | ||
37 | #define SAVE_32FPVSRS(n,c,base) \ | |
38 | BEGIN_FTR_SECTION \ | |
39 | b 2f; \ | |
40 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
41 | SAVE_32FPRS(n,base); \ | |
42 | b 3f; \ | |
43 | 2: SAVE_32VSRS(n,c,base); \ | |
44 | 3: | |
45 | #else | |
46 | #define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) | |
47 | #define SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) | |
48 | #endif | |
49 | ||
14cf11af PM |
50 | /* |
51 | * This task wants to use the FPU now. | |
52 | * On UP, disable FP for the task which had the FPU previously, | |
53 | * and save its floating-point registers in its thread_struct. | |
54 | * Load up this task's FP registers from its thread_struct, | |
55 | * enable the FPU for the current task and return to the task. | |
56 | */ | |
b85a046a | 57 | _GLOBAL(load_up_fpu) |
14cf11af PM |
58 | mfmsr r5 |
59 | ori r5,r5,MSR_FP | |
ce48b210 MN |
60 | #ifdef CONFIG_VSX |
61 | BEGIN_FTR_SECTION | |
62 | oris r5,r5,MSR_VSX@h | |
63 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
64 | #endif | |
14cf11af PM |
65 | SYNC |
66 | MTMSRD(r5) /* enable use of fpu now */ | |
67 | isync | |
68 | /* | |
69 | * For SMP, we don't do lazy FPU switching because it just gets too | |
70 | * horrendously complex, especially when a task switches from one CPU | |
71 | * to another. Instead we call giveup_fpu in switch_to. | |
72 | */ | |
73 | #ifndef CONFIG_SMP | |
e58c3495 | 74 | LOAD_REG_ADDRBASE(r3, last_task_used_math) |
6316222e | 75 | toreal(r3) |
e58c3495 | 76 | PPC_LL r4,ADDROFF(last_task_used_math)(r3) |
3ddfbcf1 | 77 | PPC_LCMPI 0,r4,0 |
14cf11af | 78 | beq 1f |
6316222e | 79 | toreal(r4) |
14cf11af | 80 | addi r4,r4,THREAD /* want last_task_used_math->thread */ |
ce48b210 | 81 | SAVE_32FPVSRS(0, r5, r4) |
14cf11af | 82 | mffs fr0 |
25c8a78b | 83 | stfd fr0,THREAD_FPSCR(r4) |
3ddfbcf1 | 84 | PPC_LL r5,PT_REGS(r4) |
6316222e | 85 | toreal(r5) |
3ddfbcf1 | 86 | PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
14cf11af PM |
87 | li r10,MSR_FP|MSR_FE0|MSR_FE1 |
88 | andc r4,r4,r10 /* disable FP for previous task */ | |
3ddfbcf1 | 89 | PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
14cf11af PM |
90 | 1: |
91 | #endif /* CONFIG_SMP */ | |
92 | /* enable use of FP after return */ | |
b85a046a | 93 | #ifdef CONFIG_PPC32 |
ee43eb78 | 94 | mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
14cf11af PM |
95 | lwz r4,THREAD_FPEXC_MODE(r5) |
96 | ori r9,r9,MSR_FP /* enable FP for current */ | |
97 | or r9,r9,r4 | |
b85a046a PM |
98 | #else |
99 | ld r4,PACACURRENT(r13) | |
100 | addi r5,r4,THREAD /* Get THREAD */ | |
e2f5a3c1 | 101 | lwz r4,THREAD_FPEXC_MODE(r5) |
b85a046a PM |
102 | ori r12,r12,MSR_FP |
103 | or r12,r12,r4 | |
104 | std r12,_MSR(r1) | |
105 | #endif | |
25c8a78b | 106 | lfd fr0,THREAD_FPSCR(r5) |
3a2c48cf | 107 | MTFSF_L(fr0) |
ce48b210 | 108 | REST_32FPVSRS(0, r4, r5) |
14cf11af PM |
109 | #ifndef CONFIG_SMP |
110 | subi r4,r5,THREAD | |
6316222e | 111 | fromreal(r4) |
e58c3495 | 112 | PPC_STL r4,ADDROFF(last_task_used_math)(r3) |
14cf11af PM |
113 | #endif /* CONFIG_SMP */ |
114 | /* restore registers and return */ | |
115 | /* we haven't used ctr or xer or lr */ | |
6f3d8e69 | 116 | blr |
14cf11af | 117 | |
14cf11af PM |
118 | /* |
119 | * giveup_fpu(tsk) | |
120 | * Disable FP for the task given as the argument, | |
121 | * and save the floating-point registers in its thread_struct. | |
122 | * Enables the FPU for use in the kernel on return. | |
123 | */ | |
b85a046a | 124 | _GLOBAL(giveup_fpu) |
14cf11af PM |
125 | mfmsr r5 |
126 | ori r5,r5,MSR_FP | |
ce48b210 MN |
127 | #ifdef CONFIG_VSX |
128 | BEGIN_FTR_SECTION | |
129 | oris r5,r5,MSR_VSX@h | |
130 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
131 | #endif | |
14cf11af PM |
132 | SYNC_601 |
133 | ISYNC_601 | |
134 | MTMSRD(r5) /* enable use of fpu now */ | |
135 | SYNC_601 | |
136 | isync | |
3ddfbcf1 | 137 | PPC_LCMPI 0,r3,0 |
14cf11af PM |
138 | beqlr- /* if no previous owner, done */ |
139 | addi r3,r3,THREAD /* want THREAD of task */ | |
3ddfbcf1 DG |
140 | PPC_LL r5,PT_REGS(r3) |
141 | PPC_LCMPI 0,r5,0 | |
ce48b210 | 142 | SAVE_32FPVSRS(0, r4 ,r3) |
14cf11af | 143 | mffs fr0 |
25c8a78b | 144 | stfd fr0,THREAD_FPSCR(r3) |
14cf11af | 145 | beq 1f |
3ddfbcf1 | 146 | PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
14cf11af | 147 | li r3,MSR_FP|MSR_FE0|MSR_FE1 |
7e875e9d MN |
148 | #ifdef CONFIG_VSX |
149 | BEGIN_FTR_SECTION | |
150 | oris r3,r3,MSR_VSX@h | |
151 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
152 | #endif | |
14cf11af | 153 | andc r4,r4,r3 /* disable FP for previous task */ |
3ddfbcf1 | 154 | PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
14cf11af PM |
155 | 1: |
156 | #ifndef CONFIG_SMP | |
157 | li r5,0 | |
e58c3495 DG |
158 | LOAD_REG_ADDRBASE(r4,last_task_used_math) |
159 | PPC_STL r5,ADDROFF(last_task_used_math)(r4) | |
14cf11af PM |
160 | #endif /* CONFIG_SMP */ |
161 | blr | |
25c8a78b DG |
162 | |
163 | /* | |
164 | * These are used in the alignment trap handler when emulating | |
165 | * single-precision loads and stores. | |
166 | * We restore and save the fpscr so the task gets the same result | |
167 | * and exceptions as if the cpu had performed the load or store. | |
168 | */ | |
169 | ||
170 | _GLOBAL(cvt_fd) | |
171 | lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ | |
3a2c48cf | 172 | MTFSF_L(0) |
25c8a78b DG |
173 | lfs 0,0(r3) |
174 | stfd 0,0(r4) | |
175 | mffs 0 | |
176 | stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */ | |
177 | blr | |
178 | ||
179 | _GLOBAL(cvt_df) | |
180 | lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ | |
3a2c48cf | 181 | MTFSF_L(0) |
25c8a78b DG |
182 | lfd 0,0(r3) |
183 | stfs 0,0(r4) | |
184 | mffs 0 | |
185 | stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */ | |
186 | blr |