Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * | |
12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
14 | * | |
0ebc4cda BH |
15 | * This file contains the entry point for the 64-bit kernel along |
16 | * with some early initialization code common to all 64-bit powerpc | |
17 | * variants. | |
14cf11af PM |
18 | * |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | */ | |
24 | ||
14cf11af | 25 | #include <linux/threads.h> |
b5bbeb23 | 26 | #include <asm/reg.h> |
14cf11af PM |
27 | #include <asm/page.h> |
28 | #include <asm/mmu.h> | |
14cf11af PM |
29 | #include <asm/ppc_asm.h> |
30 | #include <asm/asm-offsets.h> | |
31 | #include <asm/bug.h> | |
32 | #include <asm/cputable.h> | |
33 | #include <asm/setup.h> | |
34 | #include <asm/hvcall.h> | |
c43a55ff | 35 | #include <asm/iseries/lpar_map.h> |
6cb7bfeb | 36 | #include <asm/thread_info.h> |
3f639ee8 | 37 | #include <asm/firmware.h> |
16a15a30 | 38 | #include <asm/page_64.h> |
945feb17 | 39 | #include <asm/irqflags.h> |
2191d657 | 40 | #include <asm/kvm_book3s_asm.h> |
14cf11af | 41 | |
0ebc4cda BH |
42 | /* The physical memory is layed out such that the secondary processor |
43 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow | |
44 | * using the layout described in exceptions-64s.S | |
14cf11af PM |
45 | */ |
46 | ||
47 | /* | |
48 | * Entering into this code we make the following assumptions: | |
0ebc4cda BH |
49 | * |
50 | * For pSeries or server processors: | |
14cf11af PM |
51 | * 1. The MMU is off & open firmware is running in real mode. |
52 | * 2. The kernel is entered at __start | |
53 | * | |
54 | * For iSeries: | |
55 | * 1. The MMU is on (as it always is for iSeries) | |
56 | * 2. The kernel is entered at system_reset_iSeries | |
0ebc4cda BH |
57 | * |
58 | * For Book3E processors: | |
59 | * 1. The MMU is on running in AS0 in a state defined in ePAPR | |
60 | * 2. The kernel is entered at __start | |
14cf11af PM |
61 | */ |
62 | ||
63 | .text | |
64 | .globl _stext | |
65 | _stext: | |
14cf11af PM |
66 | _GLOBAL(__start) |
67 | /* NOP this out unconditionally */ | |
68 | BEGIN_FTR_SECTION | |
b85a046a | 69 | b .__start_initialization_multiplatform |
14cf11af | 70 | END_FTR_SECTION(0, 1) |
14cf11af PM |
71 | |
72 | /* Catch branch to 0 in real mode */ | |
73 | trap | |
74 | ||
1f6a93e4 PM |
75 | /* Secondary processors spin on this value until it becomes nonzero. |
76 | * When it does it contains the real address of the descriptor | |
77 | * of the function that the cpu should jump to to continue | |
78 | * initialization. | |
79 | */ | |
14cf11af PM |
80 | .globl __secondary_hold_spinloop |
81 | __secondary_hold_spinloop: | |
82 | .llong 0x0 | |
83 | ||
84 | /* Secondary processors write this value with their cpu # */ | |
85 | /* after they enter the spin loop immediately below. */ | |
86 | .globl __secondary_hold_acknowledge | |
87 | __secondary_hold_acknowledge: | |
88 | .llong 0x0 | |
89 | ||
1dce0e30 ME |
90 | #ifdef CONFIG_PPC_ISERIES |
91 | /* | |
92 | * At offset 0x20, there is a pointer to iSeries LPAR data. | |
93 | * This is required by the hypervisor | |
94 | */ | |
95 | . = 0x20 | |
96 | .llong hvReleaseData-KERNELBASE | |
97 | #endif /* CONFIG_PPC_ISERIES */ | |
98 | ||
8b8b0cc1 MM |
99 | #ifdef CONFIG_CRASH_DUMP |
100 | /* This flag is set to 1 by a loader if the kernel should run | |
101 | * at the loaded address instead of the linked address. This | |
102 | * is used by kexec-tools to keep the the kdump kernel in the | |
103 | * crash_kernel region. The loader is responsible for | |
104 | * observing the alignment requirement. | |
105 | */ | |
106 | /* Do not move this variable as kexec-tools knows about it. */ | |
107 | . = 0x5c | |
108 | .globl __run_at_load | |
109 | __run_at_load: | |
110 | .long 0x72756e30 /* "run0" -- relocate to 0 by default */ | |
111 | #endif | |
112 | ||
14cf11af PM |
113 | . = 0x60 |
114 | /* | |
75423b7b GL |
115 | * The following code is used to hold secondary processors |
116 | * in a spin loop after they have entered the kernel, but | |
14cf11af PM |
117 | * before the bulk of the kernel has been relocated. This code |
118 | * is relocated to physical address 0x60 before prom_init is run. | |
119 | * All of it must fit below the first exception vector at 0x100. | |
1f6a93e4 PM |
120 | * Use .globl here not _GLOBAL because we want __secondary_hold |
121 | * to be the actual text address, not a descriptor. | |
14cf11af | 122 | */ |
1f6a93e4 PM |
123 | .globl __secondary_hold |
124 | __secondary_hold: | |
2d27cfd3 | 125 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
126 | mfmsr r24 |
127 | ori r24,r24,MSR_RI | |
128 | mtmsrd r24 /* RI on */ | |
2d27cfd3 | 129 | #endif |
f1870f77 | 130 | /* Grab our physical cpu number */ |
14cf11af PM |
131 | mr r24,r3 |
132 | ||
133 | /* Tell the master cpu we're here */ | |
134 | /* Relocation is off & we are located at an address less */ | |
135 | /* than 0x100, so only need to grab low order offset. */ | |
e31aa453 | 136 | std r24,__secondary_hold_acknowledge-_stext(0) |
14cf11af PM |
137 | sync |
138 | ||
139 | /* All secondary cpus wait here until told to start. */ | |
e31aa453 | 140 | 100: ld r4,__secondary_hold_spinloop-_stext(0) |
1f6a93e4 PM |
141 | cmpdi 0,r4,0 |
142 | beq 100b | |
14cf11af | 143 | |
f1870f77 | 144 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
1f6a93e4 | 145 | ld r4,0(r4) /* deref function descriptor */ |
758438a7 | 146 | mtctr r4 |
14cf11af | 147 | mr r3,r24 |
2d27cfd3 | 148 | li r4,0 |
758438a7 | 149 | bctr |
14cf11af PM |
150 | #else |
151 | BUG_OPCODE | |
152 | #endif | |
14cf11af PM |
153 | |
154 | /* This value is used to mark exception frames on the stack. */ | |
155 | .section ".toc","aw" | |
156 | exception_marker: | |
157 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
158 | .text | |
159 | ||
14cf11af | 160 | /* |
0ebc4cda BH |
161 | * On server, we include the exception vectors code here as it |
162 | * relies on absolute addressing which is only possible within | |
163 | * this compilation unit | |
3c726f8d | 164 | */ |
0ebc4cda BH |
165 | #ifdef CONFIG_PPC_BOOK3S |
166 | #include "exceptions-64s.S" | |
1f6a93e4 | 167 | #endif |
3c726f8d | 168 | |
2d27cfd3 BH |
169 | _GLOBAL(generic_secondary_thread_init) |
170 | mr r24,r3 | |
171 | ||
172 | /* turn on 64-bit mode */ | |
173 | bl .enable_64b_mode | |
174 | ||
175 | /* get a valid TOC pointer, wherever we're mapped at */ | |
176 | bl .relative_toc | |
177 | ||
178 | #ifdef CONFIG_PPC_BOOK3E | |
179 | /* Book3E initialization */ | |
180 | mr r3,r24 | |
181 | bl .book3e_secondary_thread_init | |
182 | #endif | |
183 | b generic_secondary_common_init | |
14cf11af PM |
184 | |
185 | /* | |
f39b7a55 OJ |
186 | * On pSeries and most other platforms, secondary processors spin |
187 | * in the following code. | |
14cf11af | 188 | * At entry, r3 = this processor's number (physical cpu id) |
2d27cfd3 BH |
189 | * |
190 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for | |
191 | * this core already exists (setup via some other mechanism such | |
192 | * as SCOM before entry). | |
14cf11af | 193 | */ |
f39b7a55 | 194 | _GLOBAL(generic_secondary_smp_init) |
14cf11af | 195 | mr r24,r3 |
2d27cfd3 BH |
196 | mr r25,r4 |
197 | ||
14cf11af PM |
198 | /* turn on 64-bit mode */ |
199 | bl .enable_64b_mode | |
14cf11af | 200 | |
2d27cfd3 | 201 | /* get a valid TOC pointer, wherever we're mapped at */ |
e31aa453 PM |
202 | bl .relative_toc |
203 | ||
2d27cfd3 BH |
204 | #ifdef CONFIG_PPC_BOOK3E |
205 | /* Book3E initialization */ | |
206 | mr r3,r24 | |
207 | mr r4,r25 | |
208 | bl .book3e_secondary_core_init | |
209 | #endif | |
210 | ||
211 | generic_secondary_common_init: | |
14cf11af PM |
212 | /* Set up a paca value for this processor. Since we have the |
213 | * physical cpu id in r24, we need to search the pacas to find | |
214 | * which logical id maps to our physical one. | |
215 | */ | |
1426d5a3 ME |
216 | LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ |
217 | ld r13,0(r13) /* Get base vaddr of paca array */ | |
14cf11af PM |
218 | li r5,0 /* logical cpu id */ |
219 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
220 | cmpw r6,r24 /* Compare to our id */ | |
221 | beq 2f | |
222 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
223 | addi r5,r5,1 | |
224 | cmpwi r5,NR_CPUS | |
225 | blt 1b | |
226 | ||
227 | mr r3,r24 /* not found, copy phys to r3 */ | |
228 | b .kexec_wait /* next kernel might do better */ | |
229 | ||
ee43eb78 | 230 | 2: mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG */ |
2d27cfd3 BH |
231 | #ifdef CONFIG_PPC_BOOK3E |
232 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ | |
233 | mtspr SPRN_SPRG_TLB_EXFRAME,r12 | |
234 | #endif | |
235 | ||
14cf11af PM |
236 | /* From now on, r24 is expected to be logical cpuid */ |
237 | mr r24,r5 | |
238 | 3: HMT_LOW | |
239 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ | |
240 | /* start. */ | |
14cf11af | 241 | |
f39b7a55 OJ |
242 | #ifndef CONFIG_SMP |
243 | b 3b /* Never go on non-SMP */ | |
244 | #else | |
245 | cmpwi 0,r23,0 | |
246 | beq 3b /* Loop until told to go */ | |
247 | ||
b6f6b98a SR |
248 | sync /* order paca.run and cur_cpu_spec */ |
249 | ||
f39b7a55 | 250 | /* See if we need to call a cpu state restore handler */ |
e31aa453 | 251 | LOAD_REG_ADDR(r23, cur_cpu_spec) |
f39b7a55 OJ |
252 | ld r23,0(r23) |
253 | ld r23,CPU_SPEC_RESTORE(r23) | |
254 | cmpdi 0,r23,0 | |
255 | beq 4f | |
256 | ld r23,0(r23) | |
257 | mtctr r23 | |
258 | bctrl | |
259 | ||
260 | 4: /* Create a temp kernel stack for use before relocation is on. */ | |
14cf11af PM |
261 | ld r1,PACAEMERGSP(r13) |
262 | subi r1,r1,STACK_FRAME_OVERHEAD | |
263 | ||
c705677e | 264 | b __secondary_start |
14cf11af | 265 | #endif |
14cf11af | 266 | |
e31aa453 PM |
267 | /* |
268 | * Turn the MMU off. | |
269 | * Assumes we're mapped EA == RA if the MMU is on. | |
270 | */ | |
2d27cfd3 | 271 | #ifdef CONFIG_PPC_BOOK3S |
14cf11af PM |
272 | _STATIC(__mmu_off) |
273 | mfmsr r3 | |
274 | andi. r0,r3,MSR_IR|MSR_DR | |
275 | beqlr | |
e31aa453 | 276 | mflr r4 |
14cf11af PM |
277 | andc r3,r3,r0 |
278 | mtspr SPRN_SRR0,r4 | |
279 | mtspr SPRN_SRR1,r3 | |
280 | sync | |
281 | rfid | |
282 | b . /* prevent speculative execution */ | |
2d27cfd3 | 283 | #endif |
14cf11af PM |
284 | |
285 | ||
286 | /* | |
287 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
288 | * depending on the value of r5. | |
289 | * | |
290 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
291 | * in r3...r7 | |
292 | * | |
293 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
294 | * DT block, r4 is a physical pointer to the kernel itself | |
295 | * | |
296 | */ | |
297 | _GLOBAL(__start_initialization_multiplatform) | |
e31aa453 PM |
298 | /* Make sure we are running in 64 bits mode */ |
299 | bl .enable_64b_mode | |
300 | ||
301 | /* Get TOC pointer (current runtime address) */ | |
302 | bl .relative_toc | |
303 | ||
304 | /* find out where we are now */ | |
305 | bcl 20,31,$+4 | |
306 | 0: mflr r26 /* r26 = runtime addr here */ | |
307 | addis r26,r26,(_stext - 0b)@ha | |
308 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ | |
309 | ||
14cf11af PM |
310 | /* |
311 | * Are we booted from a PROM Of-type client-interface ? | |
312 | */ | |
313 | cmpldi cr0,r5,0 | |
939e60f6 SR |
314 | beq 1f |
315 | b .__boot_from_prom /* yes -> prom */ | |
316 | 1: | |
14cf11af PM |
317 | /* Save parameters */ |
318 | mr r31,r3 | |
319 | mr r30,r4 | |
320 | ||
2d27cfd3 BH |
321 | #ifdef CONFIG_PPC_BOOK3E |
322 | bl .start_initialization_book3e | |
323 | b .__after_prom_start | |
324 | #else | |
14cf11af | 325 | /* Setup some critical 970 SPRs before switching MMU off */ |
f39b7a55 OJ |
326 | mfspr r0,SPRN_PVR |
327 | srwi r0,r0,16 | |
328 | cmpwi r0,0x39 /* 970 */ | |
329 | beq 1f | |
330 | cmpwi r0,0x3c /* 970FX */ | |
331 | beq 1f | |
332 | cmpwi r0,0x44 /* 970MP */ | |
190a24f5 OJ |
333 | beq 1f |
334 | cmpwi r0,0x45 /* 970GX */ | |
f39b7a55 OJ |
335 | bne 2f |
336 | 1: bl .__cpu_preinit_ppc970 | |
337 | 2: | |
14cf11af | 338 | |
e31aa453 | 339 | /* Switch off MMU if not already off */ |
14cf11af PM |
340 | bl .__mmu_off |
341 | b .__after_prom_start | |
2d27cfd3 | 342 | #endif /* CONFIG_PPC_BOOK3E */ |
14cf11af | 343 | |
939e60f6 | 344 | _INIT_STATIC(__boot_from_prom) |
28794d34 | 345 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
14cf11af PM |
346 | /* Save parameters */ |
347 | mr r31,r3 | |
348 | mr r30,r4 | |
349 | mr r29,r5 | |
350 | mr r28,r6 | |
351 | mr r27,r7 | |
352 | ||
6088857b OH |
353 | /* |
354 | * Align the stack to 16-byte boundary | |
355 | * Depending on the size and layout of the ELF sections in the initial | |
e31aa453 | 356 | * boot binary, the stack pointer may be unaligned on PowerMac |
6088857b | 357 | */ |
c05b4770 LT |
358 | rldicr r1,r1,0,59 |
359 | ||
549e8152 PM |
360 | #ifdef CONFIG_RELOCATABLE |
361 | /* Relocate code for where we are now */ | |
362 | mr r3,r26 | |
363 | bl .relocate | |
364 | #endif | |
365 | ||
14cf11af PM |
366 | /* Restore parameters */ |
367 | mr r3,r31 | |
368 | mr r4,r30 | |
369 | mr r5,r29 | |
370 | mr r6,r28 | |
371 | mr r7,r27 | |
372 | ||
373 | /* Do all of the interaction with OF client interface */ | |
549e8152 | 374 | mr r8,r26 |
14cf11af | 375 | bl .prom_init |
28794d34 BH |
376 | #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
377 | ||
378 | /* We never return. We also hit that trap if trying to boot | |
379 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ | |
14cf11af PM |
380 | trap |
381 | ||
14cf11af | 382 | _STATIC(__after_prom_start) |
549e8152 PM |
383 | #ifdef CONFIG_RELOCATABLE |
384 | /* process relocations for the final address of the kernel */ | |
385 | lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ | |
386 | sldi r25,r25,32 | |
54622f10 | 387 | #ifdef CONFIG_CRASH_DUMP |
8b8b0cc1 MM |
388 | lwz r7,__run_at_load-_stext(r26) |
389 | cmplwi cr0,r7,1 /* kdump kernel ? - stay where we are */ | |
54622f10 MK |
390 | bne 1f |
391 | add r25,r25,r26 | |
392 | #endif | |
393 | 1: mr r3,r25 | |
549e8152 PM |
394 | bl .relocate |
395 | #endif | |
14cf11af PM |
396 | |
397 | /* | |
e31aa453 | 398 | * We need to run with _stext at physical address PHYSICAL_START. |
14cf11af PM |
399 | * This will leave some code in the first 256B of |
400 | * real memory, which are reserved for software use. | |
14cf11af PM |
401 | * |
402 | * Note: This process overwrites the OF exception vectors. | |
14cf11af | 403 | */ |
549e8152 | 404 | li r3,0 /* target addr */ |
2d27cfd3 BH |
405 | #ifdef CONFIG_PPC_BOOK3E |
406 | tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ | |
407 | #endif | |
549e8152 | 408 | mr. r4,r26 /* In some cases the loader may */ |
e31aa453 | 409 | beq 9f /* have already put us at zero */ |
14cf11af PM |
410 | li r6,0x100 /* Start offset, the first 0x100 */ |
411 | /* bytes were copied earlier. */ | |
2d27cfd3 BH |
412 | #ifdef CONFIG_PPC_BOOK3E |
413 | tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ | |
414 | #endif | |
14cf11af | 415 | |
54622f10 MK |
416 | #ifdef CONFIG_CRASH_DUMP |
417 | /* | |
418 | * Check if the kernel has to be running as relocatable kernel based on the | |
8b8b0cc1 | 419 | * variable __run_at_load, if it is set the kernel is treated as relocatable |
54622f10 MK |
420 | * kernel, otherwise it will be moved to PHYSICAL_START |
421 | */ | |
8b8b0cc1 MM |
422 | lwz r7,__run_at_load-_stext(r26) |
423 | cmplwi cr0,r7,1 | |
54622f10 MK |
424 | bne 3f |
425 | ||
426 | li r5,__end_interrupts - _stext /* just copy interrupts */ | |
427 | b 5f | |
428 | 3: | |
429 | #endif | |
430 | lis r5,(copy_to_here - _stext)@ha | |
431 | addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ | |
432 | ||
14cf11af PM |
433 | bl .copy_and_flush /* copy the first n bytes */ |
434 | /* this includes the code being */ | |
435 | /* executed here. */ | |
e31aa453 PM |
436 | addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ |
437 | addi r8,r8,(4f - _stext)@l /* that we just made */ | |
438 | mtctr r8 | |
14cf11af PM |
439 | bctr |
440 | ||
54622f10 MK |
441 | p_end: .llong _end - _stext |
442 | ||
e31aa453 PM |
443 | 4: /* Now copy the rest of the kernel up to _end */ |
444 | addis r5,r26,(p_end - _stext)@ha | |
445 | ld r5,(p_end - _stext)@l(r5) /* get _end */ | |
54622f10 | 446 | 5: bl .copy_and_flush /* copy the rest */ |
e31aa453 PM |
447 | |
448 | 9: b .start_here_multiplatform | |
449 | ||
14cf11af PM |
450 | /* |
451 | * Copy routine used to copy the kernel to start at physical address 0 | |
452 | * and flush and invalidate the caches as needed. | |
453 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
454 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
455 | * | |
456 | * Note: this routine *only* clobbers r0, r6 and lr | |
457 | */ | |
458 | _GLOBAL(copy_and_flush) | |
459 | addi r5,r5,-8 | |
460 | addi r6,r6,-8 | |
5a2fe38d | 461 | 4: li r0,8 /* Use the smallest common */ |
14cf11af PM |
462 | /* denominator cache line */ |
463 | /* size. This results in */ | |
464 | /* extra cache line flushes */ | |
465 | /* but operation is correct. */ | |
466 | /* Can't get cache line size */ | |
467 | /* from NACA as it is being */ | |
468 | /* moved too. */ | |
469 | ||
470 | mtctr r0 /* put # words/line in ctr */ | |
471 | 3: addi r6,r6,8 /* copy a cache line */ | |
472 | ldx r0,r6,r4 | |
473 | stdx r0,r6,r3 | |
474 | bdnz 3b | |
475 | dcbst r6,r3 /* write it to memory */ | |
476 | sync | |
477 | icbi r6,r3 /* flush the icache line */ | |
478 | cmpld 0,r6,r5 | |
479 | blt 4b | |
480 | sync | |
481 | addi r5,r5,8 | |
482 | addi r6,r6,8 | |
483 | blr | |
484 | ||
485 | .align 8 | |
486 | copy_to_here: | |
487 | ||
488 | #ifdef CONFIG_SMP | |
489 | #ifdef CONFIG_PPC_PMAC | |
490 | /* | |
491 | * On PowerMac, secondary processors starts from the reset vector, which | |
492 | * is temporarily turned into a call to one of the functions below. | |
493 | */ | |
494 | .section ".text"; | |
495 | .align 2 ; | |
496 | ||
35499c01 PM |
497 | .globl __secondary_start_pmac_0 |
498 | __secondary_start_pmac_0: | |
499 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
500 | li r24,0 | |
501 | b 1f | |
502 | li r24,1 | |
503 | b 1f | |
504 | li r24,2 | |
505 | b 1f | |
506 | li r24,3 | |
507 | 1: | |
14cf11af PM |
508 | |
509 | _GLOBAL(pmac_secondary_start) | |
510 | /* turn on 64-bit mode */ | |
511 | bl .enable_64b_mode | |
14cf11af | 512 | |
c478b581 BH |
513 | li r0,0 |
514 | mfspr r3,SPRN_HID4 | |
515 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ | |
516 | sync | |
517 | mtspr SPRN_HID4,r3 | |
518 | isync | |
519 | sync | |
520 | slbia | |
521 | ||
e31aa453 PM |
522 | /* get TOC pointer (real address) */ |
523 | bl .relative_toc | |
524 | ||
14cf11af | 525 | /* Copy some CPU settings from CPU 0 */ |
f39b7a55 | 526 | bl .__restore_cpu_ppc970 |
14cf11af PM |
527 | |
528 | /* pSeries do that early though I don't think we really need it */ | |
529 | mfmsr r3 | |
530 | ori r3,r3,MSR_RI | |
531 | mtmsrd r3 /* RI on */ | |
532 | ||
533 | /* Set up a paca value for this processor. */ | |
1426d5a3 ME |
534 | LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ |
535 | ld r4,0(r4) /* Get base vaddr of paca array */ | |
e31aa453 | 536 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
14cf11af | 537 | add r13,r13,r4 /* for this processor. */ |
ee43eb78 | 538 | mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/ |
14cf11af PM |
539 | |
540 | /* Create a temp kernel stack for use before relocation is on. */ | |
541 | ld r1,PACAEMERGSP(r13) | |
542 | subi r1,r1,STACK_FRAME_OVERHEAD | |
543 | ||
c705677e | 544 | b __secondary_start |
14cf11af PM |
545 | |
546 | #endif /* CONFIG_PPC_PMAC */ | |
547 | ||
548 | /* | |
549 | * This function is called after the master CPU has released the | |
550 | * secondary processors. The execution environment is relocation off. | |
551 | * The paca for this processor has the following fields initialized at | |
552 | * this point: | |
553 | * 1. Processor number | |
554 | * 2. Segment table pointer (virtual address) | |
555 | * On entry the following are set: | |
ee43eb78 BH |
556 | * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries |
557 | * r24 = cpu# (in Linux terms) | |
558 | * r13 = paca virtual address | |
559 | * SPRG_PACA = paca virtual address | |
14cf11af | 560 | */ |
2d27cfd3 BH |
561 | .section ".text"; |
562 | .align 2 ; | |
563 | ||
fc68e869 | 564 | .globl __secondary_start |
c705677e | 565 | __secondary_start: |
799d6046 PM |
566 | /* Set thread priority to MEDIUM */ |
567 | HMT_MEDIUM | |
14cf11af | 568 | |
14cf11af | 569 | /* Initialize the kernel stack. Just a repeat for iSeries. */ |
e58c3495 | 570 | LOAD_REG_ADDR(r3, current_set) |
14cf11af | 571 | sldi r28,r24,3 /* get current_set[cpu#] */ |
54a83404 MN |
572 | ldx r14,r3,r28 |
573 | addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
574 | std r14,PACAKSAVE(r13) | |
14cf11af | 575 | |
f761622e ME |
576 | /* Do early setup for that CPU (stab, slb, hash table pointer) */ |
577 | bl .early_setup_secondary | |
578 | ||
54a83404 MN |
579 | /* |
580 | * setup the new stack pointer, but *don't* use this until | |
581 | * translation is on. | |
582 | */ | |
583 | mr r1, r14 | |
584 | ||
799d6046 | 585 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
586 | li r7,0 |
587 | mtlr r7 | |
588 | ||
589 | /* enable MMU and jump to start_secondary */ | |
e58c3495 DG |
590 | LOAD_REG_ADDR(r3, .start_secondary_prolog) |
591 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
d04c56f7 | 592 | #ifdef CONFIG_PPC_ISERIES |
3f639ee8 | 593 | BEGIN_FW_FTR_SECTION |
14cf11af | 594 | ori r4,r4,MSR_EE |
ff3da2e0 BH |
595 | li r8,1 |
596 | stb r8,PACAHARDIRQEN(r13) | |
3f639ee8 | 597 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
14cf11af | 598 | #endif |
d04c56f7 | 599 | BEGIN_FW_FTR_SECTION |
d04c56f7 PM |
600 | stb r7,PACAHARDIRQEN(r13) |
601 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | |
ff3da2e0 | 602 | stb r7,PACASOFTIRQEN(r13) |
d04c56f7 | 603 | |
b5bbeb23 PM |
604 | mtspr SPRN_SRR0,r3 |
605 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 606 | RFI |
14cf11af PM |
607 | b . /* prevent speculative execution */ |
608 | ||
609 | /* | |
610 | * Running with relocation on at this point. All we want to do is | |
e31aa453 PM |
611 | * zero the stack back-chain pointer and get the TOC virtual address |
612 | * before going into C code. | |
14cf11af PM |
613 | */ |
614 | _GLOBAL(start_secondary_prolog) | |
e31aa453 | 615 | ld r2,PACATOC(r13) |
14cf11af PM |
616 | li r3,0 |
617 | std r3,0(r1) /* Zero the stack frame pointer */ | |
618 | bl .start_secondary | |
799d6046 | 619 | b . |
8dbce53c VS |
620 | /* |
621 | * Reset stack pointer and call start_secondary | |
622 | * to continue with online operation when woken up | |
623 | * from cede in cpu offline. | |
624 | */ | |
625 | _GLOBAL(start_secondary_resume) | |
626 | ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ | |
627 | li r3,0 | |
628 | std r3,0(r1) /* Zero the stack frame pointer */ | |
629 | bl .start_secondary | |
630 | b . | |
14cf11af PM |
631 | #endif |
632 | ||
633 | /* | |
634 | * This subroutine clobbers r11 and r12 | |
635 | */ | |
636 | _GLOBAL(enable_64b_mode) | |
637 | mfmsr r11 /* grab the current MSR */ | |
2d27cfd3 BH |
638 | #ifdef CONFIG_PPC_BOOK3E |
639 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ | |
640 | mtmsr r11 | |
641 | #else /* CONFIG_PPC_BOOK3E */ | |
e31aa453 PM |
642 | li r12,(MSR_SF | MSR_ISF)@highest |
643 | sldi r12,r12,48 | |
14cf11af PM |
644 | or r11,r11,r12 |
645 | mtmsrd r11 | |
646 | isync | |
2d27cfd3 | 647 | #endif |
14cf11af PM |
648 | blr |
649 | ||
e31aa453 PM |
650 | /* |
651 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected | |
652 | * by the toolchain). It computes the correct value for wherever we | |
653 | * are running at the moment, using position-independent code. | |
654 | */ | |
655 | _GLOBAL(relative_toc) | |
656 | mflr r0 | |
657 | bcl 20,31,$+4 | |
658 | 0: mflr r9 | |
659 | ld r2,(p_toc - 0b)(r9) | |
660 | add r2,r2,r9 | |
661 | mtlr r0 | |
662 | blr | |
663 | ||
664 | p_toc: .llong __toc_start + 0x8000 - 0b | |
665 | ||
14cf11af PM |
666 | /* |
667 | * This is where the main kernel code starts. | |
668 | */ | |
939e60f6 | 669 | _INIT_STATIC(start_here_multiplatform) |
e31aa453 PM |
670 | /* set up the TOC (real address) */ |
671 | bl .relative_toc | |
14cf11af PM |
672 | |
673 | /* Clear out the BSS. It may have been done in prom_init, | |
674 | * already but that's irrelevant since prom_init will soon | |
675 | * be detached from the kernel completely. Besides, we need | |
676 | * to clear it now for kexec-style entry. | |
677 | */ | |
e31aa453 PM |
678 | LOAD_REG_ADDR(r11,__bss_stop) |
679 | LOAD_REG_ADDR(r8,__bss_start) | |
14cf11af PM |
680 | sub r11,r11,r8 /* bss size */ |
681 | addi r11,r11,7 /* round up to an even double word */ | |
e31aa453 | 682 | srdi. r11,r11,3 /* shift right by 3 */ |
14cf11af PM |
683 | beq 4f |
684 | addi r8,r8,-8 | |
685 | li r0,0 | |
686 | mtctr r11 /* zero this many doublewords */ | |
687 | 3: stdu r0,8(r8) | |
688 | bdnz 3b | |
689 | 4: | |
690 | ||
2d27cfd3 | 691 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
692 | mfmsr r6 |
693 | ori r6,r6,MSR_RI | |
694 | mtmsrd r6 /* RI on */ | |
2d27cfd3 | 695 | #endif |
14cf11af | 696 | |
549e8152 PM |
697 | #ifdef CONFIG_RELOCATABLE |
698 | /* Save the physical address we're running at in kernstart_addr */ | |
699 | LOAD_REG_ADDR(r4, kernstart_addr) | |
700 | clrldi r0,r25,2 | |
701 | std r0,0(r4) | |
702 | #endif | |
703 | ||
e31aa453 | 704 | /* The following gets the stack set up with the regs */ |
14cf11af PM |
705 | /* pointing to the real addr of the kernel stack. This is */ |
706 | /* all done to support the C function call below which sets */ | |
707 | /* up the htab. This is done because we have relocated the */ | |
708 | /* kernel but are still running in real mode. */ | |
709 | ||
e31aa453 | 710 | LOAD_REG_ADDR(r3,init_thread_union) |
14cf11af | 711 | |
e31aa453 | 712 | /* set up a stack pointer */ |
14cf11af PM |
713 | addi r1,r3,THREAD_SIZE |
714 | li r0,0 | |
715 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
716 | ||
14cf11af PM |
717 | /* Do very early kernel initializations, including initial hash table, |
718 | * stab and slb setup before we turn on relocation. */ | |
719 | ||
720 | /* Restore parameters passed from prom_init/kexec */ | |
721 | mr r3,r31 | |
ee43eb78 | 722 | bl .early_setup /* also sets r13 and SPRG_PACA */ |
14cf11af | 723 | |
e31aa453 PM |
724 | LOAD_REG_ADDR(r3, .start_here_common) |
725 | ld r4,PACAKMSR(r13) | |
b5bbeb23 PM |
726 | mtspr SPRN_SRR0,r3 |
727 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 728 | RFI |
14cf11af | 729 | b . /* prevent speculative execution */ |
14cf11af PM |
730 | |
731 | /* This is where all platforms converge execution */ | |
fc68e869 | 732 | _INIT_GLOBAL(start_here_common) |
14cf11af | 733 | /* relocation is on at this point */ |
e31aa453 | 734 | std r1,PACAKSAVE(r13) |
14cf11af | 735 | |
e31aa453 | 736 | /* Load the TOC (virtual address) */ |
14cf11af | 737 | ld r2,PACATOC(r13) |
14cf11af PM |
738 | |
739 | bl .setup_system | |
740 | ||
741 | /* Load up the kernel context */ | |
742 | 5: | |
14cf11af | 743 | li r5,0 |
d04c56f7 PM |
744 | stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ |
745 | #ifdef CONFIG_PPC_ISERIES | |
746 | BEGIN_FW_FTR_SECTION | |
14cf11af | 747 | mfmsr r5 |
ff3da2e0 | 748 | ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/ |
14cf11af | 749 | mtmsrd r5 |
ff3da2e0 | 750 | li r5,1 |
3f639ee8 | 751 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
14cf11af | 752 | #endif |
ff3da2e0 | 753 | stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */ |
14cf11af | 754 | |
ff3da2e0 | 755 | bl .start_kernel |
14cf11af | 756 | |
f1870f77 AB |
757 | /* Not reached */ |
758 | BUG_OPCODE | |
14cf11af | 759 | |
14cf11af PM |
760 | /* |
761 | * We put a few things here that have to be page-aligned. | |
762 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
763 | */ | |
764 | .section ".bss" | |
765 | ||
766 | .align PAGE_SHIFT | |
767 | ||
768 | .globl empty_zero_page | |
769 | empty_zero_page: | |
770 | .space PAGE_SIZE | |
771 | ||
772 | .globl swapper_pg_dir | |
773 | swapper_pg_dir: | |
ee7a76da | 774 | .space PGD_TABLE_SIZE |