Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Kernel execution entry point code. |
3 | * | |
4 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
3c5df5c2 | 5 | * Initial PowerPC version. |
14cf11af | 6 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> |
3c5df5c2 | 7 | * Rewritten for PReP |
14cf11af | 8 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> |
3c5df5c2 | 9 | * Low-level exception handers, MMU support, and rewrite. |
14cf11af | 10 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> |
3c5df5c2 | 11 | * PowerPC 8xx modifications. |
14cf11af | 12 | * Copyright (c) 1998-1999 TiVo, Inc. |
3c5df5c2 | 13 | * PowerPC 403GCX modifications. |
14cf11af | 14 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> |
3c5df5c2 | 15 | * PowerPC 403GCX/405GP modifications. |
14cf11af PM |
16 | * Copyright 2000 MontaVista Software Inc. |
17 | * PPC405 modifications | |
3c5df5c2 KG |
18 | * PowerPC 403GCX/405GP modifications. |
19 | * Author: MontaVista Software, Inc. | |
20 | * frank_rowand@mvista.com or source@mvista.com | |
21 | * debbie_chu@mvista.com | |
14cf11af | 22 | * Copyright 2002-2004 MontaVista Software, Inc. |
3c5df5c2 | 23 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> |
14cf11af | 24 | * Copyright 2004 Freescale Semiconductor, Inc |
3c5df5c2 | 25 | * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> |
14cf11af PM |
26 | * |
27 | * This program is free software; you can redistribute it and/or modify it | |
28 | * under the terms of the GNU General Public License as published by the | |
29 | * Free Software Foundation; either version 2 of the License, or (at your | |
30 | * option) any later version. | |
31 | */ | |
32 | ||
e7039845 | 33 | #include <linux/init.h> |
14cf11af PM |
34 | #include <linux/threads.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/page.h> | |
37 | #include <asm/mmu.h> | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/cputable.h> | |
40 | #include <asm/thread_info.h> | |
41 | #include <asm/ppc_asm.h> | |
42 | #include <asm/asm-offsets.h> | |
fc4033b2 | 43 | #include <asm/cache.h> |
46f52210 | 44 | #include <asm/ptrace.h> |
14cf11af PM |
45 | #include "head_booke.h" |
46 | ||
47 | /* As with the other PowerPC ports, it is expected that when code | |
48 | * execution begins here, the following registers contain valid, yet | |
49 | * optional, information: | |
50 | * | |
51 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
52 | * r4 - Starting address of the init RAM disk | |
53 | * r5 - Ending address of the init RAM disk | |
54 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
55 | * r7 - End of kernel command line string | |
56 | * | |
57 | */ | |
e7039845 | 58 | __HEAD |
748a7683 KG |
59 | _ENTRY(_stext); |
60 | _ENTRY(_start); | |
14cf11af PM |
61 | /* |
62 | * Reserve a word at a fixed location to store the address | |
63 | * of abatron_pteptrs | |
64 | */ | |
65 | nop | |
6dece0eb SW |
66 | |
67 | /* Translate device tree address to physical, save in r30/r31 */ | |
99739611 KH |
68 | bl get_phys_addr |
69 | mr r30,r3 | |
70 | mr r31,r4 | |
6dece0eb SW |
71 | |
72 | li r25,0 /* phys kernel start (low) */ | |
73 | li r24,0 /* CPU number */ | |
74 | li r23,0 /* phys kernel start (high) */ | |
14cf11af | 75 | |
dd189692 KH |
76 | #ifdef CONFIG_RELOCATABLE |
77 | LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */ | |
78 | ||
79 | /* Translate _stext address to physical, save in r23/r25 */ | |
80 | bl get_phys_addr | |
81 | mr r23,r3 | |
82 | mr r25,r4 | |
83 | ||
7d2471f9 KH |
84 | bl 0f |
85 | 0: mflr r8 | |
86 | addis r3,r8,(is_second_reloc - 0b)@ha | |
87 | lwz r19,(is_second_reloc - 0b)@l(r3) | |
88 | ||
89 | /* Check if this is the second relocation. */ | |
90 | cmpwi r19,1 | |
91 | bne 1f | |
92 | ||
93 | /* | |
94 | * For the second relocation, we already get the real memstart_addr | |
95 | * from device tree. So we will map PAGE_OFFSET to memstart_addr, | |
96 | * then the virtual address of start kernel should be: | |
97 | * PAGE_OFFSET + (kernstart_addr - memstart_addr) | |
98 | * Since the offset between kernstart_addr and memstart_addr should | |
99 | * never be beyond 1G, so we can just use the lower 32bit of them | |
100 | * for the calculation. | |
101 | */ | |
102 | lis r3,PAGE_OFFSET@h | |
103 | ||
104 | addis r4,r8,(kernstart_addr - 0b)@ha | |
105 | addi r4,r4,(kernstart_addr - 0b)@l | |
106 | lwz r5,4(r4) | |
107 | ||
108 | addis r6,r8,(memstart_addr - 0b)@ha | |
109 | addi r6,r6,(memstart_addr - 0b)@l | |
110 | lwz r7,4(r6) | |
111 | ||
112 | subf r5,r7,r5 | |
113 | add r3,r3,r5 | |
114 | b 2f | |
115 | ||
116 | 1: | |
dd189692 KH |
117 | /* |
118 | * We have the runtime (virutal) address of our base. | |
119 | * We calculate our shift of offset from a 64M page. | |
120 | * We could map the 64M page we belong to at PAGE_OFFSET and | |
121 | * get going from there. | |
122 | */ | |
123 | lis r4,KERNELBASE@h | |
124 | ori r4,r4,KERNELBASE@l | |
125 | rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */ | |
126 | rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */ | |
127 | subf r3,r5,r6 /* r3 = r6 - r5 */ | |
128 | add r3,r4,r3 /* Required Virtual Address */ | |
129 | ||
7d2471f9 KH |
130 | 2: bl relocate |
131 | ||
132 | /* | |
133 | * For the second relocation, we already set the right tlb entries | |
134 | * for the kernel space, so skip the code in fsl_booke_entry_mapping.S | |
135 | */ | |
136 | cmpwi r19,1 | |
137 | beq set_ivor | |
dd189692 KH |
138 | #endif |
139 | ||
14cf11af PM |
140 | /* We try to not make any assumptions about how the boot loader |
141 | * setup or used the TLBs. We invalidate all mappings from the | |
142 | * boot loader and load a single entry in TLB1[0] to map the | |
e8b63761 DF |
143 | * first 64M of kernel memory. Any boot info passed from the |
144 | * bootloader needs to live in this first 64M. | |
14cf11af PM |
145 | * |
146 | * Requirement on bootloader: | |
147 | * - The page we're executing in needs to reside in TLB1 and | |
148 | * have IPROT=1. If not an invalidate broadcast could | |
149 | * evict the entry we're currently executing in. | |
150 | * | |
151 | * r3 = Index of TLB1 were executing in | |
152 | * r4 = Current MSR[IS] | |
153 | * r5 = Index of TLB1 temp mapping | |
154 | * | |
155 | * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] | |
156 | * if needed | |
157 | */ | |
158 | ||
d5b26db2 | 159 | _ENTRY(__early_start) |
105c31df | 160 | |
b3df895a | 161 | #define ENTRY_MAPPING_BOOT_SETUP |
7c08ce71 | 162 | #include "fsl_booke_entry_mapping.S" |
b3df895a | 163 | #undef ENTRY_MAPPING_BOOT_SETUP |
14cf11af | 164 | |
7d2471f9 | 165 | set_ivor: |
14cf11af PM |
166 | /* Establish the interrupt vector offsets */ |
167 | SET_IVOR(0, CriticalInput); | |
168 | SET_IVOR(1, MachineCheck); | |
169 | SET_IVOR(2, DataStorage); | |
170 | SET_IVOR(3, InstructionStorage); | |
171 | SET_IVOR(4, ExternalInput); | |
172 | SET_IVOR(5, Alignment); | |
173 | SET_IVOR(6, Program); | |
174 | SET_IVOR(7, FloatingPointUnavailable); | |
175 | SET_IVOR(8, SystemCall); | |
176 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
177 | SET_IVOR(10, Decrementer); | |
178 | SET_IVOR(11, FixedIntervalTimer); | |
179 | SET_IVOR(12, WatchdogTimer); | |
180 | SET_IVOR(13, DataTLBError); | |
181 | SET_IVOR(14, InstructionTLBError); | |
eb0cd5fd | 182 | SET_IVOR(15, DebugCrit); |
14cf11af PM |
183 | |
184 | /* Establish the interrupt vector base */ | |
185 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
186 | mtspr SPRN_IVPR,r4 | |
187 | ||
188 | /* Setup the defaults for TLB entries */ | |
d66c82ea | 189 | li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l |
14cf11af PM |
190 | #ifdef CONFIG_E200 |
191 | oris r2,r2,MAS4_TLBSELD(1)@h | |
192 | #endif | |
3c5df5c2 | 193 | mtspr SPRN_MAS4, r2 |
14cf11af PM |
194 | |
195 | #if 0 | |
196 | /* Enable DOZE */ | |
197 | mfspr r2,SPRN_HID0 | |
198 | oris r2,r2,HID0_DOZE@h | |
199 | mtspr SPRN_HID0, r2 | |
200 | #endif | |
14cf11af PM |
201 | |
202 | #if !defined(CONFIG_BDI_SWITCH) | |
203 | /* | |
204 | * The Abatron BDI JTAG debugger does not tolerate others | |
205 | * mucking with the debug registers. | |
206 | */ | |
207 | lis r2,DBCR0_IDM@h | |
208 | mtspr SPRN_DBCR0,r2 | |
a7cb0337 | 209 | isync |
14cf11af PM |
210 | /* clear any residual debug events */ |
211 | li r2,-1 | |
212 | mtspr SPRN_DBSR,r2 | |
213 | #endif | |
214 | ||
d5b26db2 KG |
215 | #ifdef CONFIG_SMP |
216 | /* Check to see if we're the second processor, and jump | |
217 | * to the secondary_start code if so | |
218 | */ | |
0be7d969 | 219 | LOAD_REG_ADDR_PIC(r24, boot_cpuid) |
2ed38b23 MM |
220 | lwz r24, 0(r24) |
221 | cmpwi r24, -1 | |
222 | mfspr r24,SPRN_PIR | |
d5b26db2 KG |
223 | bne __secondary_start |
224 | #endif | |
225 | ||
14cf11af PM |
226 | /* |
227 | * This is where the main kernel code starts. | |
228 | */ | |
229 | ||
230 | /* ptr to current */ | |
231 | lis r2,init_task@h | |
232 | ori r2,r2,init_task@l | |
233 | ||
234 | /* ptr to current thread */ | |
235 | addi r4,r2,THREAD /* init task's THREAD */ | |
ee43eb78 | 236 | mtspr SPRN_SPRG_THREAD,r4 |
14cf11af PM |
237 | |
238 | /* stack */ | |
239 | lis r1,init_thread_union@h | |
240 | ori r1,r1,init_thread_union@l | |
241 | li r0,0 | |
242 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
243 | ||
9778b696 | 244 | CURRENT_THREAD_INFO(r22, r1) |
2ed38b23 MM |
245 | stw r24, TI_CPU(r22) |
246 | ||
14cf11af PM |
247 | bl early_init |
248 | ||
dd189692 | 249 | #ifdef CONFIG_RELOCATABLE |
7d2471f9 KH |
250 | mr r3,r30 |
251 | mr r4,r31 | |
dd189692 | 252 | #ifdef CONFIG_PHYS_64BIT |
7d2471f9 KH |
253 | mr r5,r23 |
254 | mr r6,r25 | |
dd189692 | 255 | #else |
7d2471f9 | 256 | mr r5,r25 |
dd189692 KH |
257 | #endif |
258 | bl relocate_init | |
259 | #endif | |
260 | ||
0f890c8d | 261 | #ifdef CONFIG_DYNAMIC_MEMSTART |
37dd2bad KG |
262 | lis r3,kernstart_addr@ha |
263 | la r3,kernstart_addr@l(r3) | |
264 | #ifdef CONFIG_PHYS_64BIT | |
265 | stw r23,0(r3) | |
266 | stw r25,4(r3) | |
267 | #else | |
268 | stw r25,0(r3) | |
269 | #endif | |
270 | #endif | |
271 | ||
14cf11af PM |
272 | /* |
273 | * Decide what sort of machine this is and initialize the MMU. | |
274 | */ | |
6dece0eb SW |
275 | mr r3,r30 |
276 | mr r4,r31 | |
14cf11af PM |
277 | bl machine_init |
278 | bl MMU_init | |
279 | ||
280 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
281 | lis r6, swapper_pg_dir@h | |
282 | ori r6, r6, swapper_pg_dir@l | |
283 | lis r5, abatron_pteptrs@h | |
284 | ori r5, r5, abatron_pteptrs@l | |
285 | lis r4, KERNELBASE@h | |
286 | ori r4, r4, KERNELBASE@l | |
287 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ | |
288 | stw r6, 0(r5) | |
289 | ||
290 | /* Let's move on */ | |
291 | lis r4,start_kernel@h | |
292 | ori r4,r4,start_kernel@l | |
293 | lis r3,MSR_KERNEL@h | |
294 | ori r3,r3,MSR_KERNEL@l | |
295 | mtspr SPRN_SRR0,r4 | |
296 | mtspr SPRN_SRR1,r3 | |
297 | rfi /* change context and jump to start_kernel */ | |
298 | ||
299 | /* Macros to hide the PTE size differences | |
300 | * | |
301 | * FIND_PTE -- walks the page tables given EA & pgdir pointer | |
302 | * r10 -- EA of fault | |
303 | * r11 -- PGDIR pointer | |
304 | * r12 -- free | |
305 | * label 2: is the bailout case | |
306 | * | |
307 | * if we find the pte (fall through): | |
308 | * r11 is low pte word | |
309 | * r12 is pointer to the pte | |
41151e77 | 310 | * r10 is the pshift from the PGD, if we're a hugepage |
14cf11af PM |
311 | */ |
312 | #ifdef CONFIG_PTE_64BIT | |
41151e77 BB |
313 | #ifdef CONFIG_HUGETLB_PAGE |
314 | #define FIND_PTE \ | |
315 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ | |
316 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ | |
317 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
318 | blt 1000f; /* Normal non-huge page */ \ | |
319 | beq 2f; /* Bail if no table */ \ | |
320 | oris r11, r11, PD_HUGE@h; /* Put back address bit */ \ | |
321 | andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \ | |
322 | xor r12, r10, r11; /* drop size bits from pointer */ \ | |
323 | b 1001f; \ | |
324 | 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
325 | li r10, 0; /* clear r10 */ \ | |
326 | 1001: lwz r11, 4(r12); /* Get pte entry */ | |
327 | #else | |
14cf11af | 328 | #define FIND_PTE \ |
3c5df5c2 | 329 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ |
14cf11af PM |
330 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ |
331 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
332 | beq 2f; /* Bail if no table */ \ | |
333 | rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
334 | lwz r11, 4(r12); /* Get pte entry */ | |
41151e77 BB |
335 | #endif /* HUGEPAGE */ |
336 | #else /* !PTE_64BIT */ | |
14cf11af PM |
337 | #define FIND_PTE \ |
338 | rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ | |
339 | lwz r11, 0(r11); /* Get L1 entry */ \ | |
340 | rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ | |
341 | beq 2f; /* Bail if no table */ \ | |
342 | rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ | |
343 | lwz r11, 0(r12); /* Get Linux PTE */ | |
344 | #endif | |
345 | ||
346 | /* | |
347 | * Interrupt vector entry code | |
348 | * | |
349 | * The Book E MMUs are always on so we don't need to handle | |
350 | * interrupts in real mode as with previous PPC processors. In | |
351 | * this case we handle interrupts in the kernel virtual address | |
352 | * space. | |
353 | * | |
354 | * Interrupt vectors are dynamically placed relative to the | |
355 | * interrupt prefix as determined by the address of interrupt_base. | |
356 | * The interrupt vectors offsets are programmed using the labels | |
357 | * for each interrupt vector entry. | |
358 | * | |
359 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
360 | * We align on a 32 byte cache line boundary for good measure. | |
361 | */ | |
362 | ||
363 | interrupt_base: | |
364 | /* Critical Input Interrupt */ | |
cfac5784 | 365 | CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) |
14cf11af PM |
366 | |
367 | /* Machine Check Interrupt */ | |
368 | #ifdef CONFIG_E200 | |
369 | /* no RFMCI, MCSRRs on E200 */ | |
cfac5784 SW |
370 | CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \ |
371 | machine_check_exception) | |
14cf11af | 372 | #else |
dc1c1ca3 | 373 | MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af PM |
374 | #endif |
375 | ||
376 | /* Data Storage Interrupt */ | |
377 | START_EXCEPTION(DataStorage) | |
cfac5784 | 378 | NORMAL_EXCEPTION_PROLOG(DATA_STORAGE) |
6cfd8990 KG |
379 | mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ |
380 | stw r5,_ESR(r11) | |
381 | mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ | |
382 | andis. r10,r5,(ESR_ILK|ESR_DLK)@h | |
383 | bne 1f | |
a546498f | 384 | EXC_XFER_LITE(0x0300, handle_page_fault) |
6cfd8990 KG |
385 | 1: |
386 | addi r3,r1,STACK_FRAME_OVERHEAD | |
387 | EXC_XFER_EE_LITE(0x0300, CacheLockingException) | |
14cf11af PM |
388 | |
389 | /* Instruction Storage Interrupt */ | |
390 | INSTRUCTION_STORAGE_EXCEPTION | |
391 | ||
392 | /* External Input Interrupt */ | |
cfac5784 | 393 | EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE) |
14cf11af PM |
394 | |
395 | /* Alignment Interrupt */ | |
396 | ALIGNMENT_EXCEPTION | |
397 | ||
398 | /* Program Interrupt */ | |
399 | PROGRAM_EXCEPTION | |
400 | ||
401 | /* Floating Point Unavailable Interrupt */ | |
402 | #ifdef CONFIG_PPC_FPU | |
403 | FP_UNAVAILABLE_EXCEPTION | |
404 | #else | |
405 | #ifdef CONFIG_E200 | |
406 | /* E200 treats 'normal' floating point instructions as FP Unavail exception */ | |
cfac5784 SW |
407 | EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \ |
408 | program_check_exception, EXC_XFER_EE) | |
14cf11af | 409 | #else |
cfac5784 SW |
410 | EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \ |
411 | unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
412 | #endif |
413 | #endif | |
414 | ||
415 | /* System Call Interrupt */ | |
416 | START_EXCEPTION(SystemCall) | |
cfac5784 | 417 | NORMAL_EXCEPTION_PROLOG(SYSCALL) |
14cf11af PM |
418 | EXC_XFER_EE_LITE(0x0c00, DoSyscall) |
419 | ||
25985edc | 420 | /* Auxiliary Processor Unavailable Interrupt */ |
cfac5784 SW |
421 | EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \ |
422 | unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
423 | |
424 | /* Decrementer Interrupt */ | |
425 | DECREMENTER_EXCEPTION | |
426 | ||
427 | /* Fixed Internal Timer Interrupt */ | |
428 | /* TODO: Add FIT support */ | |
cfac5784 SW |
429 | EXCEPTION(0x3100, FIT, FixedIntervalTimer, \ |
430 | unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
431 | |
432 | /* Watchdog Timer Interrupt */ | |
433 | #ifdef CONFIG_BOOKE_WDT | |
cfac5784 | 434 | CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException) |
14cf11af | 435 | #else |
cfac5784 | 436 | CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception) |
14cf11af PM |
437 | #endif |
438 | ||
439 | /* Data TLB Error Interrupt */ | |
440 | START_EXCEPTION(DataTLBError) | |
ee43eb78 | 441 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
1325a684 AK |
442 | mfspr r10, SPRN_SPRG_THREAD |
443 | stw r11, THREAD_NORMSAVE(0)(r10) | |
73196cd3 SW |
444 | #ifdef CONFIG_KVM_BOOKE_HV |
445 | BEGIN_FTR_SECTION | |
446 | mfspr r11, SPRN_SRR1 | |
447 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | |
448 | #endif | |
1325a684 AK |
449 | stw r12, THREAD_NORMSAVE(1)(r10) |
450 | stw r13, THREAD_NORMSAVE(2)(r10) | |
451 | mfcr r13 | |
452 | stw r13, THREAD_NORMSAVE(3)(r10) | |
73196cd3 | 453 | DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 |
14cf11af PM |
454 | mfspr r10, SPRN_DEAR /* Get faulting address */ |
455 | ||
456 | /* If we are faulting a kernel address, we have to use the | |
457 | * kernel page tables. | |
458 | */ | |
8a13c4f9 | 459 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
460 | cmplw 5, r10, r11 |
461 | blt 5, 3f | |
462 | lis r11, swapper_pg_dir@h | |
463 | ori r11, r11, swapper_pg_dir@l | |
464 | ||
465 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
466 | rlwinm r12,r12,0,16,1 | |
467 | mtspr SPRN_MAS1,r12 | |
468 | ||
469 | b 4f | |
470 | ||
471 | /* Get the PGD for the current thread */ | |
472 | 3: | |
ee43eb78 | 473 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
474 | lwz r11,PGDIR(r11) |
475 | ||
476 | 4: | |
6cfd8990 KG |
477 | /* Mask of required permission bits. Note that while we |
478 | * do copy ESR:ST to _PAGE_RW position as trying to write | |
479 | * to an RO page is pretty common, we don't do it with | |
480 | * _PAGE_DIRTY. We could do it, but it's a fairly rare | |
481 | * event so I'd rather take the overhead when it happens | |
482 | * rather than adding an instruction here. We should measure | |
483 | * whether the whole thing is worth it in the first place | |
484 | * as we could avoid loading SPRN_ESR completely in the first | |
485 | * place... | |
486 | * | |
487 | * TODO: Is it worth doing that mfspr & rlwimi in the first | |
488 | * place or can we save a couple of instructions here ? | |
489 | */ | |
490 | mfspr r12,SPRN_ESR | |
76acc2c1 KG |
491 | #ifdef CONFIG_PTE_64BIT |
492 | li r13,_PAGE_PRESENT | |
493 | oris r13,r13,_PAGE_ACCESSED@h | |
494 | #else | |
6cfd8990 | 495 | li r13,_PAGE_PRESENT|_PAGE_ACCESSED |
76acc2c1 | 496 | #endif |
6cfd8990 KG |
497 | rlwimi r13,r12,11,29,29 |
498 | ||
14cf11af | 499 | FIND_PTE |
6cfd8990 | 500 | andc. r13,r13,r11 /* Check permission */ |
14cf11af PM |
501 | |
502 | #ifdef CONFIG_PTE_64BIT | |
b38fd42f | 503 | #ifdef CONFIG_SMP |
41151e77 BB |
504 | subf r13,r11,r12 /* create false data dep */ |
505 | lwzx r13,r11,r13 /* Get upper pte bits */ | |
b38fd42f KG |
506 | #else |
507 | lwz r13,0(r12) /* Get upper pte bits */ | |
508 | #endif | |
14cf11af | 509 | #endif |
14cf11af | 510 | |
b38fd42f KG |
511 | bne 2f /* Bail if permission/valid mismach */ |
512 | ||
513 | /* Jump to common tlb load */ | |
14cf11af PM |
514 | b finish_tlb_load |
515 | 2: | |
516 | /* The bailout. Restore registers to pre-exception conditions | |
517 | * and call the heavyweights to help us out. | |
518 | */ | |
1325a684 AK |
519 | mfspr r10, SPRN_SPRG_THREAD |
520 | lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 521 | mtcr r11 |
1325a684 AK |
522 | lwz r13, THREAD_NORMSAVE(2)(r10) |
523 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
524 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 525 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
6cfd8990 | 526 | b DataStorage |
14cf11af PM |
527 | |
528 | /* Instruction TLB Error Interrupt */ | |
529 | /* | |
530 | * Nearly the same as above, except we get our | |
531 | * information from different registers and bailout | |
532 | * to a different point. | |
533 | */ | |
534 | START_EXCEPTION(InstructionTLBError) | |
ee43eb78 | 535 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
1325a684 AK |
536 | mfspr r10, SPRN_SPRG_THREAD |
537 | stw r11, THREAD_NORMSAVE(0)(r10) | |
73196cd3 SW |
538 | #ifdef CONFIG_KVM_BOOKE_HV |
539 | BEGIN_FTR_SECTION | |
540 | mfspr r11, SPRN_SRR1 | |
541 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | |
542 | #endif | |
1325a684 AK |
543 | stw r12, THREAD_NORMSAVE(1)(r10) |
544 | stw r13, THREAD_NORMSAVE(2)(r10) | |
545 | mfcr r13 | |
546 | stw r13, THREAD_NORMSAVE(3)(r10) | |
73196cd3 | 547 | DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 |
14cf11af PM |
548 | mfspr r10, SPRN_SRR0 /* Get faulting address */ |
549 | ||
550 | /* If we are faulting a kernel address, we have to use the | |
551 | * kernel page tables. | |
552 | */ | |
8a13c4f9 | 553 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
554 | cmplw 5, r10, r11 |
555 | blt 5, 3f | |
556 | lis r11, swapper_pg_dir@h | |
557 | ori r11, r11, swapper_pg_dir@l | |
558 | ||
559 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
560 | rlwinm r12,r12,0,16,1 | |
561 | mtspr SPRN_MAS1,r12 | |
562 | ||
78e2e68a LY |
563 | /* Make up the required permissions for kernel code */ |
564 | #ifdef CONFIG_PTE_64BIT | |
565 | li r13,_PAGE_PRESENT | _PAGE_BAP_SX | |
566 | oris r13,r13,_PAGE_ACCESSED@h | |
567 | #else | |
568 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC | |
569 | #endif | |
14cf11af PM |
570 | b 4f |
571 | ||
572 | /* Get the PGD for the current thread */ | |
573 | 3: | |
ee43eb78 | 574 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
575 | lwz r11,PGDIR(r11) |
576 | ||
78e2e68a | 577 | /* Make up the required permissions for user code */ |
76acc2c1 | 578 | #ifdef CONFIG_PTE_64BIT |
78e2e68a | 579 | li r13,_PAGE_PRESENT | _PAGE_BAP_UX |
76acc2c1 KG |
580 | oris r13,r13,_PAGE_ACCESSED@h |
581 | #else | |
ea3cc330 | 582 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC |
76acc2c1 | 583 | #endif |
6cfd8990 | 584 | |
78e2e68a | 585 | 4: |
14cf11af | 586 | FIND_PTE |
6cfd8990 | 587 | andc. r13,r13,r11 /* Check permission */ |
b38fd42f KG |
588 | |
589 | #ifdef CONFIG_PTE_64BIT | |
590 | #ifdef CONFIG_SMP | |
41151e77 BB |
591 | subf r13,r11,r12 /* create false data dep */ |
592 | lwzx r13,r11,r13 /* Get upper pte bits */ | |
b38fd42f KG |
593 | #else |
594 | lwz r13,0(r12) /* Get upper pte bits */ | |
595 | #endif | |
596 | #endif | |
597 | ||
6cfd8990 | 598 | bne 2f /* Bail if permission mismach */ |
14cf11af | 599 | |
14cf11af PM |
600 | /* Jump to common TLB load point */ |
601 | b finish_tlb_load | |
602 | ||
603 | 2: | |
604 | /* The bailout. Restore registers to pre-exception conditions | |
605 | * and call the heavyweights to help us out. | |
606 | */ | |
1325a684 AK |
607 | mfspr r10, SPRN_SPRG_THREAD |
608 | lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 609 | mtcr r11 |
1325a684 AK |
610 | lwz r13, THREAD_NORMSAVE(2)(r10) |
611 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
612 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 613 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
14cf11af PM |
614 | b InstructionStorage |
615 | ||
3477e71d | 616 | /* Define SPE handlers for e200 and e500v2 */ |
14cf11af PM |
617 | #ifdef CONFIG_SPE |
618 | /* SPE Unavailable */ | |
619 | START_EXCEPTION(SPEUnavailable) | |
2b2695a8 | 620 | NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL) |
2dc3d4cc LY |
621 | beq 1f |
622 | bl load_up_spe | |
623 | b fast_exception_return | |
624 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
14cf11af | 625 | EXC_XFER_EE_LITE(0x2010, KernelSPE) |
3477e71d | 626 | #elif defined(CONFIG_SPE_POSSIBLE) |
2b2695a8 | 627 | EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \ |
cfac5784 | 628 | unknown_exception, EXC_XFER_EE) |
3477e71d | 629 | #endif /* CONFIG_SPE_POSSIBLE */ |
14cf11af PM |
630 | |
631 | /* SPE Floating Point Data */ | |
632 | #ifdef CONFIG_SPE | |
2b2695a8 | 633 | EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData, |
c58ce397 | 634 | SPEFloatingPointException, EXC_XFER_EE) |
14cf11af PM |
635 | |
636 | /* SPE Floating Point Round */ | |
cfac5784 SW |
637 | EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ |
638 | SPEFloatingPointRoundException, EXC_XFER_EE) | |
3477e71d | 639 | #elif defined(CONFIG_SPE_POSSIBLE) |
2b2695a8 | 640 | EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, |
cfac5784 SW |
641 | unknown_exception, EXC_XFER_EE) |
642 | EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ | |
643 | unknown_exception, EXC_XFER_EE) | |
3477e71d MC |
644 | #endif /* CONFIG_SPE_POSSIBLE */ |
645 | ||
14cf11af PM |
646 | |
647 | /* Performance Monitor */ | |
cfac5784 SW |
648 | EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \ |
649 | performance_monitor_exception, EXC_XFER_STD) | |
14cf11af | 650 | |
cfac5784 | 651 | EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD) |
620165f9 | 652 | |
cfac5784 SW |
653 | CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \ |
654 | CriticalDoorbell, unknown_exception) | |
14cf11af PM |
655 | |
656 | /* Debug Interrupt */ | |
eb0cd5fd | 657 | DEBUG_DEBUG_EXCEPTION |
eb0cd5fd | 658 | DEBUG_CRIT_EXCEPTION |
14cf11af | 659 | |
73196cd3 SW |
660 | GUEST_DOORBELL_EXCEPTION |
661 | ||
662 | CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \ | |
663 | unknown_exception) | |
664 | ||
665 | /* Hypercall */ | |
666 | EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE) | |
667 | ||
668 | /* Embedded Hypervisor Privilege */ | |
669 | EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE) | |
670 | ||
fc2a6cfe BB |
671 | interrupt_end: |
672 | ||
14cf11af PM |
673 | /* |
674 | * Local functions | |
675 | */ | |
676 | ||
14cf11af | 677 | /* |
14cf11af PM |
678 | * Both the instruction and data TLB miss get to this |
679 | * point to load the TLB. | |
41151e77 | 680 | * r10 - tsize encoding (if HUGETLB_PAGE) or available to use |
3c5df5c2 | 681 | * r11 - TLB (info from Linux PTE) |
6cfd8990 KG |
682 | * r12 - available to use |
683 | * r13 - upper bits of PTE (if PTE_64BIT) or available to use | |
8a13c4f9 | 684 | * CR5 - results of addr >= PAGE_OFFSET |
14cf11af PM |
685 | * MAS0, MAS1 - loaded with proper value when we get here |
686 | * MAS2, MAS3 - will need additional info from Linux PTE | |
687 | * Upon exit, we reload everything and RFI. | |
688 | */ | |
689 | finish_tlb_load: | |
41151e77 BB |
690 | #ifdef CONFIG_HUGETLB_PAGE |
691 | cmpwi 6, r10, 0 /* check for huge page */ | |
692 | beq 6, finish_tlb_load_cont /* !huge */ | |
693 | ||
694 | /* Alas, we need more scratch registers for hugepages */ | |
695 | mfspr r12, SPRN_SPRG_THREAD | |
696 | stw r14, THREAD_NORMSAVE(4)(r12) | |
697 | stw r15, THREAD_NORMSAVE(5)(r12) | |
698 | stw r16, THREAD_NORMSAVE(6)(r12) | |
699 | stw r17, THREAD_NORMSAVE(7)(r12) | |
700 | ||
701 | /* Get the next_tlbcam_idx percpu var */ | |
702 | #ifdef CONFIG_SMP | |
703 | lwz r12, THREAD_INFO-THREAD(r12) | |
704 | lwz r15, TI_CPU(r12) | |
705 | lis r14, __per_cpu_offset@h | |
706 | ori r14, r14, __per_cpu_offset@l | |
707 | rlwinm r15, r15, 2, 0, 29 | |
708 | lwzx r16, r14, r15 | |
709 | #else | |
710 | li r16, 0 | |
711 | #endif | |
712 | lis r17, next_tlbcam_idx@h | |
713 | ori r17, r17, next_tlbcam_idx@l | |
714 | add r17, r17, r16 /* r17 = *next_tlbcam_idx */ | |
715 | lwz r15, 0(r17) /* r15 = next_tlbcam_idx */ | |
716 | ||
717 | lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */ | |
718 | rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */ | |
719 | mtspr SPRN_MAS0, r14 | |
720 | ||
721 | /* Extract TLB1CFG(NENTRY) */ | |
722 | mfspr r16, SPRN_TLB1CFG | |
723 | andi. r16, r16, 0xfff | |
724 | ||
725 | /* Update next_tlbcam_idx, wrapping when necessary */ | |
726 | addi r15, r15, 1 | |
727 | cmpw r15, r16 | |
728 | blt 100f | |
729 | lis r14, tlbcam_index@h | |
730 | ori r14, r14, tlbcam_index@l | |
731 | lwz r15, 0(r14) | |
732 | 100: stw r15, 0(r17) | |
733 | ||
734 | /* | |
735 | * Calc MAS1_TSIZE from r10 (which has pshift encoded) | |
736 | * tlb_enc = (pshift - 10). | |
737 | */ | |
738 | subi r15, r10, 10 | |
739 | mfspr r16, SPRN_MAS1 | |
740 | rlwimi r16, r15, 7, 20, 24 | |
741 | mtspr SPRN_MAS1, r16 | |
742 | ||
743 | /* copy the pshift for use later */ | |
744 | mr r14, r10 | |
745 | ||
746 | /* fall through */ | |
747 | ||
748 | #endif /* CONFIG_HUGETLB_PAGE */ | |
749 | ||
14cf11af PM |
750 | /* |
751 | * We set execute, because we don't have the granularity to | |
752 | * properly set this at the page level (Linux problem). | |
753 | * Many of these bits are software only. Bits we don't set | |
754 | * here we (properly should) assume have the appropriate value. | |
755 | */ | |
41151e77 | 756 | finish_tlb_load_cont: |
76acc2c1 KG |
757 | #ifdef CONFIG_PTE_64BIT |
758 | rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ | |
759 | andi. r10, r11, _PAGE_DIRTY | |
760 | bne 1f | |
761 | li r10, MAS3_SW | MAS3_UW | |
762 | andc r12, r12, r10 | |
763 | 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ | |
764 | rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ | |
41151e77 | 765 | 2: mtspr SPRN_MAS3, r12 |
76acc2c1 KG |
766 | BEGIN_MMU_FTR_SECTION |
767 | srwi r10, r13, 12 /* grab RPN[12:31] */ | |
768 | mtspr SPRN_MAS7, r10 | |
769 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) | |
770 | #else | |
ea3cc330 | 771 | li r10, (_PAGE_EXEC | _PAGE_PRESENT) |
41151e77 | 772 | mr r13, r11 |
6cfd8990 KG |
773 | rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ |
774 | and r12, r11, r10 | |
14cf11af | 775 | andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ |
6cfd8990 KG |
776 | slwi r10, r12, 1 |
777 | or r10, r10, r12 | |
778 | iseleq r12, r12, r10 | |
41151e77 BB |
779 | rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */ |
780 | mtspr SPRN_MAS3, r13 | |
14cf11af | 781 | #endif |
41151e77 BB |
782 | |
783 | mfspr r12, SPRN_MAS2 | |
784 | #ifdef CONFIG_PTE_64BIT | |
785 | rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ | |
786 | #else | |
787 | rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ | |
788 | #endif | |
789 | #ifdef CONFIG_HUGETLB_PAGE | |
790 | beq 6, 3f /* don't mask if page isn't huge */ | |
791 | li r13, 1 | |
792 | slw r13, r13, r14 | |
793 | subi r13, r13, 1 | |
794 | rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */ | |
795 | andc r12, r12, r13 /* mask off ea bits within the page */ | |
796 | #endif | |
797 | 3: mtspr SPRN_MAS2, r12 | |
798 | ||
14cf11af PM |
799 | #ifdef CONFIG_E200 |
800 | /* Round robin TLB1 entries assignment */ | |
801 | mfspr r12, SPRN_MAS0 | |
802 | ||
803 | /* Extract TLB1CFG(NENTRY) */ | |
804 | mfspr r11, SPRN_TLB1CFG | |
805 | andi. r11, r11, 0xfff | |
806 | ||
807 | /* Extract MAS0(NV) */ | |
808 | andi. r13, r12, 0xfff | |
809 | addi r13, r13, 1 | |
810 | cmpw 0, r13, r11 | |
811 | addi r12, r12, 1 | |
812 | ||
813 | /* check if we need to wrap */ | |
814 | blt 7f | |
815 | ||
816 | /* wrap back to first free tlbcam entry */ | |
817 | lis r13, tlbcam_index@ha | |
818 | lwz r13, tlbcam_index@l(r13) | |
819 | rlwimi r12, r13, 0, 20, 31 | |
820 | 7: | |
3c5df5c2 | 821 | mtspr SPRN_MAS0,r12 |
14cf11af PM |
822 | #endif /* CONFIG_E200 */ |
823 | ||
41151e77 | 824 | tlb_write_entry: |
14cf11af PM |
825 | tlbwe |
826 | ||
827 | /* Done...restore registers and get out of here. */ | |
1325a684 | 828 | mfspr r10, SPRN_SPRG_THREAD |
41151e77 BB |
829 | #ifdef CONFIG_HUGETLB_PAGE |
830 | beq 6, 8f /* skip restore for 4k page faults */ | |
831 | lwz r14, THREAD_NORMSAVE(4)(r10) | |
832 | lwz r15, THREAD_NORMSAVE(5)(r10) | |
833 | lwz r16, THREAD_NORMSAVE(6)(r10) | |
834 | lwz r17, THREAD_NORMSAVE(7)(r10) | |
835 | #endif | |
836 | 8: lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 837 | mtcr r11 |
1325a684 AK |
838 | lwz r13, THREAD_NORMSAVE(2)(r10) |
839 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
840 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 841 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
14cf11af PM |
842 | rfi /* Force context change */ |
843 | ||
844 | #ifdef CONFIG_SPE | |
845 | /* Note that the SPE support is closely modeled after the AltiVec | |
846 | * support. Changes to one are likely to be applicable to the | |
847 | * other! */ | |
2dc3d4cc | 848 | _GLOBAL(load_up_spe) |
14cf11af PM |
849 | /* |
850 | * Disable SPE for the task which had SPE previously, | |
851 | * and save its SPE registers in its thread_struct. | |
852 | * Enables SPE for use in the kernel on return. | |
853 | * On SMP we know the SPE units are free, since we give it up every | |
854 | * switch. -- Kumar | |
855 | */ | |
856 | mfmsr r5 | |
857 | oris r5,r5,MSR_SPE@h | |
858 | mtmsr r5 /* enable use of SPE now */ | |
859 | isync | |
14cf11af PM |
860 | /* enable use of SPE after return */ |
861 | oris r9,r9,MSR_SPE@h | |
ee43eb78 | 862 | mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
14cf11af PM |
863 | li r4,1 |
864 | li r10,THREAD_ACC | |
865 | stw r4,THREAD_USED_SPE(r5) | |
866 | evlddx evr4,r10,r5 | |
867 | evmra evr4,evr4 | |
c51584d5 | 868 | REST_32EVRS(0,r10,r5,THREAD_EVR0) |
2dc3d4cc | 869 | blr |
14cf11af PM |
870 | |
871 | /* | |
872 | * SPE unavailable trap from kernel - print a message, but let | |
873 | * the task use SPE in the kernel until it returns to user mode. | |
874 | */ | |
875 | KernelSPE: | |
876 | lwz r3,_MSR(r1) | |
877 | oris r3,r3,MSR_SPE@h | |
878 | stw r3,_MSR(r1) /* enable use of SPE after return */ | |
09156a7a | 879 | #ifdef CONFIG_PRINTK |
14cf11af PM |
880 | lis r3,87f@h |
881 | ori r3,r3,87f@l | |
882 | mr r4,r2 /* current */ | |
883 | lwz r5,_NIP(r1) | |
884 | bl printk | |
09156a7a | 885 | #endif |
14cf11af | 886 | b ret_from_except |
09156a7a | 887 | #ifdef CONFIG_PRINTK |
14cf11af | 888 | 87: .string "SPE used in kernel (task=%p, pc=%x) \n" |
09156a7a | 889 | #endif |
14cf11af PM |
890 | .align 4,0 |
891 | ||
892 | #endif /* CONFIG_SPE */ | |
893 | ||
99739611 KH |
894 | /* |
895 | * Translate the effec addr in r3 to phys addr. The phys addr will be put | |
896 | * into r3(higher 32bit) and r4(lower 32bit) | |
897 | */ | |
898 | get_phys_addr: | |
899 | mfmsr r8 | |
900 | mfspr r9,SPRN_PID | |
901 | rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */ | |
902 | rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */ | |
903 | mtspr SPRN_MAS6,r9 | |
904 | ||
905 | tlbsx 0,r3 /* must succeed */ | |
906 | ||
907 | mfspr r8,SPRN_MAS1 | |
908 | mfspr r12,SPRN_MAS3 | |
909 | rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */ | |
910 | li r10,1024 | |
911 | slw r10,r10,r9 /* r10 = page size */ | |
912 | addi r10,r10,-1 | |
913 | and r11,r3,r10 /* r11 = page offset */ | |
914 | andc r4,r12,r10 /* r4 = page base */ | |
915 | or r4,r4,r11 /* r4 = devtree phys addr */ | |
916 | #ifdef CONFIG_PHYS_64BIT | |
917 | mfspr r3,SPRN_MAS7 | |
918 | #endif | |
919 | blr | |
920 | ||
14cf11af PM |
921 | /* |
922 | * Global functions | |
923 | */ | |
924 | ||
3477e71d | 925 | #ifdef CONFIG_E200 |
105c31df KG |
926 | /* Adjust or setup IVORs for e200 */ |
927 | _GLOBAL(__setup_e200_ivors) | |
928 | li r3,DebugDebug@l | |
929 | mtspr SPRN_IVOR15,r3 | |
930 | li r3,SPEUnavailable@l | |
931 | mtspr SPRN_IVOR32,r3 | |
932 | li r3,SPEFloatingPointData@l | |
933 | mtspr SPRN_IVOR33,r3 | |
934 | li r3,SPEFloatingPointRound@l | |
935 | mtspr SPRN_IVOR34,r3 | |
936 | sync | |
937 | blr | |
3477e71d | 938 | #endif |
105c31df | 939 | |
3477e71d MC |
940 | #ifdef CONFIG_E500 |
941 | #ifndef CONFIG_PPC_E500MC | |
105c31df KG |
942 | /* Adjust or setup IVORs for e500v1/v2 */ |
943 | _GLOBAL(__setup_e500_ivors) | |
944 | li r3,DebugCrit@l | |
945 | mtspr SPRN_IVOR15,r3 | |
946 | li r3,SPEUnavailable@l | |
947 | mtspr SPRN_IVOR32,r3 | |
948 | li r3,SPEFloatingPointData@l | |
949 | mtspr SPRN_IVOR33,r3 | |
950 | li r3,SPEFloatingPointRound@l | |
951 | mtspr SPRN_IVOR34,r3 | |
952 | li r3,PerformanceMonitor@l | |
953 | mtspr SPRN_IVOR35,r3 | |
954 | sync | |
955 | blr | |
3477e71d | 956 | #else |
105c31df KG |
957 | /* Adjust or setup IVORs for e500mc */ |
958 | _GLOBAL(__setup_e500mc_ivors) | |
959 | li r3,DebugDebug@l | |
960 | mtspr SPRN_IVOR15,r3 | |
961 | li r3,PerformanceMonitor@l | |
962 | mtspr SPRN_IVOR35,r3 | |
963 | li r3,Doorbell@l | |
964 | mtspr SPRN_IVOR36,r3 | |
620165f9 KG |
965 | li r3,CriticalDoorbell@l |
966 | mtspr SPRN_IVOR37,r3 | |
7e0f4872 VS |
967 | sync |
968 | blr | |
73196cd3 | 969 | |
7e0f4872 VS |
970 | /* setup ehv ivors for */ |
971 | _GLOBAL(__setup_ehv_ivors) | |
73196cd3 SW |
972 | li r3,GuestDoorbell@l |
973 | mtspr SPRN_IVOR38,r3 | |
974 | li r3,CriticalGuestDoorbell@l | |
975 | mtspr SPRN_IVOR39,r3 | |
976 | li r3,Hypercall@l | |
977 | mtspr SPRN_IVOR40,r3 | |
978 | li r3,Ehvpriv@l | |
979 | mtspr SPRN_IVOR41,r3 | |
105c31df KG |
980 | sync |
981 | blr | |
3477e71d MC |
982 | #endif /* CONFIG_PPC_E500MC */ |
983 | #endif /* CONFIG_E500 */ | |
105c31df | 984 | |
14cf11af PM |
985 | #ifdef CONFIG_SPE |
986 | /* | |
98da581e | 987 | * extern void __giveup_spe(struct task_struct *prev) |
14cf11af PM |
988 | * |
989 | */ | |
98da581e | 990 | _GLOBAL(__giveup_spe) |
14cf11af PM |
991 | addi r3,r3,THREAD /* want THREAD of task */ |
992 | lwz r5,PT_REGS(r3) | |
993 | cmpi 0,r5,0 | |
c51584d5 | 994 | SAVE_32EVRS(0, r4, r3, THREAD_EVR0) |
3c5df5c2 | 995 | evxor evr6, evr6, evr6 /* clear out evr6 */ |
14cf11af PM |
996 | evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ |
997 | li r4,THREAD_ACC | |
3c5df5c2 | 998 | evstddx evr6, r4, r3 /* save off accumulator */ |
14cf11af PM |
999 | beq 1f |
1000 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1001 | lis r3,MSR_SPE@h | |
1002 | andc r4,r4,r3 /* disable SPE for previous task */ | |
1003 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1004 | 1: | |
14cf11af PM |
1005 | blr |
1006 | #endif /* CONFIG_SPE */ | |
1007 | ||
14cf11af PM |
1008 | /* |
1009 | * extern void abort(void) | |
1010 | * | |
1011 | * At present, this routine just applies a system reset. | |
1012 | */ | |
1013 | _GLOBAL(abort) | |
1014 | li r13,0 | |
3c5df5c2 | 1015 | mtspr SPRN_DBCR0,r13 /* disable all debug events */ |
a7cb0337 | 1016 | isync |
14cf11af PM |
1017 | mfmsr r13 |
1018 | ori r13,r13,MSR_DE@l /* Enable Debug Events */ | |
1019 | mtmsr r13 | |
a7cb0337 | 1020 | isync |
3c5df5c2 KG |
1021 | mfspr r13,SPRN_DBCR0 |
1022 | lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h | |
1023 | mtspr SPRN_DBCR0,r13 | |
a7cb0337 | 1024 | isync |
14cf11af PM |
1025 | |
1026 | _GLOBAL(set_context) | |
1027 | ||
1028 | #ifdef CONFIG_BDI_SWITCH | |
1029 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
1030 | * The PGDIR is the second parameter. | |
1031 | */ | |
1032 | lis r5, abatron_pteptrs@h | |
1033 | ori r5, r5, abatron_pteptrs@l | |
1034 | stw r4, 0x4(r5) | |
1035 | #endif | |
1036 | mtspr SPRN_PID,r3 | |
1037 | isync /* Force context change */ | |
1038 | blr | |
1039 | ||
d5b26db2 KG |
1040 | #ifdef CONFIG_SMP |
1041 | /* When we get here, r24 needs to hold the CPU # */ | |
1042 | .globl __secondary_start | |
1043 | __secondary_start: | |
0be7d969 KH |
1044 | LOAD_REG_ADDR_PIC(r3, tlbcam_index) |
1045 | lwz r3,0(r3) | |
d5b26db2 KG |
1046 | mtctr r3 |
1047 | li r26,0 /* r26 safe? */ | |
1048 | ||
0be7d969 KH |
1049 | bl switch_to_as1 |
1050 | mr r27,r3 /* tlb entry */ | |
d5b26db2 KG |
1051 | /* Load each CAM entry */ |
1052 | 1: mr r3,r26 | |
1053 | bl loadcam_entry | |
1054 | addi r26,r26,1 | |
1055 | bdnz 1b | |
0be7d969 KH |
1056 | mr r3,r27 /* tlb entry */ |
1057 | LOAD_REG_ADDR_PIC(r4, memstart_addr) | |
1058 | lwz r4,0(r4) | |
1059 | mr r5,r25 /* phys kernel start */ | |
1060 | rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */ | |
1061 | subf r4,r5,r4 /* memstart_addr - phys kernel start */ | |
1062 | li r5,0 /* no device tree */ | |
1063 | li r6,0 /* not boot cpu */ | |
1064 | bl restore_to_as0 | |
1065 | ||
1066 | ||
1067 | lis r3,__secondary_hold_acknowledge@h | |
1068 | ori r3,r3,__secondary_hold_acknowledge@l | |
1069 | stw r24,0(r3) | |
1070 | ||
1071 | li r3,0 | |
1072 | mr r4,r24 /* Why? */ | |
1073 | bl call_setup_cpu | |
d5b26db2 KG |
1074 | |
1075 | /* get current_thread_info and current */ | |
1076 | lis r1,secondary_ti@ha | |
1077 | lwz r1,secondary_ti@l(r1) | |
1078 | lwz r2,TI_TASK(r1) | |
1079 | ||
1080 | /* stack */ | |
1081 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1082 | li r0,0 | |
1083 | stw r0,0(r1) | |
1084 | ||
1085 | /* ptr to current thread */ | |
1086 | addi r4,r2,THREAD /* address of our thread_struct */ | |
ee43eb78 | 1087 | mtspr SPRN_SPRG_THREAD,r4 |
d5b26db2 KG |
1088 | |
1089 | /* Setup the defaults for TLB entries */ | |
d66c82ea | 1090 | li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l |
d5b26db2 KG |
1091 | mtspr SPRN_MAS4,r4 |
1092 | ||
1093 | /* Jump to start_secondary */ | |
1094 | lis r4,MSR_KERNEL@h | |
1095 | ori r4,r4,MSR_KERNEL@l | |
1096 | lis r3,start_secondary@h | |
1097 | ori r3,r3,start_secondary@l | |
1098 | mtspr SPRN_SRR0,r3 | |
1099 | mtspr SPRN_SRR1,r4 | |
1100 | sync | |
1101 | rfi | |
1102 | sync | |
1103 | ||
1104 | .globl __secondary_hold_acknowledge | |
1105 | __secondary_hold_acknowledge: | |
1106 | .long -1 | |
1107 | #endif | |
1108 | ||
78a235ef KH |
1109 | /* |
1110 | * Create a tlb entry with the same effective and physical address as | |
1111 | * the tlb entry used by the current running code. But set the TS to 1. | |
1112 | * Then switch to the address space 1. It will return with the r3 set to | |
1113 | * the ESEL of the new created tlb. | |
1114 | */ | |
1115 | _GLOBAL(switch_to_as1) | |
1116 | mflr r5 | |
1117 | ||
1118 | /* Find a entry not used */ | |
1119 | mfspr r3,SPRN_TLB1CFG | |
1120 | andi. r3,r3,0xfff | |
1121 | mfspr r4,SPRN_PID | |
1122 | rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */ | |
1123 | mtspr SPRN_MAS6,r4 | |
1124 | 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
1125 | addi r3,r3,-1 | |
1126 | rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
1127 | mtspr SPRN_MAS0,r4 | |
1128 | tlbre | |
1129 | mfspr r4,SPRN_MAS1 | |
1130 | andis. r4,r4,MAS1_VALID@h | |
1131 | bne 1b | |
1132 | ||
1133 | /* Get the tlb entry used by the current running code */ | |
1134 | bl 0f | |
1135 | 0: mflr r4 | |
1136 | tlbsx 0,r4 | |
1137 | ||
1138 | mfspr r4,SPRN_MAS1 | |
1139 | ori r4,r4,MAS1_TS /* Set the TS = 1 */ | |
1140 | mtspr SPRN_MAS1,r4 | |
1141 | ||
1142 | mfspr r4,SPRN_MAS0 | |
1143 | rlwinm r4,r4,0,~MAS0_ESEL_MASK | |
1144 | rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
1145 | mtspr SPRN_MAS0,r4 | |
1146 | tlbwe | |
1147 | isync | |
1148 | sync | |
1149 | ||
1150 | mfmsr r4 | |
1151 | ori r4,r4,MSR_IS | MSR_DS | |
1152 | mtspr SPRN_SRR0,r5 | |
1153 | mtspr SPRN_SRR1,r4 | |
1154 | sync | |
1155 | rfi | |
1156 | ||
1157 | /* | |
1158 | * Restore to the address space 0 and also invalidate the tlb entry created | |
1159 | * by switch_to_as1. | |
7d2471f9 KH |
1160 | * r3 - the tlb entry which should be invalidated |
1161 | * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0) | |
1162 | * r5 - device tree virtual address. If r4 is 0, r5 is ignored. | |
0be7d969 | 1163 | * r6 - boot cpu |
78a235ef KH |
1164 | */ |
1165 | _GLOBAL(restore_to_as0) | |
1166 | mflr r0 | |
1167 | ||
1168 | bl 0f | |
1169 | 0: mflr r9 | |
1170 | addi r9,r9,1f - 0b | |
1171 | ||
7d2471f9 KH |
1172 | /* |
1173 | * We may map the PAGE_OFFSET in AS0 to a different physical address, | |
1174 | * so we need calculate the right jump and device tree address based | |
1175 | * on the offset passed by r4. | |
1176 | */ | |
1177 | add r9,r9,r4 | |
1178 | add r5,r5,r4 | |
0be7d969 | 1179 | add r0,r0,r4 |
7d2471f9 KH |
1180 | |
1181 | 2: mfmsr r7 | |
78a235ef KH |
1182 | li r8,(MSR_IS | MSR_DS) |
1183 | andc r7,r7,r8 | |
1184 | ||
1185 | mtspr SPRN_SRR0,r9 | |
1186 | mtspr SPRN_SRR1,r7 | |
1187 | sync | |
1188 | rfi | |
1189 | ||
1190 | /* Invalidate the temporary tlb entry for AS1 */ | |
1191 | 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
1192 | rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
1193 | mtspr SPRN_MAS0,r9 | |
1194 | tlbre | |
1195 | mfspr r9,SPRN_MAS1 | |
1196 | rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */ | |
1197 | mtspr SPRN_MAS1,r9 | |
1198 | tlbwe | |
1199 | isync | |
7d2471f9 KH |
1200 | |
1201 | cmpwi r4,0 | |
0be7d969 KH |
1202 | cmpwi cr1,r6,0 |
1203 | cror eq,4*cr1+eq,eq | |
1204 | bne 3f /* offset != 0 && is_boot_cpu */ | |
78a235ef KH |
1205 | mtlr r0 |
1206 | blr | |
1207 | ||
7d2471f9 KH |
1208 | /* |
1209 | * The PAGE_OFFSET will map to a different physical address, | |
1210 | * jump to _start to do another relocation again. | |
1211 | */ | |
1212 | 3: mr r3,r5 | |
1213 | bl _start | |
1214 | ||
14cf11af PM |
1215 | /* |
1216 | * We put a few things here that have to be page-aligned. This stuff | |
1217 | * goes at the beginning of the data segment, which is page-aligned. | |
1218 | */ | |
1219 | .data | |
ea703ce2 KG |
1220 | .align 12 |
1221 | .globl sdata | |
1222 | sdata: | |
1223 | .globl empty_zero_page | |
1224 | empty_zero_page: | |
14cf11af | 1225 | .space 4096 |
ea703ce2 KG |
1226 | .globl swapper_pg_dir |
1227 | swapper_pg_dir: | |
bee86f14 | 1228 | .space PGD_TABLE_SIZE |
14cf11af | 1229 | |
14cf11af PM |
1230 | /* |
1231 | * Room for two PTE pointers, usually the kernel and current user pointers | |
1232 | * to their respective root page table. | |
1233 | */ | |
1234 | abatron_pteptrs: | |
1235 | .space 8 |