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5516b540 KG |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
3 | * (based on pci_32.c and pci_64.c) |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
5516b540 KG |
19 | #include <linux/kernel.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/init.h> | |
d92a208d | 23 | #include <linux/delay.h> |
66b15db6 | 24 | #include <linux/export.h> |
22ae782f | 25 | #include <linux/of_address.h> |
04bea68b | 26 | #include <linux/of_pci.h> |
5516b540 KG |
27 | #include <linux/mm.h> |
28 | #include <linux/list.h> | |
29 | #include <linux/syscalls.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
c2e1d845 | 33 | #include <linux/vgaarb.h> |
5516b540 KG |
34 | |
35 | #include <asm/processor.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/prom.h> | |
38 | #include <asm/pci-bridge.h> | |
39 | #include <asm/byteorder.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/ppc-pci.h> | |
8b8da358 | 42 | #include <asm/eeh.h> |
5516b540 | 43 | |
a4c9e328 | 44 | static DEFINE_SPINLOCK(hose_spinlock); |
c3bd517d | 45 | LIST_HEAD(hose_list); |
a4c9e328 KG |
46 | |
47 | /* XXX kill that some day ... */ | |
ebfc00f7 | 48 | static int global_phb_number; /* Global phb counter */ |
a4c9e328 | 49 | |
25e81f92 BH |
50 | /* ISA Memory physical address */ |
51 | resource_size_t isa_mem_base; | |
52 | ||
a4c9e328 | 53 | |
45223c54 | 54 | static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; |
4fc665b8 | 55 | |
45223c54 | 56 | void set_pci_dma_ops(struct dma_map_ops *dma_ops) |
4fc665b8 BB |
57 | { |
58 | pci_dma_ops = dma_ops; | |
59 | } | |
60 | ||
45223c54 | 61 | struct dma_map_ops *get_pci_dma_ops(void) |
4fc665b8 BB |
62 | { |
63 | return pci_dma_ops; | |
64 | } | |
65 | EXPORT_SYMBOL(get_pci_dma_ops); | |
66 | ||
e60516e3 | 67 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
68 | { |
69 | struct pci_controller *phb; | |
70 | ||
e60516e3 | 71 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
72 | if (phb == NULL) |
73 | return NULL; | |
e60516e3 SR |
74 | spin_lock(&hose_spinlock); |
75 | phb->global_number = global_phb_number++; | |
76 | list_add_tail(&phb->list_node, &hose_list); | |
77 | spin_unlock(&hose_spinlock); | |
44ef3390 | 78 | phb->dn = dev; |
f691fa10 | 79 | phb->is_dynamic = slab_is_available(); |
a4c9e328 KG |
80 | #ifdef CONFIG_PPC64 |
81 | if (dev) { | |
82 | int nid = of_node_to_nid(dev); | |
83 | ||
84 | if (nid < 0 || !node_online(nid)) | |
85 | nid = -1; | |
86 | ||
87 | PHB_SET_NODE(phb, nid); | |
88 | } | |
89 | #endif | |
90 | return phb; | |
91 | } | |
5b64d2cc | 92 | EXPORT_SYMBOL_GPL(pcibios_alloc_controller); |
a4c9e328 KG |
93 | |
94 | void pcibios_free_controller(struct pci_controller *phb) | |
95 | { | |
96 | spin_lock(&hose_spinlock); | |
97 | list_del(&phb->list_node); | |
98 | spin_unlock(&hose_spinlock); | |
99 | ||
100 | if (phb->is_dynamic) | |
101 | kfree(phb); | |
102 | } | |
6b8b252f | 103 | EXPORT_SYMBOL_GPL(pcibios_free_controller); |
a4c9e328 | 104 | |
4c2245bb GS |
105 | /* |
106 | * The function is used to return the minimal alignment | |
107 | * for memory or I/O windows of the associated P2P bridge. | |
108 | * By default, 4KiB alignment for I/O windows and 1MiB for | |
109 | * memory windows. | |
110 | */ | |
111 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, | |
112 | unsigned long type) | |
113 | { | |
467efc2e DA |
114 | struct pci_controller *phb = pci_bus_to_host(bus); |
115 | ||
116 | if (phb->controller_ops.window_alignment) | |
117 | return phb->controller_ops.window_alignment(bus, type); | |
118 | ||
119 | /* | |
120 | * PCI core will figure out the default | |
121 | * alignment: 4KiB for I/O and 1MiB for | |
122 | * memory window. | |
123 | */ | |
124 | return 1; | |
4c2245bb GS |
125 | } |
126 | ||
d92a208d GS |
127 | void pcibios_reset_secondary_bus(struct pci_dev *dev) |
128 | { | |
467efc2e DA |
129 | struct pci_controller *phb = pci_bus_to_host(dev->bus); |
130 | ||
131 | if (phb->controller_ops.reset_secondary_bus) { | |
132 | phb->controller_ops.reset_secondary_bus(dev); | |
133 | return; | |
134 | } | |
135 | ||
136 | pci_reset_secondary_bus(dev); | |
d92a208d GS |
137 | } |
138 | ||
5350ab3f WY |
139 | #ifdef CONFIG_PCI_IOV |
140 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) | |
141 | { | |
142 | if (ppc_md.pcibios_iov_resource_alignment) | |
143 | return ppc_md.pcibios_iov_resource_alignment(pdev, resno); | |
144 | ||
145 | return pci_iov_resource_size(pdev, resno); | |
146 | } | |
147 | #endif /* CONFIG_PCI_IOV */ | |
148 | ||
c3bd517d MM |
149 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) |
150 | { | |
151 | #ifdef CONFIG_PPC64 | |
152 | return hose->pci_io_size; | |
153 | #else | |
28f65c11 | 154 | return resource_size(&hose->io_resource); |
c3bd517d MM |
155 | #endif |
156 | } | |
157 | ||
6dfbde20 BH |
158 | int pcibios_vaddr_is_ioport(void __iomem *address) |
159 | { | |
160 | int ret = 0; | |
161 | struct pci_controller *hose; | |
c3bd517d | 162 | resource_size_t size; |
6dfbde20 BH |
163 | |
164 | spin_lock(&hose_spinlock); | |
165 | list_for_each_entry(hose, &hose_list, list_node) { | |
c3bd517d | 166 | size = pcibios_io_size(hose); |
6dfbde20 BH |
167 | if (address >= hose->io_base_virt && |
168 | address < (hose->io_base_virt + size)) { | |
169 | ret = 1; | |
170 | break; | |
171 | } | |
172 | } | |
173 | spin_unlock(&hose_spinlock); | |
174 | return ret; | |
175 | } | |
176 | ||
c3bd517d MM |
177 | unsigned long pci_address_to_pio(phys_addr_t address) |
178 | { | |
179 | struct pci_controller *hose; | |
180 | resource_size_t size; | |
181 | unsigned long ret = ~0; | |
182 | ||
183 | spin_lock(&hose_spinlock); | |
184 | list_for_each_entry(hose, &hose_list, list_node) { | |
185 | size = pcibios_io_size(hose); | |
186 | if (address >= hose->io_base_phys && | |
187 | address < (hose->io_base_phys + size)) { | |
188 | unsigned long base = | |
189 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
190 | ret = base + (address - hose->io_base_phys); | |
191 | break; | |
192 | } | |
193 | } | |
194 | spin_unlock(&hose_spinlock); | |
195 | ||
196 | return ret; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
199 | ||
5516b540 KG |
200 | /* |
201 | * Return the domain number for this bus. | |
202 | */ | |
203 | int pci_domain_nr(struct pci_bus *bus) | |
204 | { | |
6207e816 | 205 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 206 | |
6207e816 | 207 | return hose->global_number; |
5516b540 | 208 | } |
5516b540 | 209 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad | 210 | |
a4c9e328 KG |
211 | /* This routine is meant to be used early during boot, when the |
212 | * PCI bus numbers have not yet been assigned, and you need to | |
213 | * issue PCI config cycles to an OF device. | |
214 | * It could also be used to "fix" RTAS config cycles if you want | |
215 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
216 | * config cycles. | |
217 | */ | |
218 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
219 | { | |
a4c9e328 KG |
220 | while(node) { |
221 | struct pci_controller *hose, *tmp; | |
222 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 223 | if (hose->dn == node) |
a4c9e328 KG |
224 | return hose; |
225 | node = node->parent; | |
226 | } | |
227 | return NULL; | |
228 | } | |
229 | ||
58083dad KG |
230 | /* |
231 | * Reads the interrupt pin to determine if interrupt is use by card. | |
232 | * If the interrupt is used, then gets the interrupt line from the | |
233 | * openfirmware and sets it in the pci_dev and pci_config line. | |
234 | */ | |
4666ca2a | 235 | static int pci_read_irq_line(struct pci_dev *pci_dev) |
58083dad | 236 | { |
530210c7 | 237 | struct of_phandle_args oirq; |
58083dad KG |
238 | unsigned int virq; |
239 | ||
b0494bc8 | 240 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); |
58083dad KG |
241 | |
242 | #ifdef DEBUG | |
243 | memset(&oirq, 0xff, sizeof(oirq)); | |
244 | #endif | |
245 | /* Try to get a mapping from the device-tree */ | |
0c02c800 | 246 | if (of_irq_parse_pci(pci_dev, &oirq)) { |
58083dad KG |
247 | u8 line, pin; |
248 | ||
249 | /* If that fails, lets fallback to what is in the config | |
250 | * space and map that through the default controller. We | |
251 | * also set the type to level low since that's what PCI | |
252 | * interrupts are. If your platform does differently, then | |
253 | * either provide a proper interrupt tree or don't use this | |
254 | * function. | |
255 | */ | |
256 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
257 | return -1; | |
258 | if (pin == 0) | |
259 | return -1; | |
260 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 261 | line == 0xff || line == 0) { |
58083dad KG |
262 | return -1; |
263 | } | |
b0494bc8 BH |
264 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", |
265 | line, pin); | |
58083dad KG |
266 | |
267 | virq = irq_create_mapping(NULL, line); | |
268 | if (virq != NO_IRQ) | |
ec775d0e | 269 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
58083dad | 270 | } else { |
b0494bc8 | 271 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
530210c7 GL |
272 | oirq.args_count, oirq.args[0], oirq.args[1], |
273 | of_node_full_name(oirq.np)); | |
58083dad | 274 | |
e6d30ab1 | 275 | virq = irq_create_of_mapping(&oirq); |
58083dad KG |
276 | } |
277 | if(virq == NO_IRQ) { | |
b0494bc8 | 278 | pr_debug(" Failed to map !\n"); |
58083dad KG |
279 | return -1; |
280 | } | |
281 | ||
b0494bc8 | 282 | pr_debug(" Mapped to linux irq %d\n", virq); |
58083dad KG |
283 | |
284 | pci_dev->irq = virq; | |
285 | ||
286 | return 0; | |
287 | } | |
58083dad KG |
288 | |
289 | /* | |
290 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
291 | * modelled on the sparc64 implementation by Dave Miller. | |
292 | * -- paulus. | |
293 | */ | |
294 | ||
295 | /* | |
296 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
297 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
298 | * | |
299 | * Basically, the user finds the base address for his device which he wishes | |
300 | * to mmap. They read the 32-bit value from the config space base register, | |
301 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
302 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
303 | * | |
304 | * Returns negative error code on failure, zero on success. | |
305 | */ | |
306 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
307 | resource_size_t *offset, | |
308 | enum pci_mmap_state mmap_state) | |
309 | { | |
310 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
311 | unsigned long io_offset = 0; | |
312 | int i, res_bit; | |
313 | ||
b0d436c7 | 314 | if (hose == NULL) |
58083dad KG |
315 | return NULL; /* should never happen */ |
316 | ||
317 | /* If memory, add on the PCI bridge address offset */ | |
318 | if (mmap_state == pci_mmap_mem) { | |
319 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
320 | *offset += hose->pci_mem_offset; | |
321 | #endif | |
322 | res_bit = IORESOURCE_MEM; | |
323 | } else { | |
324 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
325 | *offset += io_offset; | |
326 | res_bit = IORESOURCE_IO; | |
327 | } | |
328 | ||
329 | /* | |
330 | * Check that the offset requested corresponds to one of the | |
331 | * resources of the device. | |
332 | */ | |
333 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
334 | struct resource *rp = &dev->resource[i]; | |
335 | int flags = rp->flags; | |
336 | ||
337 | /* treat ROM as memory (should be already) */ | |
338 | if (i == PCI_ROM_RESOURCE) | |
339 | flags |= IORESOURCE_MEM; | |
340 | ||
341 | /* Active and same type? */ | |
342 | if ((flags & res_bit) == 0) | |
343 | continue; | |
344 | ||
345 | /* In the range of this resource? */ | |
346 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
347 | continue; | |
348 | ||
349 | /* found it! construct the final physical address */ | |
350 | if (mmap_state == pci_mmap_io) | |
351 | *offset += hose->io_base_phys - io_offset; | |
352 | return rp; | |
353 | } | |
354 | ||
355 | return NULL; | |
356 | } | |
357 | ||
358 | /* | |
359 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
360 | * device mapping. | |
361 | */ | |
362 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
363 | pgprot_t protection, | |
364 | enum pci_mmap_state mmap_state, | |
365 | int write_combine) | |
366 | { | |
58083dad KG |
367 | |
368 | /* Write combine is always 0 on non-memory space mappings. On | |
369 | * memory space, if the user didn't pass 1, we check for a | |
370 | * "prefetchable" resource. This is a bit hackish, but we use | |
371 | * this to workaround the inability of /sysfs to provide a write | |
372 | * combine bit | |
373 | */ | |
374 | if (mmap_state != pci_mmap_mem) | |
375 | write_combine = 0; | |
376 | else if (write_combine == 0) { | |
377 | if (rp->flags & IORESOURCE_PREFETCH) | |
378 | write_combine = 1; | |
379 | } | |
380 | ||
381 | /* XXX would be nice to have a way to ask for write-through */ | |
58083dad | 382 | if (write_combine) |
83d5e64b | 383 | return pgprot_noncached_wc(protection); |
58083dad | 384 | else |
83d5e64b | 385 | return pgprot_noncached(protection); |
58083dad KG |
386 | } |
387 | ||
388 | /* | |
389 | * This one is used by /dev/mem and fbdev who have no clue about the | |
390 | * PCI device, it tries to find the PCI device first and calls the | |
391 | * above routine | |
392 | */ | |
393 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
394 | unsigned long pfn, | |
395 | unsigned long size, | |
64b3d0e8 | 396 | pgprot_t prot) |
58083dad KG |
397 | { |
398 | struct pci_dev *pdev = NULL; | |
399 | struct resource *found = NULL; | |
7c12d906 | 400 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
401 | int i; |
402 | ||
403 | if (page_is_ram(pfn)) | |
64b3d0e8 | 404 | return prot; |
58083dad | 405 | |
64b3d0e8 | 406 | prot = pgprot_noncached(prot); |
58083dad KG |
407 | for_each_pci_dev(pdev) { |
408 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
409 | struct resource *rp = &pdev->resource[i]; | |
410 | int flags = rp->flags; | |
411 | ||
412 | /* Active and same type? */ | |
413 | if ((flags & IORESOURCE_MEM) == 0) | |
414 | continue; | |
415 | /* In the range of this resource? */ | |
416 | if (offset < (rp->start & PAGE_MASK) || | |
417 | offset > rp->end) | |
418 | continue; | |
419 | found = rp; | |
420 | break; | |
421 | } | |
422 | if (found) | |
423 | break; | |
424 | } | |
425 | if (found) { | |
426 | if (found->flags & IORESOURCE_PREFETCH) | |
64b3d0e8 | 427 | prot = pgprot_noncached_wc(prot); |
58083dad KG |
428 | pci_dev_put(pdev); |
429 | } | |
430 | ||
b0494bc8 | 431 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
64b3d0e8 | 432 | (unsigned long long)offset, pgprot_val(prot)); |
58083dad | 433 | |
64b3d0e8 | 434 | return prot; |
58083dad KG |
435 | } |
436 | ||
437 | ||
438 | /* | |
439 | * Perform the actual remap of the pages for a PCI device mapping, as | |
440 | * appropriate for this architecture. The region in the process to map | |
441 | * is described by vm_start and vm_end members of VMA, the base physical | |
442 | * address is found in vm_pgoff. | |
443 | * The pci device structure is provided so that architectures may make mapping | |
444 | * decisions on a per-device or per-bus basis. | |
445 | * | |
446 | * Returns a negative error code on failure, zero on success. | |
447 | */ | |
448 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
449 | enum pci_mmap_state mmap_state, int write_combine) | |
450 | { | |
7c12d906 BH |
451 | resource_size_t offset = |
452 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
58083dad KG |
453 | struct resource *rp; |
454 | int ret; | |
455 | ||
456 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
457 | if (rp == NULL) | |
458 | return -EINVAL; | |
459 | ||
460 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
461 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
462 | vma->vm_page_prot, | |
463 | mmap_state, write_combine); | |
464 | ||
465 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
466 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
467 | ||
468 | return ret; | |
469 | } | |
470 | ||
e9f82cb7 BH |
471 | /* This provides legacy IO read access on a bus */ |
472 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
473 | { | |
474 | unsigned long offset; | |
475 | struct pci_controller *hose = pci_bus_to_host(bus); | |
476 | struct resource *rp = &hose->io_resource; | |
477 | void __iomem *addr; | |
478 | ||
479 | /* Check if port can be supported by that bus. We only check | |
480 | * the ranges of the PHB though, not the bus itself as the rules | |
481 | * for forwarding legacy cycles down bridges are not our problem | |
482 | * here. So if the host bridge supports it, we do it. | |
483 | */ | |
484 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
485 | offset += port; | |
486 | ||
487 | if (!(rp->flags & IORESOURCE_IO)) | |
488 | return -ENXIO; | |
489 | if (offset < rp->start || (offset + size) > rp->end) | |
490 | return -ENXIO; | |
491 | addr = hose->io_base_virt + port; | |
492 | ||
493 | switch(size) { | |
494 | case 1: | |
495 | *((u8 *)val) = in_8(addr); | |
496 | return 1; | |
497 | case 2: | |
498 | if (port & 1) | |
499 | return -EINVAL; | |
500 | *((u16 *)val) = in_le16(addr); | |
501 | return 2; | |
502 | case 4: | |
503 | if (port & 3) | |
504 | return -EINVAL; | |
505 | *((u32 *)val) = in_le32(addr); | |
506 | return 4; | |
507 | } | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
511 | /* This provides legacy IO write access on a bus */ | |
512 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
513 | { | |
514 | unsigned long offset; | |
515 | struct pci_controller *hose = pci_bus_to_host(bus); | |
516 | struct resource *rp = &hose->io_resource; | |
517 | void __iomem *addr; | |
518 | ||
519 | /* Check if port can be supported by that bus. We only check | |
520 | * the ranges of the PHB though, not the bus itself as the rules | |
521 | * for forwarding legacy cycles down bridges are not our problem | |
522 | * here. So if the host bridge supports it, we do it. | |
523 | */ | |
524 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
525 | offset += port; | |
526 | ||
527 | if (!(rp->flags & IORESOURCE_IO)) | |
528 | return -ENXIO; | |
529 | if (offset < rp->start || (offset + size) > rp->end) | |
530 | return -ENXIO; | |
531 | addr = hose->io_base_virt + port; | |
532 | ||
533 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
534 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
535 | * as a u32, which means that we have to correct the location of | |
536 | * the data read within those 32 bits for size 1 and 2 | |
537 | */ | |
538 | switch(size) { | |
539 | case 1: | |
540 | out_8(addr, val >> 24); | |
541 | return 1; | |
542 | case 2: | |
543 | if (port & 1) | |
544 | return -EINVAL; | |
545 | out_le16(addr, val >> 16); | |
546 | return 2; | |
547 | case 4: | |
548 | if (port & 3) | |
549 | return -EINVAL; | |
550 | out_le32(addr, val); | |
551 | return 4; | |
552 | } | |
553 | return -EINVAL; | |
554 | } | |
555 | ||
556 | /* This provides legacy IO or memory mmap access on a bus */ | |
557 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
558 | struct vm_area_struct *vma, | |
559 | enum pci_mmap_state mmap_state) | |
560 | { | |
561 | struct pci_controller *hose = pci_bus_to_host(bus); | |
562 | resource_size_t offset = | |
563 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
564 | resource_size_t size = vma->vm_end - vma->vm_start; | |
565 | struct resource *rp; | |
566 | ||
567 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
568 | pci_domain_nr(bus), bus->number, | |
569 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
570 | (unsigned long long)offset, | |
571 | (unsigned long long)(offset + size - 1)); | |
572 | ||
573 | if (mmap_state == pci_mmap_mem) { | |
5b11abfd BH |
574 | /* Hack alert ! |
575 | * | |
576 | * Because X is lame and can fail starting if it gets an error trying | |
577 | * to mmap legacy_mem (instead of just moving on without legacy memory | |
578 | * access) we fake it here by giving it anonymous memory, effectively | |
579 | * behaving just like /dev/zero | |
580 | */ | |
581 | if ((offset + size) > hose->isa_mem_size) { | |
582 | printk(KERN_DEBUG | |
583 | "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", | |
584 | current->comm, current->pid, pci_domain_nr(bus), bus->number); | |
585 | if (vma->vm_flags & VM_SHARED) | |
586 | return shmem_zero_setup(vma); | |
587 | return 0; | |
588 | } | |
e9f82cb7 BH |
589 | offset += hose->isa_mem_phys; |
590 | } else { | |
591 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
592 | unsigned long roffset = offset + io_offset; | |
593 | rp = &hose->io_resource; | |
594 | if (!(rp->flags & IORESOURCE_IO)) | |
595 | return -ENXIO; | |
596 | if (roffset < rp->start || (roffset + size) > rp->end) | |
597 | return -ENXIO; | |
598 | offset += hose->io_base_phys; | |
599 | } | |
600 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
601 | ||
602 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
64b3d0e8 | 603 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
e9f82cb7 BH |
604 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
605 | vma->vm_end - vma->vm_start, | |
606 | vma->vm_page_prot); | |
607 | } | |
608 | ||
58083dad KG |
609 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
610 | const struct resource *rsrc, | |
611 | resource_size_t *start, resource_size_t *end) | |
612 | { | |
613 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
614 | resource_size_t offset = 0; | |
615 | ||
616 | if (hose == NULL) | |
617 | return; | |
618 | ||
619 | if (rsrc->flags & IORESOURCE_IO) | |
620 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
621 | ||
622 | /* We pass a fully fixed up address to userland for MMIO instead of | |
623 | * a BAR value because X is lame and expects to be able to use that | |
624 | * to pass to /dev/mem ! | |
625 | * | |
626 | * That means that we'll have potentially 64 bits values where some | |
627 | * userland apps only expect 32 (like X itself since it thinks only | |
628 | * Sparc has 64 bits MMIO) but if we don't do that, we break it on | |
629 | * 32 bits CHRPs :-( | |
630 | * | |
631 | * Hopefully, the sysfs insterface is immune to that gunk. Once X | |
632 | * has been fixed (and the fix spread enough), we can re-enable the | |
633 | * 2 lines below and pass down a BAR value to userland. In that case | |
634 | * we'll also have to re-enable the matching code in | |
635 | * __pci_mmap_make_offset(). | |
636 | * | |
637 | * BenH. | |
638 | */ | |
639 | #if 0 | |
640 | else if (rsrc->flags & IORESOURCE_MEM) | |
641 | offset = hose->pci_mem_offset; | |
642 | #endif | |
643 | ||
644 | *start = rsrc->start - offset; | |
645 | *end = rsrc->end - offset; | |
646 | } | |
13dccb9e BH |
647 | |
648 | /** | |
649 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
650 | * @hose: newly allocated pci_controller to be setup | |
651 | * @dev: device node of the host bridge | |
652 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
653 | * | |
654 | * This function will parse the "ranges" property of a PCI host bridge device | |
655 | * node and setup the resource mapping of a pci controller based on its | |
656 | * content. | |
657 | * | |
658 | * Life would be boring if it wasn't for a few issues that we have to deal | |
659 | * with here: | |
660 | * | |
661 | * - We can only cope with one IO space range and up to 3 Memory space | |
662 | * ranges. However, some machines (thanks Apple !) tend to split their | |
663 | * space into lots of small contiguous ranges. So we have to coalesce. | |
664 | * | |
13dccb9e BH |
665 | * - Some busses have IO space not starting at 0, which causes trouble with |
666 | * the way we do our IO resource renumbering. The code somewhat deals with | |
667 | * it for 64 bits but I would expect problems on 32 bits. | |
668 | * | |
669 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
670 | * 32 bits so we need to use 64 bits values for the parsing | |
671 | */ | |
cad5cef6 GKH |
672 | void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
673 | struct device_node *dev, int primary) | |
13dccb9e | 674 | { |
858957ab | 675 | int memno = 0; |
13dccb9e | 676 | struct resource *res; |
654837e8 AM |
677 | struct of_pci_range range; |
678 | struct of_pci_range_parser parser; | |
13dccb9e BH |
679 | |
680 | printk(KERN_INFO "PCI host bridge %s %s ranges:\n", | |
681 | dev->full_name, primary ? "(primary)" : ""); | |
682 | ||
654837e8 AM |
683 | /* Check for ranges property */ |
684 | if (of_pci_range_parser_init(&parser, dev)) | |
13dccb9e BH |
685 | return; |
686 | ||
687 | /* Parse it */ | |
654837e8 | 688 | for_each_of_pci_range(&parser, &range) { |
e9f82cb7 BH |
689 | /* If we failed translation or got a zero-sized region |
690 | * (some FW try to feed us with non sensical zero sized regions | |
691 | * such as power3 which look like some kind of attempt at exposing | |
692 | * the VGA memory hole) | |
693 | */ | |
654837e8 | 694 | if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) |
13dccb9e BH |
695 | continue; |
696 | ||
13dccb9e BH |
697 | /* Act based on address space type */ |
698 | res = NULL; | |
654837e8 AM |
699 | switch (range.flags & IORESOURCE_TYPE_BITS) { |
700 | case IORESOURCE_IO: | |
13dccb9e BH |
701 | printk(KERN_INFO |
702 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
654837e8 AM |
703 | range.cpu_addr, range.cpu_addr + range.size - 1, |
704 | range.pci_addr); | |
13dccb9e BH |
705 | |
706 | /* We support only one IO range */ | |
707 | if (hose->pci_io_size) { | |
708 | printk(KERN_INFO | |
709 | " \\--> Skipped (too many) !\n"); | |
710 | continue; | |
711 | } | |
712 | #ifdef CONFIG_PPC32 | |
713 | /* On 32 bits, limit I/O space to 16MB */ | |
654837e8 AM |
714 | if (range.size > 0x01000000) |
715 | range.size = 0x01000000; | |
13dccb9e BH |
716 | |
717 | /* 32 bits needs to map IOs here */ | |
654837e8 AM |
718 | hose->io_base_virt = ioremap(range.cpu_addr, |
719 | range.size); | |
13dccb9e BH |
720 | |
721 | /* Expect trouble if pci_addr is not 0 */ | |
722 | if (primary) | |
723 | isa_io_base = | |
724 | (unsigned long)hose->io_base_virt; | |
725 | #endif /* CONFIG_PPC32 */ | |
726 | /* pci_io_size and io_base_phys always represent IO | |
727 | * space starting at 0 so we factor in pci_addr | |
728 | */ | |
654837e8 AM |
729 | hose->pci_io_size = range.pci_addr + range.size; |
730 | hose->io_base_phys = range.cpu_addr - range.pci_addr; | |
13dccb9e BH |
731 | |
732 | /* Build resource */ | |
733 | res = &hose->io_resource; | |
654837e8 | 734 | range.cpu_addr = range.pci_addr; |
13dccb9e | 735 | break; |
654837e8 | 736 | case IORESOURCE_MEM: |
13dccb9e BH |
737 | printk(KERN_INFO |
738 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
654837e8 AM |
739 | range.cpu_addr, range.cpu_addr + range.size - 1, |
740 | range.pci_addr, | |
741 | (range.pci_space & 0x40000000) ? | |
742 | "Prefetch" : ""); | |
13dccb9e BH |
743 | |
744 | /* We support only 3 memory ranges */ | |
745 | if (memno >= 3) { | |
746 | printk(KERN_INFO | |
747 | " \\--> Skipped (too many) !\n"); | |
748 | continue; | |
749 | } | |
750 | /* Handles ISA memory hole space here */ | |
654837e8 | 751 | if (range.pci_addr == 0) { |
13dccb9e | 752 | if (primary || isa_mem_base == 0) |
654837e8 AM |
753 | isa_mem_base = range.cpu_addr; |
754 | hose->isa_mem_phys = range.cpu_addr; | |
755 | hose->isa_mem_size = range.size; | |
13dccb9e BH |
756 | } |
757 | ||
13dccb9e | 758 | /* Build resource */ |
654837e8 AM |
759 | hose->mem_offset[memno] = range.cpu_addr - |
760 | range.pci_addr; | |
13dccb9e | 761 | res = &hose->mem_resources[memno++]; |
13dccb9e BH |
762 | break; |
763 | } | |
764 | if (res != NULL) { | |
aeba3731 ME |
765 | res->name = dev->full_name; |
766 | res->flags = range.flags; | |
767 | res->start = range.cpu_addr; | |
768 | res->end = range.cpu_addr + range.size - 1; | |
769 | res->parent = res->child = res->sibling = NULL; | |
13dccb9e BH |
770 | } |
771 | } | |
13dccb9e | 772 | } |
fa462f2d BH |
773 | |
774 | /* Decide whether to display the domain number in /proc */ | |
775 | int pci_proc_domain(struct pci_bus *bus) | |
776 | { | |
777 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1fd0f525 | 778 | |
0e47ff1c | 779 | if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) |
fa462f2d | 780 | return 0; |
0e47ff1c | 781 | if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) |
fa462f2d BH |
782 | return hose->global_number != 0; |
783 | return 1; | |
fa462f2d BH |
784 | } |
785 | ||
d82fb31a KSS |
786 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
787 | { | |
788 | if (ppc_md.pcibios_root_bridge_prepare) | |
789 | return ppc_md.pcibios_root_bridge_prepare(bridge); | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
bf5e2ba2 BH |
794 | /* This header fixup will do the resource fixup for all devices as they are |
795 | * probed, but not for bridge ranges | |
796 | */ | |
cad5cef6 | 797 | static void pcibios_fixup_resources(struct pci_dev *dev) |
bf5e2ba2 BH |
798 | { |
799 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
800 | int i; | |
801 | ||
802 | if (!hose) { | |
803 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
804 | pci_name(dev)); | |
805 | return; | |
806 | } | |
c3b80fb0 WY |
807 | |
808 | if (dev->is_virtfn) | |
809 | return; | |
810 | ||
bf5e2ba2 BH |
811 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
812 | struct resource *res = dev->resource + i; | |
c5df457f | 813 | struct pci_bus_region reg; |
bf5e2ba2 BH |
814 | if (!res->flags) |
815 | continue; | |
48c2ce97 BH |
816 | |
817 | /* If we're going to re-assign everything, we mark all resources | |
818 | * as unset (and 0-base them). In addition, we mark BARs starting | |
819 | * at 0 as unset as well, except if PCI_PROBE_ONLY is also set | |
820 | * since in that case, we don't want to re-assign anything | |
7f172890 | 821 | */ |
fc279850 | 822 | pcibios_resource_to_bus(dev->bus, ®, res); |
48c2ce97 | 823 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || |
c5df457f | 824 | (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { |
48c2ce97 BH |
825 | /* Only print message if not re-assigning */ |
826 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) | |
ae2a84b4 KH |
827 | pr_debug("PCI:%s Resource %d %pR is unassigned\n", |
828 | pci_name(dev), i, res); | |
bf5e2ba2 BH |
829 | res->end -= res->start; |
830 | res->start = 0; | |
831 | res->flags |= IORESOURCE_UNSET; | |
832 | continue; | |
833 | } | |
834 | ||
ae2a84b4 | 835 | pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res); |
bf5e2ba2 BH |
836 | } |
837 | ||
838 | /* Call machine specific resource fixup */ | |
839 | if (ppc_md.pcibios_fixup_resources) | |
840 | ppc_md.pcibios_fixup_resources(dev); | |
841 | } | |
842 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
843 | ||
b5561511 BH |
844 | /* This function tries to figure out if a bridge resource has been initialized |
845 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
846 | * things go more smoothly when it gets it right. It should covers cases such | |
847 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
848 | */ | |
cad5cef6 GKH |
849 | static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, |
850 | struct resource *res) | |
bf5e2ba2 | 851 | { |
be8cbcd8 | 852 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 853 | struct pci_dev *dev = bus->self; |
b5561511 | 854 | resource_size_t offset; |
3fd47f06 | 855 | struct pci_bus_region region; |
b5561511 BH |
856 | u16 command; |
857 | int i; | |
bf5e2ba2 | 858 | |
b5561511 | 859 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
0e47ff1c | 860 | if (pci_has_flag(PCI_PROBE_ONLY)) |
b5561511 | 861 | return 0; |
bf5e2ba2 | 862 | |
b5561511 BH |
863 | /* Job is a bit different between memory and IO */ |
864 | if (res->flags & IORESOURCE_MEM) { | |
fc279850 | 865 | pcibios_resource_to_bus(dev->bus, ®ion, res); |
3fd47f06 BH |
866 | |
867 | /* If the BAR is non-0 then it's probably been initialized */ | |
868 | if (region.start != 0) | |
b5561511 | 869 | return 0; |
bf5e2ba2 | 870 | |
b5561511 BH |
871 | /* The BAR is 0, let's check if memory decoding is enabled on |
872 | * the bridge. If not, we consider it unassigned | |
873 | */ | |
874 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
875 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
876 | return 1; | |
be8cbcd8 | 877 | |
b5561511 BH |
878 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
879 | * resources covers that starting address (0 then it's good enough for | |
3fd47f06 | 880 | * us for memory space) |
b5561511 BH |
881 | */ |
882 | for (i = 0; i < 3; i++) { | |
883 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
3fd47f06 | 884 | hose->mem_resources[i].start == hose->mem_offset[i]) |
b5561511 BH |
885 | return 0; |
886 | } | |
887 | ||
888 | /* Well, it starts at 0 and we know it will collide so we may as | |
889 | * well consider it as unassigned. That covers the Apple case. | |
890 | */ | |
891 | return 1; | |
892 | } else { | |
893 | /* If the BAR is non-0, then we consider it assigned */ | |
894 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
895 | if (((res->start - offset) & 0xfffffffful) != 0) | |
896 | return 0; | |
897 | ||
898 | /* Here, we are a bit different than memory as typically IO space | |
899 | * starting at low addresses -is- valid. What we do instead if that | |
900 | * we consider as unassigned anything that doesn't have IO enabled | |
901 | * in the PCI command register, and that's it. | |
902 | */ | |
903 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
904 | if (command & PCI_COMMAND_IO) | |
905 | return 0; | |
906 | ||
907 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
908 | * it unassigned | |
909 | */ | |
910 | return 1; | |
911 | } | |
912 | } | |
913 | ||
914 | /* Fixup resources of a PCI<->PCI bridge */ | |
cad5cef6 | 915 | static void pcibios_fixup_bridge(struct pci_bus *bus) |
b5561511 BH |
916 | { |
917 | struct resource *res; | |
918 | int i; | |
919 | ||
920 | struct pci_dev *dev = bus->self; | |
921 | ||
89a74ecc BH |
922 | pci_bus_for_each_resource(bus, res, i) { |
923 | if (!res || !res->flags) | |
b5561511 BH |
924 | continue; |
925 | if (i >= 3 && bus->self->transparent) | |
926 | continue; | |
927 | ||
cf1a4cf8 GS |
928 | /* If we're going to reassign everything, we can |
929 | * shrink the P2P resource to have size as being | |
930 | * of 0 in order to save space. | |
48c2ce97 BH |
931 | */ |
932 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { | |
933 | res->flags |= IORESOURCE_UNSET; | |
48c2ce97 | 934 | res->start = 0; |
cf1a4cf8 | 935 | res->end = -1; |
48c2ce97 BH |
936 | continue; |
937 | } | |
938 | ||
ae2a84b4 | 939 | pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); |
bf5e2ba2 | 940 | |
b5561511 BH |
941 | /* Try to detect uninitialized P2P bridge resources, |
942 | * and clear them out so they get re-assigned later | |
943 | */ | |
944 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
945 | res->flags = 0; | |
946 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
bf5e2ba2 BH |
947 | } |
948 | } | |
b5561511 BH |
949 | } |
950 | ||
cad5cef6 | 951 | void pcibios_setup_bus_self(struct pci_bus *bus) |
8b8da358 | 952 | { |
467efc2e DA |
953 | struct pci_controller *phb; |
954 | ||
7eef440a | 955 | /* Fix up the bus resources for P2P bridges */ |
8b8da358 BH |
956 | if (bus->self != NULL) |
957 | pcibios_fixup_bridge(bus); | |
958 | ||
959 | /* Platform specific bus fixups. This is currently only used | |
7eef440a | 960 | * by fsl_pci and I'm hoping to get rid of it at some point |
8b8da358 BH |
961 | */ |
962 | if (ppc_md.pcibios_fixup_bus) | |
963 | ppc_md.pcibios_fixup_bus(bus); | |
964 | ||
965 | /* Setup bus DMA mappings */ | |
467efc2e DA |
966 | phb = pci_bus_to_host(bus); |
967 | if (phb->controller_ops.dma_bus_setup) | |
968 | phb->controller_ops.dma_bus_setup(bus); | |
8b8da358 BH |
969 | } |
970 | ||
7846de40 | 971 | static void pcibios_setup_device(struct pci_dev *dev) |
37f02195 | 972 | { |
467efc2e | 973 | struct pci_controller *phb; |
37f02195 YC |
974 | /* Fixup NUMA node as it may not be setup yet by the generic |
975 | * code and is needed by the DMA init | |
976 | */ | |
977 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
978 | ||
979 | /* Hook up default DMA ops */ | |
980 | set_dma_ops(&dev->dev, pci_dma_ops); | |
981 | set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); | |
982 | ||
983 | /* Additional platform DMA/iommu setup */ | |
467efc2e DA |
984 | phb = pci_bus_to_host(dev->bus); |
985 | if (phb->controller_ops.dma_dev_setup) | |
986 | phb->controller_ops.dma_dev_setup(dev); | |
37f02195 YC |
987 | |
988 | /* Read default IRQs and fixup if necessary */ | |
989 | pci_read_irq_line(dev); | |
990 | if (ppc_md.pci_irq_fixup) | |
991 | ppc_md.pci_irq_fixup(dev); | |
992 | } | |
993 | ||
7846de40 GR |
994 | int pcibios_add_device(struct pci_dev *dev) |
995 | { | |
996 | /* | |
997 | * We can only call pcibios_setup_device() after bus setup is complete, | |
998 | * since some of the platform specific DMA setup code depends on it. | |
999 | */ | |
1000 | if (dev->bus->is_added) | |
1001 | pcibios_setup_device(dev); | |
6e628c7d WY |
1002 | |
1003 | #ifdef CONFIG_PCI_IOV | |
1004 | if (ppc_md.pcibios_fixup_sriov) | |
1005 | ppc_md.pcibios_fixup_sriov(dev); | |
1006 | #endif /* CONFIG_PCI_IOV */ | |
1007 | ||
7846de40 GR |
1008 | return 0; |
1009 | } | |
1010 | ||
cad5cef6 | 1011 | void pcibios_setup_bus_devices(struct pci_bus *bus) |
7eef440a BH |
1012 | { |
1013 | struct pci_dev *dev; | |
1014 | ||
1015 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
1016 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
1017 | ||
1018 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
2d1c8618 BH |
1019 | /* Cardbus can call us to add new devices to a bus, so ignore |
1020 | * those who are already fully discovered | |
1021 | */ | |
1022 | if (dev->is_added) | |
1023 | continue; | |
1024 | ||
37f02195 | 1025 | pcibios_setup_device(dev); |
7eef440a BH |
1026 | } |
1027 | } | |
1028 | ||
79c8be83 MS |
1029 | void pcibios_set_master(struct pci_dev *dev) |
1030 | { | |
1031 | /* No special bus mastering setup handling */ | |
1032 | } | |
1033 | ||
cad5cef6 | 1034 | void pcibios_fixup_bus(struct pci_bus *bus) |
bf5e2ba2 | 1035 | { |
237865f1 BH |
1036 | /* When called from the generic PCI probe, read PCI<->PCI bridge |
1037 | * bases. This is -not- called when generating the PCI tree from | |
1038 | * the OF device-tree. | |
1039 | */ | |
1040 | pci_read_bridge_bases(bus); | |
1041 | ||
1042 | /* Now fixup the bus bus */ | |
8b8da358 BH |
1043 | pcibios_setup_bus_self(bus); |
1044 | ||
1045 | /* Now fixup devices on that bus */ | |
1046 | pcibios_setup_bus_devices(bus); | |
bf5e2ba2 | 1047 | } |
8b8da358 | 1048 | EXPORT_SYMBOL(pcibios_fixup_bus); |
3fd94c6b | 1049 | |
cad5cef6 | 1050 | void pci_fixup_cardbus(struct pci_bus *bus) |
2d1c8618 BH |
1051 | { |
1052 | /* Now fixup devices on that bus */ | |
1053 | pcibios_setup_bus_devices(bus); | |
1054 | } | |
1055 | ||
1056 | ||
3fd94c6b BH |
1057 | static int skip_isa_ioresource_align(struct pci_dev *dev) |
1058 | { | |
0e47ff1c | 1059 | if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && |
3fd94c6b BH |
1060 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) |
1061 | return 1; | |
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | /* | |
1066 | * We need to avoid collisions with `mirrored' VGA ports | |
1067 | * and other strange ISA hardware, so we always want the | |
1068 | * addresses to be allocated in the 0x000-0x0ff region | |
1069 | * modulo 0x400. | |
1070 | * | |
1071 | * Why? Because some silly external IO cards only decode | |
1072 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1073 | * is reserved for motherboard devices that decode all 16 | |
1074 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1075 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1076 | * which might have be mirrored at 0x0100-0x03ff.. | |
1077 | */ | |
3b7a17fc | 1078 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
3fd94c6b BH |
1079 | resource_size_t size, resource_size_t align) |
1080 | { | |
1081 | struct pci_dev *dev = data; | |
b26b2d49 | 1082 | resource_size_t start = res->start; |
3fd94c6b BH |
1083 | |
1084 | if (res->flags & IORESOURCE_IO) { | |
3fd94c6b | 1085 | if (skip_isa_ioresource_align(dev)) |
b26b2d49 DB |
1086 | return start; |
1087 | if (start & 0x300) | |
3fd94c6b | 1088 | start = (start + 0x3ff) & ~0x3ff; |
3fd94c6b | 1089 | } |
b26b2d49 DB |
1090 | |
1091 | return start; | |
3fd94c6b BH |
1092 | } |
1093 | EXPORT_SYMBOL(pcibios_align_resource); | |
1094 | ||
1095 | /* | |
1096 | * Reparent resource children of pr that conflict with res | |
1097 | * under res, and make res replace those children. | |
1098 | */ | |
0f6023d5 | 1099 | static int reparent_resources(struct resource *parent, |
3fd94c6b BH |
1100 | struct resource *res) |
1101 | { | |
1102 | struct resource *p, **pp; | |
1103 | struct resource **firstpp = NULL; | |
1104 | ||
1105 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1106 | if (p->end < res->start) | |
1107 | continue; | |
1108 | if (res->end < p->start) | |
1109 | break; | |
1110 | if (p->start < res->start || p->end > res->end) | |
1111 | return -1; /* not completely contained */ | |
1112 | if (firstpp == NULL) | |
1113 | firstpp = pp; | |
1114 | } | |
1115 | if (firstpp == NULL) | |
1116 | return -1; /* didn't find any conflicting entries? */ | |
1117 | res->parent = parent; | |
1118 | res->child = *firstpp; | |
1119 | res->sibling = *pp; | |
1120 | *firstpp = res; | |
1121 | *pp = NULL; | |
1122 | for (p = res->child; p != NULL; p = p->sibling) { | |
1123 | p->parent = res; | |
ae2a84b4 KH |
1124 | pr_debug("PCI: Reparented %s %pR under %s\n", |
1125 | p->name, p, res->name); | |
3fd94c6b BH |
1126 | } |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * Handle resources of PCI devices. If the world were perfect, we could | |
1132 | * just allocate all the resource regions and do nothing more. It isn't. | |
1133 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1134 | * require us to know lots of host bridge internals. So we attempt to | |
1135 | * keep as much of the original configuration as possible, but tweak it | |
1136 | * when it's found to be wrong. | |
1137 | * | |
1138 | * Known BIOS problems we have to work around: | |
1139 | * - I/O or memory regions not configured | |
1140 | * - regions configured, but not enabled in the command register | |
1141 | * - bogus I/O addresses above 64K used | |
1142 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1143 | * the fact the PCI specs explicitly allow address decoders to be | |
1144 | * shared between expansion ROMs and other resource regions, it's | |
1145 | * at least dangerous) | |
1146 | * | |
1147 | * Our solution: | |
1148 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1149 | * This gives us fixed barriers on where we can allocate. | |
1150 | * (2) Allocate resources for all enabled devices. If there is | |
1151 | * a collision, just mark the resource as unallocated. Also | |
1152 | * disable expansion ROMs during this step. | |
1153 | * (3) Try to allocate resources for disabled devices. If the | |
1154 | * resources were assigned correctly, everything goes well, | |
1155 | * if they weren't, they won't disturb allocation of other | |
1156 | * resources. | |
1157 | * (4) Assign new addresses to resources which were either | |
1158 | * not configured at all or misconfigured. If explicitly | |
1159 | * requested by the user, configure expansion ROM address | |
1160 | * as well. | |
1161 | */ | |
1162 | ||
e51df2c1 | 1163 | static void pcibios_allocate_bus_resources(struct pci_bus *bus) |
3fd94c6b | 1164 | { |
e90a1318 | 1165 | struct pci_bus *b; |
3fd94c6b BH |
1166 | int i; |
1167 | struct resource *res, *pr; | |
1168 | ||
b5ae5f91 BH |
1169 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
1170 | pci_domain_nr(bus), bus->number); | |
1171 | ||
89a74ecc BH |
1172 | pci_bus_for_each_resource(bus, res, i) { |
1173 | if (!res || !res->flags || res->start > res->end || res->parent) | |
e90a1318 | 1174 | continue; |
48c2ce97 BH |
1175 | |
1176 | /* If the resource was left unset at this point, we clear it */ | |
1177 | if (res->flags & IORESOURCE_UNSET) | |
1178 | goto clear_resource; | |
1179 | ||
e90a1318 NF |
1180 | if (bus->parent == NULL) |
1181 | pr = (res->flags & IORESOURCE_IO) ? | |
1182 | &ioport_resource : &iomem_resource; | |
1183 | else { | |
e90a1318 NF |
1184 | pr = pci_find_parent_resource(bus->self, res); |
1185 | if (pr == res) { | |
1186 | /* this happens when the generic PCI | |
1187 | * code (wrongly) decides that this | |
1188 | * bridge is transparent -- paulus | |
3fd94c6b | 1189 | */ |
e90a1318 | 1190 | continue; |
3fd94c6b | 1191 | } |
e90a1318 | 1192 | } |
3fd94c6b | 1193 | |
ae2a84b4 KH |
1194 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", |
1195 | bus->self ? pci_name(bus->self) : "PHB", bus->number, | |
1196 | i, res, pr, (pr && pr->name) ? pr->name : "nil"); | |
e90a1318 NF |
1197 | |
1198 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
3ebfe46a YL |
1199 | struct pci_dev *dev = bus->self; |
1200 | ||
e90a1318 NF |
1201 | if (request_resource(pr, res) == 0) |
1202 | continue; | |
1203 | /* | |
1204 | * Must be a conflict with an existing entry. | |
1205 | * Move that entry (or entries) under the | |
1206 | * bridge resource and try again. | |
1207 | */ | |
1208 | if (reparent_resources(pr, res) == 0) | |
1209 | continue; | |
3ebfe46a YL |
1210 | |
1211 | if (dev && i < PCI_BRIDGE_RESOURCE_NUM && | |
1212 | pci_claim_bridge_resource(dev, | |
1213 | i + PCI_BRIDGE_RESOURCES) == 0) | |
1214 | continue; | |
3fd94c6b | 1215 | } |
48c2ce97 BH |
1216 | pr_warning("PCI: Cannot allocate resource region " |
1217 | "%d of PCI bridge %d, will remap\n", i, bus->number); | |
1218 | clear_resource: | |
cf1a4cf8 GS |
1219 | /* The resource might be figured out when doing |
1220 | * reassignment based on the resources required | |
1221 | * by the downstream PCI devices. Here we set | |
1222 | * the size of the resource to be 0 in order to | |
1223 | * save more space. | |
1224 | */ | |
1225 | res->start = 0; | |
1226 | res->end = -1; | |
e90a1318 | 1227 | res->flags = 0; |
3fd94c6b | 1228 | } |
e90a1318 NF |
1229 | |
1230 | list_for_each_entry(b, &bus->children, node) | |
1231 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1232 | } |
1233 | ||
cad5cef6 | 1234 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1235 | { |
1236 | struct resource *pr, *r = &dev->resource[idx]; | |
1237 | ||
ae2a84b4 KH |
1238 | pr_debug("PCI: Allocating %s: Resource %d: %pR\n", |
1239 | pci_name(dev), idx, r); | |
3fd94c6b BH |
1240 | |
1241 | pr = pci_find_parent_resource(dev, r); | |
1242 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1243 | request_resource(pr, r) < 0) { | |
1244 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1245 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1246 | if (pr) | |
ae2a84b4 | 1247 | pr_debug("PCI: parent is %p: %pR\n", pr, pr); |
3fd94c6b BH |
1248 | /* We'll assign a new address later */ |
1249 | r->flags |= IORESOURCE_UNSET; | |
1250 | r->end -= r->start; | |
1251 | r->start = 0; | |
1252 | } | |
1253 | } | |
1254 | ||
1255 | static void __init pcibios_allocate_resources(int pass) | |
1256 | { | |
1257 | struct pci_dev *dev = NULL; | |
1258 | int idx, disabled; | |
1259 | u16 command; | |
1260 | struct resource *r; | |
1261 | ||
1262 | for_each_pci_dev(dev) { | |
1263 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
ad892a63 | 1264 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { |
3fd94c6b BH |
1265 | r = &dev->resource[idx]; |
1266 | if (r->parent) /* Already allocated */ | |
1267 | continue; | |
1268 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1269 | continue; /* Not assigned at all */ | |
ad892a63 BH |
1270 | /* We only allocate ROMs on pass 1 just in case they |
1271 | * have been screwed up by firmware | |
1272 | */ | |
1273 | if (idx == PCI_ROM_RESOURCE ) | |
1274 | disabled = 1; | |
3fd94c6b BH |
1275 | if (r->flags & IORESOURCE_IO) |
1276 | disabled = !(command & PCI_COMMAND_IO); | |
1277 | else | |
1278 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1279 | if (pass == disabled) |
1280 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1281 | } |
1282 | if (pass) | |
1283 | continue; | |
1284 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
ad892a63 | 1285 | if (r->flags) { |
3fd94c6b BH |
1286 | /* Turn the ROM off, leave the resource region, |
1287 | * but keep it unregistered. | |
1288 | */ | |
1289 | u32 reg; | |
3fd94c6b | 1290 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
ad892a63 BH |
1291 | if (reg & PCI_ROM_ADDRESS_ENABLE) { |
1292 | pr_debug("PCI: Switching off ROM of %s\n", | |
1293 | pci_name(dev)); | |
1294 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1295 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1296 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1297 | } | |
3fd94c6b BH |
1298 | } |
1299 | } | |
1300 | } | |
1301 | ||
c1f34302 BH |
1302 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) |
1303 | { | |
1304 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1305 | resource_size_t offset; | |
1306 | struct resource *res, *pres; | |
1307 | int i; | |
1308 | ||
1309 | pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); | |
1310 | ||
1311 | /* Check for IO */ | |
1312 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1313 | goto no_io; | |
1314 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1315 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1316 | BUG_ON(res == NULL); | |
1317 | res->name = "Legacy IO"; | |
1318 | res->flags = IORESOURCE_IO; | |
1319 | res->start = offset; | |
1320 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1321 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1322 | if (request_resource(&hose->io_resource, res)) { | |
1323 | printk(KERN_DEBUG | |
1324 | "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", | |
1325 | pci_domain_nr(bus), bus->number, res); | |
1326 | kfree(res); | |
1327 | } | |
1328 | ||
1329 | no_io: | |
1330 | /* Check for memory */ | |
c1f34302 BH |
1331 | for (i = 0; i < 3; i++) { |
1332 | pres = &hose->mem_resources[i]; | |
3fd47f06 | 1333 | offset = hose->mem_offset[i]; |
c1f34302 BH |
1334 | if (!(pres->flags & IORESOURCE_MEM)) |
1335 | continue; | |
1336 | pr_debug("hose mem res: %pR\n", pres); | |
1337 | if ((pres->start - offset) <= 0xa0000 && | |
1338 | (pres->end - offset) >= 0xbffff) | |
1339 | break; | |
1340 | } | |
1341 | if (i >= 3) | |
1342 | return; | |
1343 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1344 | BUG_ON(res == NULL); | |
1345 | res->name = "Legacy VGA memory"; | |
1346 | res->flags = IORESOURCE_MEM; | |
1347 | res->start = 0xa0000 + offset; | |
1348 | res->end = 0xbffff + offset; | |
1349 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1350 | if (request_resource(pres, res)) { | |
1351 | printk(KERN_DEBUG | |
1352 | "PCI %04x:%02x Cannot reserve VGA memory %pR\n", | |
1353 | pci_domain_nr(bus), bus->number, res); | |
1354 | kfree(res); | |
1355 | } | |
1356 | } | |
1357 | ||
3fd94c6b BH |
1358 | void __init pcibios_resource_survey(void) |
1359 | { | |
e90a1318 NF |
1360 | struct pci_bus *b; |
1361 | ||
48c2ce97 | 1362 | /* Allocate and assign resources */ |
e90a1318 NF |
1363 | list_for_each_entry(b, &pci_root_buses, node) |
1364 | pcibios_allocate_bus_resources(b); | |
48c2ce97 BH |
1365 | pcibios_allocate_resources(0); |
1366 | pcibios_allocate_resources(1); | |
3fd94c6b | 1367 | |
c1f34302 BH |
1368 | /* Before we start assigning unassigned resource, we try to reserve |
1369 | * the low IO area and the VGA memory area if they intersect the | |
1370 | * bus available resources to avoid allocating things on top of them | |
1371 | */ | |
0e47ff1c | 1372 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
c1f34302 BH |
1373 | list_for_each_entry(b, &pci_root_buses, node) |
1374 | pcibios_reserve_legacy_regions(b); | |
1375 | } | |
1376 | ||
1377 | /* Now, if the platform didn't decide to blindly trust the firmware, | |
1378 | * we proceed to assigning things that were left unassigned | |
1379 | */ | |
0e47ff1c | 1380 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
a77acda0 | 1381 | pr_debug("PCI: Assigning unassigned resources...\n"); |
3fd94c6b BH |
1382 | pci_assign_unassigned_resources(); |
1383 | } | |
1384 | ||
1385 | /* Call machine dependent fixup */ | |
1386 | if (ppc_md.pcibios_fixup) | |
1387 | ppc_md.pcibios_fixup(); | |
1388 | } | |
1389 | ||
fd6852c8 | 1390 | /* This is used by the PCI hotplug driver to allocate resource |
3fd94c6b | 1391 | * of newly plugged busses. We can try to consolidate with the |
fd6852c8 BH |
1392 | * rest of the code later, for now, keep it as-is as our main |
1393 | * resource allocation function doesn't deal with sub-trees yet. | |
3fd94c6b | 1394 | */ |
baf75b0a | 1395 | void pcibios_claim_one_bus(struct pci_bus *bus) |
3fd94c6b BH |
1396 | { |
1397 | struct pci_dev *dev; | |
1398 | struct pci_bus *child_bus; | |
1399 | ||
1400 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1401 | int i; | |
1402 | ||
1403 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1404 | struct resource *r = &dev->resource[i]; | |
1405 | ||
1406 | if (r->parent || !r->start || !r->flags) | |
1407 | continue; | |
fd6852c8 | 1408 | |
ae2a84b4 KH |
1409 | pr_debug("PCI: Claiming %s: Resource %d: %pR\n", |
1410 | pci_name(dev), i, r); | |
fd6852c8 | 1411 | |
3ebfe46a YL |
1412 | if (pci_claim_resource(dev, i) == 0) |
1413 | continue; | |
1414 | ||
1415 | pci_claim_bridge_resource(dev, i); | |
3fd94c6b BH |
1416 | } |
1417 | } | |
1418 | ||
1419 | list_for_each_entry(child_bus, &bus->children, node) | |
1420 | pcibios_claim_one_bus(child_bus); | |
1421 | } | |
5b64d2cc | 1422 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); |
fd6852c8 BH |
1423 | |
1424 | ||
1425 | /* pcibios_finish_adding_to_bus | |
1426 | * | |
1427 | * This is to be called by the hotplug code after devices have been | |
1428 | * added to a bus, this include calling it for a PHB that is just | |
1429 | * being added | |
1430 | */ | |
1431 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1432 | { | |
1433 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1434 | pci_domain_nr(bus), bus->number); | |
1435 | ||
1436 | /* Allocate bus and devices resources */ | |
1437 | pcibios_allocate_bus_resources(bus); | |
1438 | pcibios_claim_one_bus(bus); | |
ab444ec9 GS |
1439 | if (!pci_has_flag(PCI_PROBE_ONLY)) |
1440 | pci_assign_unassigned_bus_resources(bus); | |
fd6852c8 | 1441 | |
6a040ce7 TLSC |
1442 | /* Fixup EEH */ |
1443 | eeh_add_device_tree_late(bus); | |
1444 | ||
fd6852c8 BH |
1445 | /* Add new devices to global lists. Register in proc, sysfs. */ |
1446 | pci_bus_add_devices(bus); | |
1447 | ||
6a040ce7 TLSC |
1448 | /* sysfs files should only be added after devices are added */ |
1449 | eeh_add_sysfs_files(bus); | |
fd6852c8 BH |
1450 | } |
1451 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1452 | ||
549beb9b BH |
1453 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1454 | { | |
467efc2e DA |
1455 | struct pci_controller *phb = pci_bus_to_host(dev->bus); |
1456 | ||
1457 | if (phb->controller_ops.enable_device_hook) | |
1458 | if (!phb->controller_ops.enable_device_hook(dev)) | |
1459 | return -EINVAL; | |
549beb9b | 1460 | |
7cfb5f9a | 1461 | return pci_enable_resources(dev, mask); |
549beb9b | 1462 | } |
53280323 | 1463 | |
abeeed6d MN |
1464 | void pcibios_disable_device(struct pci_dev *dev) |
1465 | { | |
1466 | struct pci_controller *phb = pci_bus_to_host(dev->bus); | |
1467 | ||
1468 | if (phb->controller_ops.disable_device) | |
1469 | phb->controller_ops.disable_device(dev); | |
1470 | } | |
1471 | ||
38973ba7 BH |
1472 | resource_size_t pcibios_io_space_offset(struct pci_controller *hose) |
1473 | { | |
1474 | return (unsigned long) hose->io_base_virt - _IO_BASE; | |
1475 | } | |
1476 | ||
cad5cef6 GKH |
1477 | static void pcibios_setup_phb_resources(struct pci_controller *hose, |
1478 | struct list_head *resources) | |
53280323 | 1479 | { |
53280323 | 1480 | struct resource *res; |
3fd47f06 | 1481 | resource_size_t offset; |
53280323 BH |
1482 | int i; |
1483 | ||
1484 | /* Hookup PHB IO resource */ | |
45a709f8 | 1485 | res = &hose->io_resource; |
53280323 BH |
1486 | |
1487 | if (!res->flags) { | |
adb7cd73 | 1488 | pr_info("PCI: I/O resource not set for host" |
53280323 BH |
1489 | " bridge %s (domain %d)\n", |
1490 | hose->dn->full_name, hose->global_number); | |
3fd47f06 BH |
1491 | } else { |
1492 | offset = pcibios_io_space_offset(hose); | |
1493 | ||
ae2a84b4 KH |
1494 | pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n", |
1495 | res, (unsigned long long)offset); | |
3fd47f06 | 1496 | pci_add_resource_offset(resources, res, offset); |
a0b8e76f | 1497 | } |
53280323 BH |
1498 | |
1499 | /* Hookup PHB Memory resources */ | |
1500 | for (i = 0; i < 3; ++i) { | |
1501 | res = &hose->mem_resources[i]; | |
1502 | if (!res->flags) { | |
bee7dd9c BH |
1503 | if (i == 0) |
1504 | printk(KERN_ERR "PCI: Memory resource 0 not set for " | |
1505 | "host bridge %s (domain %d)\n", | |
1506 | hose->dn->full_name, hose->global_number); | |
3fd47f06 | 1507 | continue; |
a0b8e76f | 1508 | } |
3fd47f06 | 1509 | offset = hose->mem_offset[i]; |
53280323 | 1510 | |
3fd47f06 | 1511 | |
ae2a84b4 KH |
1512 | pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, |
1513 | res, (unsigned long long)offset); | |
3fd47f06 BH |
1514 | |
1515 | pci_add_resource_offset(resources, res, offset); | |
1516 | } | |
53280323 | 1517 | } |
89c2dd62 KG |
1518 | |
1519 | /* | |
1520 | * Null PCI config access functions, for the case when we can't | |
1521 | * find a hose. | |
1522 | */ | |
1523 | #define NULL_PCI_OP(rw, size, type) \ | |
1524 | static int \ | |
1525 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1526 | { \ | |
1527 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1528 | } | |
1529 | ||
1530 | static int | |
1531 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1532 | int len, u32 *val) | |
1533 | { | |
1534 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1535 | } | |
1536 | ||
1537 | static int | |
1538 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1539 | int len, u32 val) | |
1540 | { | |
1541 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1542 | } | |
1543 | ||
1544 | static struct pci_ops null_pci_ops = | |
1545 | { | |
1546 | .read = null_read_config, | |
1547 | .write = null_write_config, | |
1548 | }; | |
1549 | ||
1550 | /* | |
1551 | * These functions are used early on before PCI scanning is done | |
1552 | * and all of the pci_dev and pci_bus structures have been created. | |
1553 | */ | |
1554 | static struct pci_bus * | |
1555 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1556 | { | |
1557 | static struct pci_bus bus; | |
1558 | ||
b0d436c7 | 1559 | if (hose == NULL) { |
89c2dd62 KG |
1560 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); |
1561 | } | |
1562 | bus.number = busnr; | |
1563 | bus.sysdata = hose; | |
1564 | bus.ops = hose? hose->ops: &null_pci_ops; | |
1565 | return &bus; | |
1566 | } | |
1567 | ||
1568 | #define EARLY_PCI_OP(rw, size, type) \ | |
1569 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1570 | int devfn, int offset, type value) \ | |
1571 | { \ | |
1572 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1573 | devfn, offset, value); \ | |
1574 | } | |
1575 | ||
1576 | EARLY_PCI_OP(read, byte, u8 *) | |
1577 | EARLY_PCI_OP(read, word, u16 *) | |
1578 | EARLY_PCI_OP(read, dword, u32 *) | |
1579 | EARLY_PCI_OP(write, byte, u8) | |
1580 | EARLY_PCI_OP(write, word, u16) | |
1581 | EARLY_PCI_OP(write, dword, u32) | |
1582 | ||
89c2dd62 KG |
1583 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, |
1584 | int cap) | |
1585 | { | |
1586 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1587 | } | |
0ed2c722 | 1588 | |
98d9f30c BH |
1589 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
1590 | { | |
1591 | struct pci_controller *hose = bus->sysdata; | |
1592 | ||
1593 | return of_node_get(hose->dn); | |
1594 | } | |
1595 | ||
0ed2c722 GL |
1596 | /** |
1597 | * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus | |
1598 | * @hose: Pointer to the PCI host controller instance structure | |
0ed2c722 | 1599 | */ |
cad5cef6 | 1600 | void pcibios_scan_phb(struct pci_controller *hose) |
0ed2c722 | 1601 | { |
45a709f8 | 1602 | LIST_HEAD(resources); |
0ed2c722 GL |
1603 | struct pci_bus *bus; |
1604 | struct device_node *node = hose->dn; | |
1605 | int mode; | |
1606 | ||
74a7f084 | 1607 | pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); |
0ed2c722 | 1608 | |
45a709f8 BH |
1609 | /* Get some IO space for the new PHB */ |
1610 | pcibios_setup_phb_io_space(hose); | |
1611 | ||
1612 | /* Wire up PHB bus resources */ | |
1613 | pcibios_setup_phb_resources(hose, &resources); | |
1614 | ||
be8e60d8 YL |
1615 | hose->busn.start = hose->first_busno; |
1616 | hose->busn.end = hose->last_busno; | |
1617 | hose->busn.flags = IORESOURCE_BUS; | |
1618 | pci_add_resource(&resources, &hose->busn); | |
1619 | ||
0ed2c722 | 1620 | /* Create an empty bus for the toplevel */ |
45a709f8 BH |
1621 | bus = pci_create_root_bus(hose->parent, hose->first_busno, |
1622 | hose->ops, hose, &resources); | |
0ed2c722 GL |
1623 | if (bus == NULL) { |
1624 | pr_err("Failed to create bus for PCI domain %04x\n", | |
1625 | hose->global_number); | |
45a709f8 | 1626 | pci_free_resource_list(&resources); |
0ed2c722 GL |
1627 | return; |
1628 | } | |
0ed2c722 GL |
1629 | hose->bus = bus; |
1630 | ||
0ed2c722 GL |
1631 | /* Get probe mode and perform scan */ |
1632 | mode = PCI_PROBE_NORMAL; | |
467efc2e DA |
1633 | if (node && hose->controller_ops.probe_mode) |
1634 | mode = hose->controller_ops.probe_mode(bus); | |
0ed2c722 | 1635 | pr_debug(" probe mode: %d\n", mode); |
be8e60d8 | 1636 | if (mode == PCI_PROBE_DEVTREE) |
0ed2c722 | 1637 | of_scan_bus(node, bus); |
0ed2c722 | 1638 | |
be8e60d8 YL |
1639 | if (mode == PCI_PROBE_NORMAL) { |
1640 | pci_bus_update_busn_res_end(bus, 255); | |
1641 | hose->last_busno = pci_scan_child_bus(bus); | |
1642 | pci_bus_update_busn_res_end(bus, hose->last_busno); | |
1643 | } | |
781fb7a3 | 1644 | |
491b98c3 BH |
1645 | /* Platform gets a chance to do some global fixups before |
1646 | * we proceed to resource allocation | |
1647 | */ | |
1648 | if (ppc_md.pcibios_fixup_phb) | |
1649 | ppc_md.pcibios_fixup_phb(hose); | |
1650 | ||
781fb7a3 | 1651 | /* Configure PCI Express settings */ |
bb36c445 | 1652 | if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { |
781fb7a3 | 1653 | struct pci_bus *child; |
a58674ff BH |
1654 | list_for_each_entry(child, &bus->children, node) |
1655 | pcie_bus_configure_settings(child); | |
781fb7a3 | 1656 | } |
0ed2c722 | 1657 | } |
5b64d2cc | 1658 | EXPORT_SYMBOL_GPL(pcibios_scan_phb); |
c065488f KG |
1659 | |
1660 | static void fixup_hide_host_resource_fsl(struct pci_dev *dev) | |
1661 | { | |
1662 | int i, class = dev->class >> 8; | |
05737c7c JJ |
1663 | /* When configured as agent, programing interface = 1 */ |
1664 | int prog_if = dev->class & 0xf; | |
c065488f KG |
1665 | |
1666 | if ((class == PCI_CLASS_PROCESSOR_POWERPC || | |
1667 | class == PCI_CLASS_BRIDGE_OTHER) && | |
1668 | (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && | |
05737c7c | 1669 | (prog_if == 0) && |
c065488f KG |
1670 | (dev->bus->parent == NULL)) { |
1671 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1672 | dev->resource[i].start = 0; | |
1673 | dev->resource[i].end = 0; | |
1674 | dev->resource[i].flags = 0; | |
1675 | } | |
1676 | } | |
1677 | } | |
1678 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
1679 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
c2e1d845 BK |
1680 | |
1681 | static void fixup_vga(struct pci_dev *pdev) | |
1682 | { | |
1683 | u16 cmd; | |
1684 | ||
1685 | pci_read_config_word(pdev, PCI_COMMAND, &cmd); | |
1686 | if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) | |
1687 | vga_set_default_device(pdev); | |
1688 | ||
1689 | } | |
1690 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, | |
1691 | PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); |