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5516b540 KG |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
3 | * (based on pci_32.c and pci_64.c) |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
5516b540 KG |
19 | #include <linux/kernel.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/bootmem.h> | |
22ae782f | 24 | #include <linux/of_address.h> |
5516b540 KG |
25 | #include <linux/mm.h> |
26 | #include <linux/list.h> | |
27 | #include <linux/syscalls.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
5516b540 KG |
31 | |
32 | #include <asm/processor.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/prom.h> | |
35 | #include <asm/pci-bridge.h> | |
36 | #include <asm/byteorder.h> | |
37 | #include <asm/machdep.h> | |
38 | #include <asm/ppc-pci.h> | |
39 | #include <asm/firmware.h> | |
8b8da358 | 40 | #include <asm/eeh.h> |
5516b540 | 41 | |
a4c9e328 | 42 | static DEFINE_SPINLOCK(hose_spinlock); |
c3bd517d | 43 | LIST_HEAD(hose_list); |
a4c9e328 KG |
44 | |
45 | /* XXX kill that some day ... */ | |
ebfc00f7 | 46 | static int global_phb_number; /* Global phb counter */ |
a4c9e328 | 47 | |
25e81f92 BH |
48 | /* ISA Memory physical address */ |
49 | resource_size_t isa_mem_base; | |
50 | ||
1fd0f525 BH |
51 | /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */ |
52 | unsigned int ppc_pci_flags = 0; | |
53 | ||
a4c9e328 | 54 | |
45223c54 | 55 | static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; |
4fc665b8 | 56 | |
45223c54 | 57 | void set_pci_dma_ops(struct dma_map_ops *dma_ops) |
4fc665b8 BB |
58 | { |
59 | pci_dma_ops = dma_ops; | |
60 | } | |
61 | ||
45223c54 | 62 | struct dma_map_ops *get_pci_dma_ops(void) |
4fc665b8 BB |
63 | { |
64 | return pci_dma_ops; | |
65 | } | |
66 | EXPORT_SYMBOL(get_pci_dma_ops); | |
67 | ||
e60516e3 | 68 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
69 | { |
70 | struct pci_controller *phb; | |
71 | ||
e60516e3 | 72 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
73 | if (phb == NULL) |
74 | return NULL; | |
e60516e3 SR |
75 | spin_lock(&hose_spinlock); |
76 | phb->global_number = global_phb_number++; | |
77 | list_add_tail(&phb->list_node, &hose_list); | |
78 | spin_unlock(&hose_spinlock); | |
44ef3390 | 79 | phb->dn = dev; |
a4c9e328 KG |
80 | phb->is_dynamic = mem_init_done; |
81 | #ifdef CONFIG_PPC64 | |
82 | if (dev) { | |
83 | int nid = of_node_to_nid(dev); | |
84 | ||
85 | if (nid < 0 || !node_online(nid)) | |
86 | nid = -1; | |
87 | ||
88 | PHB_SET_NODE(phb, nid); | |
89 | } | |
90 | #endif | |
91 | return phb; | |
92 | } | |
93 | ||
94 | void pcibios_free_controller(struct pci_controller *phb) | |
95 | { | |
96 | spin_lock(&hose_spinlock); | |
97 | list_del(&phb->list_node); | |
98 | spin_unlock(&hose_spinlock); | |
99 | ||
100 | if (phb->is_dynamic) | |
101 | kfree(phb); | |
102 | } | |
103 | ||
c3bd517d MM |
104 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) |
105 | { | |
106 | #ifdef CONFIG_PPC64 | |
107 | return hose->pci_io_size; | |
108 | #else | |
109 | return hose->io_resource.end - hose->io_resource.start + 1; | |
110 | #endif | |
111 | } | |
112 | ||
6dfbde20 BH |
113 | int pcibios_vaddr_is_ioport(void __iomem *address) |
114 | { | |
115 | int ret = 0; | |
116 | struct pci_controller *hose; | |
c3bd517d | 117 | resource_size_t size; |
6dfbde20 BH |
118 | |
119 | spin_lock(&hose_spinlock); | |
120 | list_for_each_entry(hose, &hose_list, list_node) { | |
c3bd517d | 121 | size = pcibios_io_size(hose); |
6dfbde20 BH |
122 | if (address >= hose->io_base_virt && |
123 | address < (hose->io_base_virt + size)) { | |
124 | ret = 1; | |
125 | break; | |
126 | } | |
127 | } | |
128 | spin_unlock(&hose_spinlock); | |
129 | return ret; | |
130 | } | |
131 | ||
c3bd517d MM |
132 | unsigned long pci_address_to_pio(phys_addr_t address) |
133 | { | |
134 | struct pci_controller *hose; | |
135 | resource_size_t size; | |
136 | unsigned long ret = ~0; | |
137 | ||
138 | spin_lock(&hose_spinlock); | |
139 | list_for_each_entry(hose, &hose_list, list_node) { | |
140 | size = pcibios_io_size(hose); | |
141 | if (address >= hose->io_base_phys && | |
142 | address < (hose->io_base_phys + size)) { | |
143 | unsigned long base = | |
144 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
145 | ret = base + (address - hose->io_base_phys); | |
146 | break; | |
147 | } | |
148 | } | |
149 | spin_unlock(&hose_spinlock); | |
150 | ||
151 | return ret; | |
152 | } | |
153 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
154 | ||
5516b540 KG |
155 | /* |
156 | * Return the domain number for this bus. | |
157 | */ | |
158 | int pci_domain_nr(struct pci_bus *bus) | |
159 | { | |
6207e816 | 160 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 161 | |
6207e816 | 162 | return hose->global_number; |
5516b540 | 163 | } |
5516b540 | 164 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad | 165 | |
a4c9e328 KG |
166 | /* This routine is meant to be used early during boot, when the |
167 | * PCI bus numbers have not yet been assigned, and you need to | |
168 | * issue PCI config cycles to an OF device. | |
169 | * It could also be used to "fix" RTAS config cycles if you want | |
170 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
171 | * config cycles. | |
172 | */ | |
173 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
174 | { | |
a4c9e328 KG |
175 | while(node) { |
176 | struct pci_controller *hose, *tmp; | |
177 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 178 | if (hose->dn == node) |
a4c9e328 KG |
179 | return hose; |
180 | node = node->parent; | |
181 | } | |
182 | return NULL; | |
183 | } | |
184 | ||
58083dad KG |
185 | static ssize_t pci_show_devspec(struct device *dev, |
186 | struct device_attribute *attr, char *buf) | |
187 | { | |
188 | struct pci_dev *pdev; | |
189 | struct device_node *np; | |
190 | ||
191 | pdev = to_pci_dev (dev); | |
192 | np = pci_device_to_OF_node(pdev); | |
193 | if (np == NULL || np->full_name == NULL) | |
194 | return 0; | |
195 | return sprintf(buf, "%s", np->full_name); | |
196 | } | |
197 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
58083dad KG |
198 | |
199 | /* Add sysfs properties */ | |
4f3731da | 200 | int pcibios_add_platform_entries(struct pci_dev *pdev) |
58083dad | 201 | { |
4f3731da | 202 | return device_create_file(&pdev->dev, &dev_attr_devspec); |
58083dad KG |
203 | } |
204 | ||
a2b7390a | 205 | char __devinit *pcibios_setup(char *str) |
58083dad KG |
206 | { |
207 | return str; | |
208 | } | |
209 | ||
210 | /* | |
211 | * Reads the interrupt pin to determine if interrupt is use by card. | |
212 | * If the interrupt is used, then gets the interrupt line from the | |
213 | * openfirmware and sets it in the pci_dev and pci_config line. | |
214 | */ | |
215 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
216 | { | |
217 | struct of_irq oirq; | |
218 | unsigned int virq; | |
219 | ||
50c9bc2f BH |
220 | /* The current device-tree that iSeries generates from the HV |
221 | * PCI informations doesn't contain proper interrupt routing, | |
222 | * and all the fallback would do is print out crap, so we | |
223 | * don't attempt to resolve the interrupts here at all, some | |
224 | * iSeries specific fixup does it. | |
225 | * | |
226 | * In the long run, we will hopefully fix the generated device-tree | |
227 | * instead. | |
228 | */ | |
229 | #ifdef CONFIG_PPC_ISERIES | |
230 | if (firmware_has_feature(FW_FEATURE_ISERIES)) | |
231 | return -1; | |
232 | #endif | |
233 | ||
b0494bc8 | 234 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); |
58083dad KG |
235 | |
236 | #ifdef DEBUG | |
237 | memset(&oirq, 0xff, sizeof(oirq)); | |
238 | #endif | |
239 | /* Try to get a mapping from the device-tree */ | |
240 | if (of_irq_map_pci(pci_dev, &oirq)) { | |
241 | u8 line, pin; | |
242 | ||
243 | /* If that fails, lets fallback to what is in the config | |
244 | * space and map that through the default controller. We | |
245 | * also set the type to level low since that's what PCI | |
246 | * interrupts are. If your platform does differently, then | |
247 | * either provide a proper interrupt tree or don't use this | |
248 | * function. | |
249 | */ | |
250 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
251 | return -1; | |
252 | if (pin == 0) | |
253 | return -1; | |
254 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 255 | line == 0xff || line == 0) { |
58083dad KG |
256 | return -1; |
257 | } | |
b0494bc8 BH |
258 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", |
259 | line, pin); | |
58083dad KG |
260 | |
261 | virq = irq_create_mapping(NULL, line); | |
262 | if (virq != NO_IRQ) | |
263 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); | |
264 | } else { | |
b0494bc8 BH |
265 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
266 | oirq.size, oirq.specifier[0], oirq.specifier[1], | |
59b608c2 BH |
267 | oirq.controller ? oirq.controller->full_name : |
268 | "<default>"); | |
58083dad KG |
269 | |
270 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
271 | oirq.size); | |
272 | } | |
273 | if(virq == NO_IRQ) { | |
b0494bc8 | 274 | pr_debug(" Failed to map !\n"); |
58083dad KG |
275 | return -1; |
276 | } | |
277 | ||
b0494bc8 | 278 | pr_debug(" Mapped to linux irq %d\n", virq); |
58083dad KG |
279 | |
280 | pci_dev->irq = virq; | |
281 | ||
282 | return 0; | |
283 | } | |
284 | EXPORT_SYMBOL(pci_read_irq_line); | |
285 | ||
286 | /* | |
287 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
288 | * modelled on the sparc64 implementation by Dave Miller. | |
289 | * -- paulus. | |
290 | */ | |
291 | ||
292 | /* | |
293 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
294 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
295 | * | |
296 | * Basically, the user finds the base address for his device which he wishes | |
297 | * to mmap. They read the 32-bit value from the config space base register, | |
298 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
299 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
300 | * | |
301 | * Returns negative error code on failure, zero on success. | |
302 | */ | |
303 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
304 | resource_size_t *offset, | |
305 | enum pci_mmap_state mmap_state) | |
306 | { | |
307 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
308 | unsigned long io_offset = 0; | |
309 | int i, res_bit; | |
310 | ||
311 | if (hose == 0) | |
312 | return NULL; /* should never happen */ | |
313 | ||
314 | /* If memory, add on the PCI bridge address offset */ | |
315 | if (mmap_state == pci_mmap_mem) { | |
316 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
317 | *offset += hose->pci_mem_offset; | |
318 | #endif | |
319 | res_bit = IORESOURCE_MEM; | |
320 | } else { | |
321 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
322 | *offset += io_offset; | |
323 | res_bit = IORESOURCE_IO; | |
324 | } | |
325 | ||
326 | /* | |
327 | * Check that the offset requested corresponds to one of the | |
328 | * resources of the device. | |
329 | */ | |
330 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
331 | struct resource *rp = &dev->resource[i]; | |
332 | int flags = rp->flags; | |
333 | ||
334 | /* treat ROM as memory (should be already) */ | |
335 | if (i == PCI_ROM_RESOURCE) | |
336 | flags |= IORESOURCE_MEM; | |
337 | ||
338 | /* Active and same type? */ | |
339 | if ((flags & res_bit) == 0) | |
340 | continue; | |
341 | ||
342 | /* In the range of this resource? */ | |
343 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
344 | continue; | |
345 | ||
346 | /* found it! construct the final physical address */ | |
347 | if (mmap_state == pci_mmap_io) | |
348 | *offset += hose->io_base_phys - io_offset; | |
349 | return rp; | |
350 | } | |
351 | ||
352 | return NULL; | |
353 | } | |
354 | ||
355 | /* | |
356 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
357 | * device mapping. | |
358 | */ | |
359 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
360 | pgprot_t protection, | |
361 | enum pci_mmap_state mmap_state, | |
362 | int write_combine) | |
363 | { | |
364 | unsigned long prot = pgprot_val(protection); | |
365 | ||
366 | /* Write combine is always 0 on non-memory space mappings. On | |
367 | * memory space, if the user didn't pass 1, we check for a | |
368 | * "prefetchable" resource. This is a bit hackish, but we use | |
369 | * this to workaround the inability of /sysfs to provide a write | |
370 | * combine bit | |
371 | */ | |
372 | if (mmap_state != pci_mmap_mem) | |
373 | write_combine = 0; | |
374 | else if (write_combine == 0) { | |
375 | if (rp->flags & IORESOURCE_PREFETCH) | |
376 | write_combine = 1; | |
377 | } | |
378 | ||
379 | /* XXX would be nice to have a way to ask for write-through */ | |
58083dad | 380 | if (write_combine) |
64b3d0e8 | 381 | return pgprot_noncached_wc(prot); |
58083dad | 382 | else |
64b3d0e8 | 383 | return pgprot_noncached(prot); |
58083dad KG |
384 | } |
385 | ||
386 | /* | |
387 | * This one is used by /dev/mem and fbdev who have no clue about the | |
388 | * PCI device, it tries to find the PCI device first and calls the | |
389 | * above routine | |
390 | */ | |
391 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
392 | unsigned long pfn, | |
393 | unsigned long size, | |
64b3d0e8 | 394 | pgprot_t prot) |
58083dad KG |
395 | { |
396 | struct pci_dev *pdev = NULL; | |
397 | struct resource *found = NULL; | |
7c12d906 | 398 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
399 | int i; |
400 | ||
401 | if (page_is_ram(pfn)) | |
64b3d0e8 | 402 | return prot; |
58083dad | 403 | |
64b3d0e8 | 404 | prot = pgprot_noncached(prot); |
58083dad KG |
405 | for_each_pci_dev(pdev) { |
406 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
407 | struct resource *rp = &pdev->resource[i]; | |
408 | int flags = rp->flags; | |
409 | ||
410 | /* Active and same type? */ | |
411 | if ((flags & IORESOURCE_MEM) == 0) | |
412 | continue; | |
413 | /* In the range of this resource? */ | |
414 | if (offset < (rp->start & PAGE_MASK) || | |
415 | offset > rp->end) | |
416 | continue; | |
417 | found = rp; | |
418 | break; | |
419 | } | |
420 | if (found) | |
421 | break; | |
422 | } | |
423 | if (found) { | |
424 | if (found->flags & IORESOURCE_PREFETCH) | |
64b3d0e8 | 425 | prot = pgprot_noncached_wc(prot); |
58083dad KG |
426 | pci_dev_put(pdev); |
427 | } | |
428 | ||
b0494bc8 | 429 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
64b3d0e8 | 430 | (unsigned long long)offset, pgprot_val(prot)); |
58083dad | 431 | |
64b3d0e8 | 432 | return prot; |
58083dad KG |
433 | } |
434 | ||
435 | ||
436 | /* | |
437 | * Perform the actual remap of the pages for a PCI device mapping, as | |
438 | * appropriate for this architecture. The region in the process to map | |
439 | * is described by vm_start and vm_end members of VMA, the base physical | |
440 | * address is found in vm_pgoff. | |
441 | * The pci device structure is provided so that architectures may make mapping | |
442 | * decisions on a per-device or per-bus basis. | |
443 | * | |
444 | * Returns a negative error code on failure, zero on success. | |
445 | */ | |
446 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
447 | enum pci_mmap_state mmap_state, int write_combine) | |
448 | { | |
7c12d906 BH |
449 | resource_size_t offset = |
450 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
58083dad KG |
451 | struct resource *rp; |
452 | int ret; | |
453 | ||
454 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
455 | if (rp == NULL) | |
456 | return -EINVAL; | |
457 | ||
458 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
459 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
460 | vma->vm_page_prot, | |
461 | mmap_state, write_combine); | |
462 | ||
463 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
464 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
465 | ||
466 | return ret; | |
467 | } | |
468 | ||
e9f82cb7 BH |
469 | /* This provides legacy IO read access on a bus */ |
470 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
471 | { | |
472 | unsigned long offset; | |
473 | struct pci_controller *hose = pci_bus_to_host(bus); | |
474 | struct resource *rp = &hose->io_resource; | |
475 | void __iomem *addr; | |
476 | ||
477 | /* Check if port can be supported by that bus. We only check | |
478 | * the ranges of the PHB though, not the bus itself as the rules | |
479 | * for forwarding legacy cycles down bridges are not our problem | |
480 | * here. So if the host bridge supports it, we do it. | |
481 | */ | |
482 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
483 | offset += port; | |
484 | ||
485 | if (!(rp->flags & IORESOURCE_IO)) | |
486 | return -ENXIO; | |
487 | if (offset < rp->start || (offset + size) > rp->end) | |
488 | return -ENXIO; | |
489 | addr = hose->io_base_virt + port; | |
490 | ||
491 | switch(size) { | |
492 | case 1: | |
493 | *((u8 *)val) = in_8(addr); | |
494 | return 1; | |
495 | case 2: | |
496 | if (port & 1) | |
497 | return -EINVAL; | |
498 | *((u16 *)val) = in_le16(addr); | |
499 | return 2; | |
500 | case 4: | |
501 | if (port & 3) | |
502 | return -EINVAL; | |
503 | *((u32 *)val) = in_le32(addr); | |
504 | return 4; | |
505 | } | |
506 | return -EINVAL; | |
507 | } | |
508 | ||
509 | /* This provides legacy IO write access on a bus */ | |
510 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
511 | { | |
512 | unsigned long offset; | |
513 | struct pci_controller *hose = pci_bus_to_host(bus); | |
514 | struct resource *rp = &hose->io_resource; | |
515 | void __iomem *addr; | |
516 | ||
517 | /* Check if port can be supported by that bus. We only check | |
518 | * the ranges of the PHB though, not the bus itself as the rules | |
519 | * for forwarding legacy cycles down bridges are not our problem | |
520 | * here. So if the host bridge supports it, we do it. | |
521 | */ | |
522 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
523 | offset += port; | |
524 | ||
525 | if (!(rp->flags & IORESOURCE_IO)) | |
526 | return -ENXIO; | |
527 | if (offset < rp->start || (offset + size) > rp->end) | |
528 | return -ENXIO; | |
529 | addr = hose->io_base_virt + port; | |
530 | ||
531 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
532 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
533 | * as a u32, which means that we have to correct the location of | |
534 | * the data read within those 32 bits for size 1 and 2 | |
535 | */ | |
536 | switch(size) { | |
537 | case 1: | |
538 | out_8(addr, val >> 24); | |
539 | return 1; | |
540 | case 2: | |
541 | if (port & 1) | |
542 | return -EINVAL; | |
543 | out_le16(addr, val >> 16); | |
544 | return 2; | |
545 | case 4: | |
546 | if (port & 3) | |
547 | return -EINVAL; | |
548 | out_le32(addr, val); | |
549 | return 4; | |
550 | } | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | /* This provides legacy IO or memory mmap access on a bus */ | |
555 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
556 | struct vm_area_struct *vma, | |
557 | enum pci_mmap_state mmap_state) | |
558 | { | |
559 | struct pci_controller *hose = pci_bus_to_host(bus); | |
560 | resource_size_t offset = | |
561 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
562 | resource_size_t size = vma->vm_end - vma->vm_start; | |
563 | struct resource *rp; | |
564 | ||
565 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
566 | pci_domain_nr(bus), bus->number, | |
567 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
568 | (unsigned long long)offset, | |
569 | (unsigned long long)(offset + size - 1)); | |
570 | ||
571 | if (mmap_state == pci_mmap_mem) { | |
5b11abfd BH |
572 | /* Hack alert ! |
573 | * | |
574 | * Because X is lame and can fail starting if it gets an error trying | |
575 | * to mmap legacy_mem (instead of just moving on without legacy memory | |
576 | * access) we fake it here by giving it anonymous memory, effectively | |
577 | * behaving just like /dev/zero | |
578 | */ | |
579 | if ((offset + size) > hose->isa_mem_size) { | |
580 | printk(KERN_DEBUG | |
581 | "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", | |
582 | current->comm, current->pid, pci_domain_nr(bus), bus->number); | |
583 | if (vma->vm_flags & VM_SHARED) | |
584 | return shmem_zero_setup(vma); | |
585 | return 0; | |
586 | } | |
e9f82cb7 BH |
587 | offset += hose->isa_mem_phys; |
588 | } else { | |
589 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
590 | unsigned long roffset = offset + io_offset; | |
591 | rp = &hose->io_resource; | |
592 | if (!(rp->flags & IORESOURCE_IO)) | |
593 | return -ENXIO; | |
594 | if (roffset < rp->start || (roffset + size) > rp->end) | |
595 | return -ENXIO; | |
596 | offset += hose->io_base_phys; | |
597 | } | |
598 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
599 | ||
600 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
64b3d0e8 | 601 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
e9f82cb7 BH |
602 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
603 | vma->vm_end - vma->vm_start, | |
604 | vma->vm_page_prot); | |
605 | } | |
606 | ||
58083dad KG |
607 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
608 | const struct resource *rsrc, | |
609 | resource_size_t *start, resource_size_t *end) | |
610 | { | |
611 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
612 | resource_size_t offset = 0; | |
613 | ||
614 | if (hose == NULL) | |
615 | return; | |
616 | ||
617 | if (rsrc->flags & IORESOURCE_IO) | |
618 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
619 | ||
620 | /* We pass a fully fixed up address to userland for MMIO instead of | |
621 | * a BAR value because X is lame and expects to be able to use that | |
622 | * to pass to /dev/mem ! | |
623 | * | |
624 | * That means that we'll have potentially 64 bits values where some | |
625 | * userland apps only expect 32 (like X itself since it thinks only | |
626 | * Sparc has 64 bits MMIO) but if we don't do that, we break it on | |
627 | * 32 bits CHRPs :-( | |
628 | * | |
629 | * Hopefully, the sysfs insterface is immune to that gunk. Once X | |
630 | * has been fixed (and the fix spread enough), we can re-enable the | |
631 | * 2 lines below and pass down a BAR value to userland. In that case | |
632 | * we'll also have to re-enable the matching code in | |
633 | * __pci_mmap_make_offset(). | |
634 | * | |
635 | * BenH. | |
636 | */ | |
637 | #if 0 | |
638 | else if (rsrc->flags & IORESOURCE_MEM) | |
639 | offset = hose->pci_mem_offset; | |
640 | #endif | |
641 | ||
642 | *start = rsrc->start - offset; | |
643 | *end = rsrc->end - offset; | |
644 | } | |
13dccb9e BH |
645 | |
646 | /** | |
647 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
648 | * @hose: newly allocated pci_controller to be setup | |
649 | * @dev: device node of the host bridge | |
650 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
651 | * | |
652 | * This function will parse the "ranges" property of a PCI host bridge device | |
653 | * node and setup the resource mapping of a pci controller based on its | |
654 | * content. | |
655 | * | |
656 | * Life would be boring if it wasn't for a few issues that we have to deal | |
657 | * with here: | |
658 | * | |
659 | * - We can only cope with one IO space range and up to 3 Memory space | |
660 | * ranges. However, some machines (thanks Apple !) tend to split their | |
661 | * space into lots of small contiguous ranges. So we have to coalesce. | |
662 | * | |
663 | * - We can only cope with all memory ranges having the same offset | |
664 | * between CPU addresses and PCI addresses. Unfortunately, some bridges | |
665 | * are setup for a large 1:1 mapping along with a small "window" which | |
666 | * maps PCI address 0 to some arbitrary high address of the CPU space in | |
667 | * order to give access to the ISA memory hole. | |
668 | * The way out of here that I've chosen for now is to always set the | |
669 | * offset based on the first resource found, then override it if we | |
670 | * have a different offset and the previous was set by an ISA hole. | |
671 | * | |
672 | * - Some busses have IO space not starting at 0, which causes trouble with | |
673 | * the way we do our IO resource renumbering. The code somewhat deals with | |
674 | * it for 64 bits but I would expect problems on 32 bits. | |
675 | * | |
676 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
677 | * 32 bits so we need to use 64 bits values for the parsing | |
678 | */ | |
679 | void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
680 | struct device_node *dev, | |
681 | int primary) | |
682 | { | |
683 | const u32 *ranges; | |
684 | int rlen; | |
685 | int pna = of_n_addr_cells(dev); | |
686 | int np = pna + 5; | |
687 | int memno = 0, isa_hole = -1; | |
688 | u32 pci_space; | |
689 | unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; | |
690 | unsigned long long isa_mb = 0; | |
691 | struct resource *res; | |
692 | ||
693 | printk(KERN_INFO "PCI host bridge %s %s ranges:\n", | |
694 | dev->full_name, primary ? "(primary)" : ""); | |
695 | ||
696 | /* Get ranges property */ | |
697 | ranges = of_get_property(dev, "ranges", &rlen); | |
698 | if (ranges == NULL) | |
699 | return; | |
700 | ||
701 | /* Parse it */ | |
702 | while ((rlen -= np * 4) >= 0) { | |
703 | /* Read next ranges element */ | |
704 | pci_space = ranges[0]; | |
705 | pci_addr = of_read_number(ranges + 1, 2); | |
706 | cpu_addr = of_translate_address(dev, ranges + 3); | |
707 | size = of_read_number(ranges + pna + 3, 2); | |
708 | ranges += np; | |
e9f82cb7 BH |
709 | |
710 | /* If we failed translation or got a zero-sized region | |
711 | * (some FW try to feed us with non sensical zero sized regions | |
712 | * such as power3 which look like some kind of attempt at exposing | |
713 | * the VGA memory hole) | |
714 | */ | |
13dccb9e BH |
715 | if (cpu_addr == OF_BAD_ADDR || size == 0) |
716 | continue; | |
717 | ||
718 | /* Now consume following elements while they are contiguous */ | |
719 | for (; rlen >= np * sizeof(u32); | |
720 | ranges += np, rlen -= np * 4) { | |
721 | if (ranges[0] != pci_space) | |
722 | break; | |
723 | pci_next = of_read_number(ranges + 1, 2); | |
724 | cpu_next = of_translate_address(dev, ranges + 3); | |
725 | if (pci_next != pci_addr + size || | |
726 | cpu_next != cpu_addr + size) | |
727 | break; | |
728 | size += of_read_number(ranges + pna + 3, 2); | |
729 | } | |
730 | ||
731 | /* Act based on address space type */ | |
732 | res = NULL; | |
733 | switch ((pci_space >> 24) & 0x3) { | |
734 | case 1: /* PCI IO space */ | |
735 | printk(KERN_INFO | |
736 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
737 | cpu_addr, cpu_addr + size - 1, pci_addr); | |
738 | ||
739 | /* We support only one IO range */ | |
740 | if (hose->pci_io_size) { | |
741 | printk(KERN_INFO | |
742 | " \\--> Skipped (too many) !\n"); | |
743 | continue; | |
744 | } | |
745 | #ifdef CONFIG_PPC32 | |
746 | /* On 32 bits, limit I/O space to 16MB */ | |
747 | if (size > 0x01000000) | |
748 | size = 0x01000000; | |
749 | ||
750 | /* 32 bits needs to map IOs here */ | |
751 | hose->io_base_virt = ioremap(cpu_addr, size); | |
752 | ||
753 | /* Expect trouble if pci_addr is not 0 */ | |
754 | if (primary) | |
755 | isa_io_base = | |
756 | (unsigned long)hose->io_base_virt; | |
757 | #endif /* CONFIG_PPC32 */ | |
758 | /* pci_io_size and io_base_phys always represent IO | |
759 | * space starting at 0 so we factor in pci_addr | |
760 | */ | |
761 | hose->pci_io_size = pci_addr + size; | |
762 | hose->io_base_phys = cpu_addr - pci_addr; | |
763 | ||
764 | /* Build resource */ | |
765 | res = &hose->io_resource; | |
766 | res->flags = IORESOURCE_IO; | |
767 | res->start = pci_addr; | |
768 | break; | |
769 | case 2: /* PCI Memory space */ | |
67260ac9 | 770 | case 3: /* PCI 64 bits Memory space */ |
13dccb9e BH |
771 | printk(KERN_INFO |
772 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
773 | cpu_addr, cpu_addr + size - 1, pci_addr, | |
774 | (pci_space & 0x40000000) ? "Prefetch" : ""); | |
775 | ||
776 | /* We support only 3 memory ranges */ | |
777 | if (memno >= 3) { | |
778 | printk(KERN_INFO | |
779 | " \\--> Skipped (too many) !\n"); | |
780 | continue; | |
781 | } | |
782 | /* Handles ISA memory hole space here */ | |
783 | if (pci_addr == 0) { | |
784 | isa_mb = cpu_addr; | |
785 | isa_hole = memno; | |
786 | if (primary || isa_mem_base == 0) | |
787 | isa_mem_base = cpu_addr; | |
e9f82cb7 BH |
788 | hose->isa_mem_phys = cpu_addr; |
789 | hose->isa_mem_size = size; | |
13dccb9e BH |
790 | } |
791 | ||
792 | /* We get the PCI/Mem offset from the first range or | |
793 | * the, current one if the offset came from an ISA | |
794 | * hole. If they don't match, bugger. | |
795 | */ | |
796 | if (memno == 0 || | |
797 | (isa_hole >= 0 && pci_addr != 0 && | |
798 | hose->pci_mem_offset == isa_mb)) | |
799 | hose->pci_mem_offset = cpu_addr - pci_addr; | |
800 | else if (pci_addr != 0 && | |
801 | hose->pci_mem_offset != cpu_addr - pci_addr) { | |
802 | printk(KERN_INFO | |
803 | " \\--> Skipped (offset mismatch) !\n"); | |
804 | continue; | |
805 | } | |
806 | ||
807 | /* Build resource */ | |
808 | res = &hose->mem_resources[memno++]; | |
809 | res->flags = IORESOURCE_MEM; | |
810 | if (pci_space & 0x40000000) | |
811 | res->flags |= IORESOURCE_PREFETCH; | |
812 | res->start = cpu_addr; | |
813 | break; | |
814 | } | |
815 | if (res != NULL) { | |
816 | res->name = dev->full_name; | |
817 | res->end = res->start + size - 1; | |
818 | res->parent = NULL; | |
819 | res->sibling = NULL; | |
820 | res->child = NULL; | |
821 | } | |
822 | } | |
823 | ||
8db13a0e BH |
824 | /* If there's an ISA hole and the pci_mem_offset is -not- matching |
825 | * the ISA hole offset, then we need to remove the ISA hole from | |
826 | * the resource list for that brige | |
827 | */ | |
828 | if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { | |
829 | unsigned int next = isa_hole + 1; | |
830 | printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); | |
831 | if (next < memno) | |
832 | memmove(&hose->mem_resources[isa_hole], | |
833 | &hose->mem_resources[next], | |
834 | sizeof(struct resource) * (memno - next)); | |
835 | hose->mem_resources[--memno].flags = 0; | |
13dccb9e BH |
836 | } |
837 | } | |
fa462f2d BH |
838 | |
839 | /* Decide whether to display the domain number in /proc */ | |
840 | int pci_proc_domain(struct pci_bus *bus) | |
841 | { | |
842 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1fd0f525 | 843 | |
fa462f2d BH |
844 | if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) |
845 | return 0; | |
846 | if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) | |
847 | return hose->global_number != 0; | |
848 | return 1; | |
fa462f2d BH |
849 | } |
850 | ||
fe2d338c BH |
851 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
852 | struct resource *res) | |
853 | { | |
854 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
855 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
856 | ||
857 | if (!hose) | |
858 | return; | |
859 | if (res->flags & IORESOURCE_IO) { | |
860 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
861 | mask = 0xffffffffu; | |
862 | } else if (res->flags & IORESOURCE_MEM) | |
863 | offset = hose->pci_mem_offset; | |
864 | ||
865 | region->start = (res->start - offset) & mask; | |
866 | region->end = (res->end - offset) & mask; | |
867 | } | |
868 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
869 | ||
870 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
871 | struct pci_bus_region *region) | |
872 | { | |
873 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
874 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
875 | ||
876 | if (!hose) | |
877 | return; | |
878 | if (res->flags & IORESOURCE_IO) { | |
879 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
880 | mask = 0xffffffffu; | |
881 | } else if (res->flags & IORESOURCE_MEM) | |
882 | offset = hose->pci_mem_offset; | |
883 | res->start = (region->start + offset) & mask; | |
884 | res->end = (region->end + offset) & mask; | |
885 | } | |
886 | EXPORT_SYMBOL(pcibios_bus_to_resource); | |
bf5e2ba2 BH |
887 | |
888 | /* Fixup a bus resource into a linux resource */ | |
889 | static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) | |
890 | { | |
891 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
892 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
893 | ||
894 | if (res->flags & IORESOURCE_IO) { | |
895 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
896 | mask = 0xffffffffu; | |
897 | } else if (res->flags & IORESOURCE_MEM) | |
898 | offset = hose->pci_mem_offset; | |
899 | ||
900 | res->start = (res->start + offset) & mask; | |
901 | res->end = (res->end + offset) & mask; | |
bf5e2ba2 BH |
902 | } |
903 | ||
904 | ||
905 | /* This header fixup will do the resource fixup for all devices as they are | |
906 | * probed, but not for bridge ranges | |
907 | */ | |
908 | static void __devinit pcibios_fixup_resources(struct pci_dev *dev) | |
909 | { | |
910 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
911 | int i; | |
912 | ||
913 | if (!hose) { | |
914 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
915 | pci_name(dev)); | |
916 | return; | |
917 | } | |
918 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
919 | struct resource *res = dev->resource + i; | |
920 | if (!res->flags) | |
921 | continue; | |
7f172890 BH |
922 | /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't |
923 | * consider 0 as an unassigned BAR value. It's technically | |
924 | * a valid value, but linux doesn't like it... so when we can | |
925 | * re-assign things, we do so, but if we can't, we keep it | |
926 | * around and hope for the best... | |
927 | */ | |
928 | if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { | |
bf5e2ba2 BH |
929 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", |
930 | pci_name(dev), i, | |
931 | (unsigned long long)res->start, | |
932 | (unsigned long long)res->end, | |
933 | (unsigned int)res->flags); | |
934 | res->end -= res->start; | |
935 | res->start = 0; | |
936 | res->flags |= IORESOURCE_UNSET; | |
937 | continue; | |
938 | } | |
939 | ||
940 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", | |
941 | pci_name(dev), i, | |
942 | (unsigned long long)res->start,\ | |
943 | (unsigned long long)res->end, | |
944 | (unsigned int)res->flags); | |
945 | ||
946 | fixup_resource(res, dev); | |
b5561511 BH |
947 | |
948 | pr_debug("PCI:%s %016llx-%016llx\n", | |
949 | pci_name(dev), | |
950 | (unsigned long long)res->start, | |
951 | (unsigned long long)res->end); | |
bf5e2ba2 BH |
952 | } |
953 | ||
954 | /* Call machine specific resource fixup */ | |
955 | if (ppc_md.pcibios_fixup_resources) | |
956 | ppc_md.pcibios_fixup_resources(dev); | |
957 | } | |
958 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
959 | ||
b5561511 BH |
960 | /* This function tries to figure out if a bridge resource has been initialized |
961 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
962 | * things go more smoothly when it gets it right. It should covers cases such | |
963 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
964 | */ | |
965 | static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, | |
966 | struct resource *res) | |
bf5e2ba2 | 967 | { |
be8cbcd8 | 968 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 969 | struct pci_dev *dev = bus->self; |
b5561511 BH |
970 | resource_size_t offset; |
971 | u16 command; | |
972 | int i; | |
bf5e2ba2 | 973 | |
b5561511 BH |
974 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
975 | if (ppc_pci_flags & PPC_PCI_PROBE_ONLY) | |
976 | return 0; | |
bf5e2ba2 | 977 | |
b5561511 BH |
978 | /* Job is a bit different between memory and IO */ |
979 | if (res->flags & IORESOURCE_MEM) { | |
980 | /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been | |
981 | * initialized by somebody | |
982 | */ | |
983 | if (res->start != hose->pci_mem_offset) | |
984 | return 0; | |
bf5e2ba2 | 985 | |
b5561511 BH |
986 | /* The BAR is 0, let's check if memory decoding is enabled on |
987 | * the bridge. If not, we consider it unassigned | |
988 | */ | |
989 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
990 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
991 | return 1; | |
be8cbcd8 | 992 | |
b5561511 BH |
993 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
994 | * resources covers that starting address (0 then it's good enough for | |
995 | * us for memory | |
996 | */ | |
997 | for (i = 0; i < 3; i++) { | |
998 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
999 | hose->mem_resources[i].start == hose->pci_mem_offset) | |
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | /* Well, it starts at 0 and we know it will collide so we may as | |
1004 | * well consider it as unassigned. That covers the Apple case. | |
1005 | */ | |
1006 | return 1; | |
1007 | } else { | |
1008 | /* If the BAR is non-0, then we consider it assigned */ | |
1009 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1010 | if (((res->start - offset) & 0xfffffffful) != 0) | |
1011 | return 0; | |
1012 | ||
1013 | /* Here, we are a bit different than memory as typically IO space | |
1014 | * starting at low addresses -is- valid. What we do instead if that | |
1015 | * we consider as unassigned anything that doesn't have IO enabled | |
1016 | * in the PCI command register, and that's it. | |
1017 | */ | |
1018 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1019 | if (command & PCI_COMMAND_IO) | |
1020 | return 0; | |
1021 | ||
1022 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
1023 | * it unassigned | |
1024 | */ | |
1025 | return 1; | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | /* Fixup resources of a PCI<->PCI bridge */ | |
1030 | static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) | |
1031 | { | |
1032 | struct resource *res; | |
1033 | int i; | |
1034 | ||
1035 | struct pci_dev *dev = bus->self; | |
1036 | ||
89a74ecc BH |
1037 | pci_bus_for_each_resource(bus, res, i) { |
1038 | if (!res || !res->flags) | |
b5561511 BH |
1039 | continue; |
1040 | if (i >= 3 && bus->self->transparent) | |
1041 | continue; | |
1042 | ||
1043 | pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", | |
1044 | pci_name(dev), i, | |
1045 | (unsigned long long)res->start,\ | |
1046 | (unsigned long long)res->end, | |
1047 | (unsigned int)res->flags); | |
bf5e2ba2 | 1048 | |
b5561511 BH |
1049 | /* Perform fixup */ |
1050 | fixup_resource(res, dev); | |
1051 | ||
1052 | /* Try to detect uninitialized P2P bridge resources, | |
1053 | * and clear them out so they get re-assigned later | |
1054 | */ | |
1055 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
1056 | res->flags = 0; | |
1057 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
1058 | } else { | |
1059 | ||
1060 | pr_debug("PCI:%s %016llx-%016llx\n", | |
1061 | pci_name(dev), | |
1062 | (unsigned long long)res->start, | |
1063 | (unsigned long long)res->end); | |
bf5e2ba2 BH |
1064 | } |
1065 | } | |
b5561511 BH |
1066 | } |
1067 | ||
8b8da358 BH |
1068 | void __devinit pcibios_setup_bus_self(struct pci_bus *bus) |
1069 | { | |
7eef440a | 1070 | /* Fix up the bus resources for P2P bridges */ |
8b8da358 BH |
1071 | if (bus->self != NULL) |
1072 | pcibios_fixup_bridge(bus); | |
1073 | ||
1074 | /* Platform specific bus fixups. This is currently only used | |
7eef440a | 1075 | * by fsl_pci and I'm hoping to get rid of it at some point |
8b8da358 BH |
1076 | */ |
1077 | if (ppc_md.pcibios_fixup_bus) | |
1078 | ppc_md.pcibios_fixup_bus(bus); | |
1079 | ||
1080 | /* Setup bus DMA mappings */ | |
1081 | if (ppc_md.pci_dma_bus_setup) | |
1082 | ppc_md.pci_dma_bus_setup(bus); | |
1083 | } | |
1084 | ||
7eef440a BH |
1085 | void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) |
1086 | { | |
1087 | struct pci_dev *dev; | |
1088 | ||
1089 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
1090 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
1091 | ||
1092 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1093 | struct dev_archdata *sd = &dev->dev.archdata; | |
1094 | ||
2d1c8618 BH |
1095 | /* Cardbus can call us to add new devices to a bus, so ignore |
1096 | * those who are already fully discovered | |
1097 | */ | |
1098 | if (dev->is_added) | |
1099 | continue; | |
1100 | ||
d706c1b0 | 1101 | /* Setup OF node pointer in the device */ |
d706c1b0 | 1102 | dev->dev.of_node = pci_device_to_OF_node(dev); |
7eef440a BH |
1103 | |
1104 | /* Fixup NUMA node as it may not be setup yet by the generic | |
1105 | * code and is needed by the DMA init | |
1106 | */ | |
1107 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
1108 | ||
1109 | /* Hook up default DMA ops */ | |
1110 | sd->dma_ops = pci_dma_ops; | |
738ef42e | 1111 | set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); |
7eef440a BH |
1112 | |
1113 | /* Additional platform DMA/iommu setup */ | |
1114 | if (ppc_md.pci_dma_dev_setup) | |
1115 | ppc_md.pci_dma_dev_setup(dev); | |
1116 | ||
1117 | /* Read default IRQs and fixup if necessary */ | |
1118 | pci_read_irq_line(dev); | |
1119 | if (ppc_md.pci_irq_fixup) | |
1120 | ppc_md.pci_irq_fixup(dev); | |
1121 | } | |
1122 | } | |
1123 | ||
bf5e2ba2 BH |
1124 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
1125 | { | |
1126 | /* When called from the generic PCI probe, read PCI<->PCI bridge | |
7eef440a | 1127 | * bases. This is -not- called when generating the PCI tree from |
8b8da358 | 1128 | * the OF device-tree. |
bf5e2ba2 BH |
1129 | */ |
1130 | if (bus->self != NULL) | |
1131 | pci_read_bridge_bases(bus); | |
bf5e2ba2 | 1132 | |
8b8da358 BH |
1133 | /* Now fixup the bus bus */ |
1134 | pcibios_setup_bus_self(bus); | |
1135 | ||
1136 | /* Now fixup devices on that bus */ | |
1137 | pcibios_setup_bus_devices(bus); | |
bf5e2ba2 | 1138 | } |
8b8da358 | 1139 | EXPORT_SYMBOL(pcibios_fixup_bus); |
3fd94c6b | 1140 | |
2d1c8618 BH |
1141 | void __devinit pci_fixup_cardbus(struct pci_bus *bus) |
1142 | { | |
1143 | /* Now fixup devices on that bus */ | |
1144 | pcibios_setup_bus_devices(bus); | |
1145 | } | |
1146 | ||
1147 | ||
3fd94c6b BH |
1148 | static int skip_isa_ioresource_align(struct pci_dev *dev) |
1149 | { | |
1150 | if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && | |
1151 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) | |
1152 | return 1; | |
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | /* | |
1157 | * We need to avoid collisions with `mirrored' VGA ports | |
1158 | * and other strange ISA hardware, so we always want the | |
1159 | * addresses to be allocated in the 0x000-0x0ff region | |
1160 | * modulo 0x400. | |
1161 | * | |
1162 | * Why? Because some silly external IO cards only decode | |
1163 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1164 | * is reserved for motherboard devices that decode all 16 | |
1165 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1166 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1167 | * which might have be mirrored at 0x0100-0x03ff.. | |
1168 | */ | |
3b7a17fc | 1169 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
3fd94c6b BH |
1170 | resource_size_t size, resource_size_t align) |
1171 | { | |
1172 | struct pci_dev *dev = data; | |
b26b2d49 | 1173 | resource_size_t start = res->start; |
3fd94c6b BH |
1174 | |
1175 | if (res->flags & IORESOURCE_IO) { | |
3fd94c6b | 1176 | if (skip_isa_ioresource_align(dev)) |
b26b2d49 DB |
1177 | return start; |
1178 | if (start & 0x300) | |
3fd94c6b | 1179 | start = (start + 0x3ff) & ~0x3ff; |
3fd94c6b | 1180 | } |
b26b2d49 DB |
1181 | |
1182 | return start; | |
3fd94c6b BH |
1183 | } |
1184 | EXPORT_SYMBOL(pcibios_align_resource); | |
1185 | ||
1186 | /* | |
1187 | * Reparent resource children of pr that conflict with res | |
1188 | * under res, and make res replace those children. | |
1189 | */ | |
0f6023d5 | 1190 | static int reparent_resources(struct resource *parent, |
3fd94c6b BH |
1191 | struct resource *res) |
1192 | { | |
1193 | struct resource *p, **pp; | |
1194 | struct resource **firstpp = NULL; | |
1195 | ||
1196 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1197 | if (p->end < res->start) | |
1198 | continue; | |
1199 | if (res->end < p->start) | |
1200 | break; | |
1201 | if (p->start < res->start || p->end > res->end) | |
1202 | return -1; /* not completely contained */ | |
1203 | if (firstpp == NULL) | |
1204 | firstpp = pp; | |
1205 | } | |
1206 | if (firstpp == NULL) | |
1207 | return -1; /* didn't find any conflicting entries? */ | |
1208 | res->parent = parent; | |
1209 | res->child = *firstpp; | |
1210 | res->sibling = *pp; | |
1211 | *firstpp = res; | |
1212 | *pp = NULL; | |
1213 | for (p = res->child; p != NULL; p = p->sibling) { | |
1214 | p->parent = res; | |
b0494bc8 BH |
1215 | pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", |
1216 | p->name, | |
1217 | (unsigned long long)p->start, | |
1218 | (unsigned long long)p->end, res->name); | |
3fd94c6b BH |
1219 | } |
1220 | return 0; | |
1221 | } | |
1222 | ||
1223 | /* | |
1224 | * Handle resources of PCI devices. If the world were perfect, we could | |
1225 | * just allocate all the resource regions and do nothing more. It isn't. | |
1226 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1227 | * require us to know lots of host bridge internals. So we attempt to | |
1228 | * keep as much of the original configuration as possible, but tweak it | |
1229 | * when it's found to be wrong. | |
1230 | * | |
1231 | * Known BIOS problems we have to work around: | |
1232 | * - I/O or memory regions not configured | |
1233 | * - regions configured, but not enabled in the command register | |
1234 | * - bogus I/O addresses above 64K used | |
1235 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1236 | * the fact the PCI specs explicitly allow address decoders to be | |
1237 | * shared between expansion ROMs and other resource regions, it's | |
1238 | * at least dangerous) | |
1239 | * | |
1240 | * Our solution: | |
1241 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1242 | * This gives us fixed barriers on where we can allocate. | |
1243 | * (2) Allocate resources for all enabled devices. If there is | |
1244 | * a collision, just mark the resource as unallocated. Also | |
1245 | * disable expansion ROMs during this step. | |
1246 | * (3) Try to allocate resources for disabled devices. If the | |
1247 | * resources were assigned correctly, everything goes well, | |
1248 | * if they weren't, they won't disturb allocation of other | |
1249 | * resources. | |
1250 | * (4) Assign new addresses to resources which were either | |
1251 | * not configured at all or misconfigured. If explicitly | |
1252 | * requested by the user, configure expansion ROM address | |
1253 | * as well. | |
1254 | */ | |
1255 | ||
e90a1318 | 1256 | void pcibios_allocate_bus_resources(struct pci_bus *bus) |
3fd94c6b | 1257 | { |
e90a1318 | 1258 | struct pci_bus *b; |
3fd94c6b BH |
1259 | int i; |
1260 | struct resource *res, *pr; | |
1261 | ||
b5ae5f91 BH |
1262 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
1263 | pci_domain_nr(bus), bus->number); | |
1264 | ||
89a74ecc BH |
1265 | pci_bus_for_each_resource(bus, res, i) { |
1266 | if (!res || !res->flags || res->start > res->end || res->parent) | |
e90a1318 NF |
1267 | continue; |
1268 | if (bus->parent == NULL) | |
1269 | pr = (res->flags & IORESOURCE_IO) ? | |
1270 | &ioport_resource : &iomem_resource; | |
1271 | else { | |
1272 | /* Don't bother with non-root busses when | |
1273 | * re-assigning all resources. We clear the | |
1274 | * resource flags as if they were colliding | |
1275 | * and as such ensure proper re-allocation | |
1276 | * later. | |
1277 | */ | |
1278 | if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) | |
1279 | goto clear_resource; | |
1280 | pr = pci_find_parent_resource(bus->self, res); | |
1281 | if (pr == res) { | |
1282 | /* this happens when the generic PCI | |
1283 | * code (wrongly) decides that this | |
1284 | * bridge is transparent -- paulus | |
3fd94c6b | 1285 | */ |
e90a1318 | 1286 | continue; |
3fd94c6b | 1287 | } |
e90a1318 | 1288 | } |
3fd94c6b | 1289 | |
b0494bc8 BH |
1290 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " |
1291 | "[0x%x], parent %p (%s)\n", | |
1292 | bus->self ? pci_name(bus->self) : "PHB", | |
1293 | bus->number, i, | |
1294 | (unsigned long long)res->start, | |
1295 | (unsigned long long)res->end, | |
1296 | (unsigned int)res->flags, | |
1297 | pr, (pr && pr->name) ? pr->name : "nil"); | |
e90a1318 NF |
1298 | |
1299 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
1300 | if (request_resource(pr, res) == 0) | |
1301 | continue; | |
1302 | /* | |
1303 | * Must be a conflict with an existing entry. | |
1304 | * Move that entry (or entries) under the | |
1305 | * bridge resource and try again. | |
1306 | */ | |
1307 | if (reparent_resources(pr, res) == 0) | |
1308 | continue; | |
3fd94c6b | 1309 | } |
e90a1318 NF |
1310 | printk(KERN_WARNING "PCI: Cannot allocate resource region " |
1311 | "%d of PCI bridge %d, will remap\n", i, bus->number); | |
1312 | clear_resource: | |
837c4ef1 | 1313 | res->start = res->end = 0; |
e90a1318 | 1314 | res->flags = 0; |
3fd94c6b | 1315 | } |
e90a1318 NF |
1316 | |
1317 | list_for_each_entry(b, &bus->children, node) | |
1318 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1319 | } |
1320 | ||
533b1928 | 1321 | static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1322 | { |
1323 | struct resource *pr, *r = &dev->resource[idx]; | |
1324 | ||
b0494bc8 BH |
1325 | pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", |
1326 | pci_name(dev), idx, | |
1327 | (unsigned long long)r->start, | |
1328 | (unsigned long long)r->end, | |
1329 | (unsigned int)r->flags); | |
3fd94c6b BH |
1330 | |
1331 | pr = pci_find_parent_resource(dev, r); | |
1332 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1333 | request_resource(pr, r) < 0) { | |
1334 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1335 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1336 | if (pr) | |
b0494bc8 BH |
1337 | pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", |
1338 | pr, | |
1339 | (unsigned long long)pr->start, | |
1340 | (unsigned long long)pr->end, | |
1341 | (unsigned int)pr->flags); | |
3fd94c6b BH |
1342 | /* We'll assign a new address later */ |
1343 | r->flags |= IORESOURCE_UNSET; | |
1344 | r->end -= r->start; | |
1345 | r->start = 0; | |
1346 | } | |
1347 | } | |
1348 | ||
1349 | static void __init pcibios_allocate_resources(int pass) | |
1350 | { | |
1351 | struct pci_dev *dev = NULL; | |
1352 | int idx, disabled; | |
1353 | u16 command; | |
1354 | struct resource *r; | |
1355 | ||
1356 | for_each_pci_dev(dev) { | |
1357 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
ad892a63 | 1358 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { |
3fd94c6b BH |
1359 | r = &dev->resource[idx]; |
1360 | if (r->parent) /* Already allocated */ | |
1361 | continue; | |
1362 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1363 | continue; /* Not assigned at all */ | |
ad892a63 BH |
1364 | /* We only allocate ROMs on pass 1 just in case they |
1365 | * have been screwed up by firmware | |
1366 | */ | |
1367 | if (idx == PCI_ROM_RESOURCE ) | |
1368 | disabled = 1; | |
3fd94c6b BH |
1369 | if (r->flags & IORESOURCE_IO) |
1370 | disabled = !(command & PCI_COMMAND_IO); | |
1371 | else | |
1372 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1373 | if (pass == disabled) |
1374 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1375 | } |
1376 | if (pass) | |
1377 | continue; | |
1378 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
ad892a63 | 1379 | if (r->flags) { |
3fd94c6b BH |
1380 | /* Turn the ROM off, leave the resource region, |
1381 | * but keep it unregistered. | |
1382 | */ | |
1383 | u32 reg; | |
3fd94c6b | 1384 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
ad892a63 BH |
1385 | if (reg & PCI_ROM_ADDRESS_ENABLE) { |
1386 | pr_debug("PCI: Switching off ROM of %s\n", | |
1387 | pci_name(dev)); | |
1388 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1389 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1390 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1391 | } | |
3fd94c6b BH |
1392 | } |
1393 | } | |
1394 | } | |
1395 | ||
c1f34302 BH |
1396 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) |
1397 | { | |
1398 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1399 | resource_size_t offset; | |
1400 | struct resource *res, *pres; | |
1401 | int i; | |
1402 | ||
1403 | pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); | |
1404 | ||
1405 | /* Check for IO */ | |
1406 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1407 | goto no_io; | |
1408 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1409 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1410 | BUG_ON(res == NULL); | |
1411 | res->name = "Legacy IO"; | |
1412 | res->flags = IORESOURCE_IO; | |
1413 | res->start = offset; | |
1414 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1415 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1416 | if (request_resource(&hose->io_resource, res)) { | |
1417 | printk(KERN_DEBUG | |
1418 | "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", | |
1419 | pci_domain_nr(bus), bus->number, res); | |
1420 | kfree(res); | |
1421 | } | |
1422 | ||
1423 | no_io: | |
1424 | /* Check for memory */ | |
1425 | offset = hose->pci_mem_offset; | |
1426 | pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); | |
1427 | for (i = 0; i < 3; i++) { | |
1428 | pres = &hose->mem_resources[i]; | |
1429 | if (!(pres->flags & IORESOURCE_MEM)) | |
1430 | continue; | |
1431 | pr_debug("hose mem res: %pR\n", pres); | |
1432 | if ((pres->start - offset) <= 0xa0000 && | |
1433 | (pres->end - offset) >= 0xbffff) | |
1434 | break; | |
1435 | } | |
1436 | if (i >= 3) | |
1437 | return; | |
1438 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1439 | BUG_ON(res == NULL); | |
1440 | res->name = "Legacy VGA memory"; | |
1441 | res->flags = IORESOURCE_MEM; | |
1442 | res->start = 0xa0000 + offset; | |
1443 | res->end = 0xbffff + offset; | |
1444 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1445 | if (request_resource(pres, res)) { | |
1446 | printk(KERN_DEBUG | |
1447 | "PCI %04x:%02x Cannot reserve VGA memory %pR\n", | |
1448 | pci_domain_nr(bus), bus->number, res); | |
1449 | kfree(res); | |
1450 | } | |
1451 | } | |
1452 | ||
3fd94c6b BH |
1453 | void __init pcibios_resource_survey(void) |
1454 | { | |
e90a1318 NF |
1455 | struct pci_bus *b; |
1456 | ||
3fd94c6b BH |
1457 | /* Allocate and assign resources. If we re-assign everything, then |
1458 | * we skip the allocate phase | |
1459 | */ | |
e90a1318 NF |
1460 | list_for_each_entry(b, &pci_root_buses, node) |
1461 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1462 | |
1463 | if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { | |
1464 | pcibios_allocate_resources(0); | |
1465 | pcibios_allocate_resources(1); | |
1466 | } | |
1467 | ||
c1f34302 BH |
1468 | /* Before we start assigning unassigned resource, we try to reserve |
1469 | * the low IO area and the VGA memory area if they intersect the | |
1470 | * bus available resources to avoid allocating things on top of them | |
1471 | */ | |
1472 | if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { | |
1473 | list_for_each_entry(b, &pci_root_buses, node) | |
1474 | pcibios_reserve_legacy_regions(b); | |
1475 | } | |
1476 | ||
1477 | /* Now, if the platform didn't decide to blindly trust the firmware, | |
1478 | * we proceed to assigning things that were left unassigned | |
1479 | */ | |
3fd94c6b | 1480 | if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { |
a77acda0 | 1481 | pr_debug("PCI: Assigning unassigned resources...\n"); |
3fd94c6b BH |
1482 | pci_assign_unassigned_resources(); |
1483 | } | |
1484 | ||
1485 | /* Call machine dependent fixup */ | |
1486 | if (ppc_md.pcibios_fixup) | |
1487 | ppc_md.pcibios_fixup(); | |
1488 | } | |
1489 | ||
1490 | #ifdef CONFIG_HOTPLUG | |
8b8da358 | 1491 | |
fd6852c8 | 1492 | /* This is used by the PCI hotplug driver to allocate resource |
3fd94c6b | 1493 | * of newly plugged busses. We can try to consolidate with the |
fd6852c8 BH |
1494 | * rest of the code later, for now, keep it as-is as our main |
1495 | * resource allocation function doesn't deal with sub-trees yet. | |
3fd94c6b | 1496 | */ |
baf75b0a | 1497 | void pcibios_claim_one_bus(struct pci_bus *bus) |
3fd94c6b BH |
1498 | { |
1499 | struct pci_dev *dev; | |
1500 | struct pci_bus *child_bus; | |
1501 | ||
1502 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1503 | int i; | |
1504 | ||
1505 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1506 | struct resource *r = &dev->resource[i]; | |
1507 | ||
1508 | if (r->parent || !r->start || !r->flags) | |
1509 | continue; | |
fd6852c8 BH |
1510 | |
1511 | pr_debug("PCI: Claiming %s: " | |
1512 | "Resource %d: %016llx..%016llx [%x]\n", | |
1513 | pci_name(dev), i, | |
1514 | (unsigned long long)r->start, | |
1515 | (unsigned long long)r->end, | |
1516 | (unsigned int)r->flags); | |
1517 | ||
3fd94c6b BH |
1518 | pci_claim_resource(dev, i); |
1519 | } | |
1520 | } | |
1521 | ||
1522 | list_for_each_entry(child_bus, &bus->children, node) | |
1523 | pcibios_claim_one_bus(child_bus); | |
1524 | } | |
fd6852c8 BH |
1525 | |
1526 | ||
1527 | /* pcibios_finish_adding_to_bus | |
1528 | * | |
1529 | * This is to be called by the hotplug code after devices have been | |
1530 | * added to a bus, this include calling it for a PHB that is just | |
1531 | * being added | |
1532 | */ | |
1533 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1534 | { | |
1535 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1536 | pci_domain_nr(bus), bus->number); | |
1537 | ||
1538 | /* Allocate bus and devices resources */ | |
1539 | pcibios_allocate_bus_resources(bus); | |
1540 | pcibios_claim_one_bus(bus); | |
1541 | ||
1542 | /* Add new devices to global lists. Register in proc, sysfs. */ | |
1543 | pci_bus_add_devices(bus); | |
1544 | ||
1545 | /* Fixup EEH */ | |
1546 | eeh_add_device_tree_late(bus); | |
1547 | } | |
1548 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1549 | ||
3fd94c6b | 1550 | #endif /* CONFIG_HOTPLUG */ |
549beb9b BH |
1551 | |
1552 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
1553 | { | |
549beb9b BH |
1554 | if (ppc_md.pcibios_enable_device_hook) |
1555 | if (ppc_md.pcibios_enable_device_hook(dev)) | |
1556 | return -EINVAL; | |
1557 | ||
7cfb5f9a | 1558 | return pci_enable_resources(dev, mask); |
549beb9b | 1559 | } |
53280323 BH |
1560 | |
1561 | void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) | |
1562 | { | |
1563 | struct pci_bus *bus = hose->bus; | |
1564 | struct resource *res; | |
1565 | int i; | |
1566 | ||
1567 | /* Hookup PHB IO resource */ | |
1568 | bus->resource[0] = res = &hose->io_resource; | |
1569 | ||
1570 | if (!res->flags) { | |
1571 | printk(KERN_WARNING "PCI: I/O resource not set for host" | |
1572 | " bridge %s (domain %d)\n", | |
1573 | hose->dn->full_name, hose->global_number); | |
1574 | #ifdef CONFIG_PPC32 | |
1575 | /* Workaround for lack of IO resource only on 32-bit */ | |
1576 | res->start = (unsigned long)hose->io_base_virt - isa_io_base; | |
1577 | res->end = res->start + IO_SPACE_LIMIT; | |
1578 | res->flags = IORESOURCE_IO; | |
1579 | #endif /* CONFIG_PPC32 */ | |
1580 | } | |
1581 | ||
1582 | pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", | |
1583 | (unsigned long long)res->start, | |
1584 | (unsigned long long)res->end, | |
1585 | (unsigned long)res->flags); | |
1586 | ||
1587 | /* Hookup PHB Memory resources */ | |
1588 | for (i = 0; i < 3; ++i) { | |
1589 | res = &hose->mem_resources[i]; | |
1590 | if (!res->flags) { | |
1591 | if (i > 0) | |
1592 | continue; | |
1593 | printk(KERN_ERR "PCI: Memory resource 0 not set for " | |
1594 | "host bridge %s (domain %d)\n", | |
1595 | hose->dn->full_name, hose->global_number); | |
1596 | #ifdef CONFIG_PPC32 | |
1597 | /* Workaround for lack of MEM resource only on 32-bit */ | |
1598 | res->start = hose->pci_mem_offset; | |
1599 | res->end = (resource_size_t)-1LL; | |
1600 | res->flags = IORESOURCE_MEM; | |
1601 | #endif /* CONFIG_PPC32 */ | |
1602 | } | |
1603 | bus->resource[i+1] = res; | |
1604 | ||
1605 | pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, | |
1606 | (unsigned long long)res->start, | |
1607 | (unsigned long long)res->end, | |
1608 | (unsigned long)res->flags); | |
1609 | } | |
1610 | ||
1611 | pr_debug("PCI: PHB MEM offset = %016llx\n", | |
1612 | (unsigned long long)hose->pci_mem_offset); | |
1613 | pr_debug("PCI: PHB IO offset = %08lx\n", | |
1614 | (unsigned long)hose->io_base_virt - _IO_BASE); | |
1615 | ||
1616 | } | |
89c2dd62 KG |
1617 | |
1618 | /* | |
1619 | * Null PCI config access functions, for the case when we can't | |
1620 | * find a hose. | |
1621 | */ | |
1622 | #define NULL_PCI_OP(rw, size, type) \ | |
1623 | static int \ | |
1624 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1625 | { \ | |
1626 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1627 | } | |
1628 | ||
1629 | static int | |
1630 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1631 | int len, u32 *val) | |
1632 | { | |
1633 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1634 | } | |
1635 | ||
1636 | static int | |
1637 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1638 | int len, u32 val) | |
1639 | { | |
1640 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1641 | } | |
1642 | ||
1643 | static struct pci_ops null_pci_ops = | |
1644 | { | |
1645 | .read = null_read_config, | |
1646 | .write = null_write_config, | |
1647 | }; | |
1648 | ||
1649 | /* | |
1650 | * These functions are used early on before PCI scanning is done | |
1651 | * and all of the pci_dev and pci_bus structures have been created. | |
1652 | */ | |
1653 | static struct pci_bus * | |
1654 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1655 | { | |
1656 | static struct pci_bus bus; | |
1657 | ||
1658 | if (hose == 0) { | |
1659 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); | |
1660 | } | |
1661 | bus.number = busnr; | |
1662 | bus.sysdata = hose; | |
1663 | bus.ops = hose? hose->ops: &null_pci_ops; | |
1664 | return &bus; | |
1665 | } | |
1666 | ||
1667 | #define EARLY_PCI_OP(rw, size, type) \ | |
1668 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1669 | int devfn, int offset, type value) \ | |
1670 | { \ | |
1671 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1672 | devfn, offset, value); \ | |
1673 | } | |
1674 | ||
1675 | EARLY_PCI_OP(read, byte, u8 *) | |
1676 | EARLY_PCI_OP(read, word, u16 *) | |
1677 | EARLY_PCI_OP(read, dword, u32 *) | |
1678 | EARLY_PCI_OP(write, byte, u8) | |
1679 | EARLY_PCI_OP(write, word, u16) | |
1680 | EARLY_PCI_OP(write, dword, u32) | |
1681 | ||
1682 | extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); | |
1683 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, | |
1684 | int cap) | |
1685 | { | |
1686 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1687 | } | |
0ed2c722 GL |
1688 | |
1689 | /** | |
1690 | * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus | |
1691 | * @hose: Pointer to the PCI host controller instance structure | |
1692 | * @sysdata: value to use for sysdata pointer. ppc32 and ppc64 differ here | |
1693 | * | |
1694 | * Note: the 'data' pointer is a temporary measure. As 32 and 64 bit | |
1695 | * pci code gets merged, this parameter should become unnecessary because | |
1696 | * both will use the same value. | |
1697 | */ | |
1698 | void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata) | |
1699 | { | |
1700 | struct pci_bus *bus; | |
1701 | struct device_node *node = hose->dn; | |
1702 | int mode; | |
1703 | ||
1704 | pr_debug("PCI: Scanning PHB %s\n", | |
1705 | node ? node->full_name : "<NO NAME>"); | |
1706 | ||
1707 | /* Create an empty bus for the toplevel */ | |
1708 | bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, | |
1709 | sysdata); | |
1710 | if (bus == NULL) { | |
1711 | pr_err("Failed to create bus for PCI domain %04x\n", | |
1712 | hose->global_number); | |
1713 | return; | |
1714 | } | |
1715 | bus->secondary = hose->first_busno; | |
1716 | hose->bus = bus; | |
1717 | ||
1718 | /* Get some IO space for the new PHB */ | |
1719 | pcibios_setup_phb_io_space(hose); | |
1720 | ||
1721 | /* Wire up PHB bus resources */ | |
1722 | pcibios_setup_phb_resources(hose); | |
1723 | ||
1724 | /* Get probe mode and perform scan */ | |
1725 | mode = PCI_PROBE_NORMAL; | |
1726 | if (node && ppc_md.pci_probe_mode) | |
1727 | mode = ppc_md.pci_probe_mode(bus); | |
1728 | pr_debug(" probe mode: %d\n", mode); | |
1729 | if (mode == PCI_PROBE_DEVTREE) { | |
1730 | bus->subordinate = hose->last_busno; | |
1731 | of_scan_bus(node, bus); | |
1732 | } | |
1733 | ||
1734 | if (mode == PCI_PROBE_NORMAL) | |
1735 | hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); | |
1736 | } |