Commit | Line | Data |
---|---|---|
5516b540 KG |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
3 | * (based on pci_32.c and pci_64.c) |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
5516b540 KG |
19 | #include <linux/kernel.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/bootmem.h> | |
66b15db6 | 24 | #include <linux/export.h> |
22ae782f | 25 | #include <linux/of_address.h> |
04bea68b | 26 | #include <linux/of_pci.h> |
5516b540 KG |
27 | #include <linux/mm.h> |
28 | #include <linux/list.h> | |
29 | #include <linux/syscalls.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
c2e1d845 | 33 | #include <linux/vgaarb.h> |
5516b540 KG |
34 | |
35 | #include <asm/processor.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/prom.h> | |
38 | #include <asm/pci-bridge.h> | |
39 | #include <asm/byteorder.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/ppc-pci.h> | |
8b8da358 | 42 | #include <asm/eeh.h> |
5516b540 | 43 | |
a4c9e328 | 44 | static DEFINE_SPINLOCK(hose_spinlock); |
c3bd517d | 45 | LIST_HEAD(hose_list); |
a4c9e328 KG |
46 | |
47 | /* XXX kill that some day ... */ | |
ebfc00f7 | 48 | static int global_phb_number; /* Global phb counter */ |
a4c9e328 | 49 | |
25e81f92 BH |
50 | /* ISA Memory physical address */ |
51 | resource_size_t isa_mem_base; | |
52 | ||
a4c9e328 | 53 | |
45223c54 | 54 | static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; |
4fc665b8 | 55 | |
45223c54 | 56 | void set_pci_dma_ops(struct dma_map_ops *dma_ops) |
4fc665b8 BB |
57 | { |
58 | pci_dma_ops = dma_ops; | |
59 | } | |
60 | ||
45223c54 | 61 | struct dma_map_ops *get_pci_dma_ops(void) |
4fc665b8 BB |
62 | { |
63 | return pci_dma_ops; | |
64 | } | |
65 | EXPORT_SYMBOL(get_pci_dma_ops); | |
66 | ||
e60516e3 | 67 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
68 | { |
69 | struct pci_controller *phb; | |
70 | ||
e60516e3 | 71 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
72 | if (phb == NULL) |
73 | return NULL; | |
e60516e3 SR |
74 | spin_lock(&hose_spinlock); |
75 | phb->global_number = global_phb_number++; | |
76 | list_add_tail(&phb->list_node, &hose_list); | |
77 | spin_unlock(&hose_spinlock); | |
44ef3390 | 78 | phb->dn = dev; |
a4c9e328 KG |
79 | phb->is_dynamic = mem_init_done; |
80 | #ifdef CONFIG_PPC64 | |
81 | if (dev) { | |
82 | int nid = of_node_to_nid(dev); | |
83 | ||
84 | if (nid < 0 || !node_online(nid)) | |
85 | nid = -1; | |
86 | ||
87 | PHB_SET_NODE(phb, nid); | |
88 | } | |
89 | #endif | |
90 | return phb; | |
91 | } | |
92 | ||
93 | void pcibios_free_controller(struct pci_controller *phb) | |
94 | { | |
95 | spin_lock(&hose_spinlock); | |
96 | list_del(&phb->list_node); | |
97 | spin_unlock(&hose_spinlock); | |
98 | ||
99 | if (phb->is_dynamic) | |
100 | kfree(phb); | |
101 | } | |
102 | ||
4c2245bb GS |
103 | /* |
104 | * The function is used to return the minimal alignment | |
105 | * for memory or I/O windows of the associated P2P bridge. | |
106 | * By default, 4KiB alignment for I/O windows and 1MiB for | |
107 | * memory windows. | |
108 | */ | |
109 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, | |
110 | unsigned long type) | |
111 | { | |
112 | if (ppc_md.pcibios_window_alignment) | |
113 | return ppc_md.pcibios_window_alignment(bus, type); | |
114 | ||
115 | /* | |
116 | * PCI core will figure out the default | |
117 | * alignment: 4KiB for I/O and 1MiB for | |
118 | * memory window. | |
119 | */ | |
120 | return 1; | |
121 | } | |
122 | ||
c3bd517d MM |
123 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) |
124 | { | |
125 | #ifdef CONFIG_PPC64 | |
126 | return hose->pci_io_size; | |
127 | #else | |
28f65c11 | 128 | return resource_size(&hose->io_resource); |
c3bd517d MM |
129 | #endif |
130 | } | |
131 | ||
6dfbde20 BH |
132 | int pcibios_vaddr_is_ioport(void __iomem *address) |
133 | { | |
134 | int ret = 0; | |
135 | struct pci_controller *hose; | |
c3bd517d | 136 | resource_size_t size; |
6dfbde20 BH |
137 | |
138 | spin_lock(&hose_spinlock); | |
139 | list_for_each_entry(hose, &hose_list, list_node) { | |
c3bd517d | 140 | size = pcibios_io_size(hose); |
6dfbde20 BH |
141 | if (address >= hose->io_base_virt && |
142 | address < (hose->io_base_virt + size)) { | |
143 | ret = 1; | |
144 | break; | |
145 | } | |
146 | } | |
147 | spin_unlock(&hose_spinlock); | |
148 | return ret; | |
149 | } | |
150 | ||
c3bd517d MM |
151 | unsigned long pci_address_to_pio(phys_addr_t address) |
152 | { | |
153 | struct pci_controller *hose; | |
154 | resource_size_t size; | |
155 | unsigned long ret = ~0; | |
156 | ||
157 | spin_lock(&hose_spinlock); | |
158 | list_for_each_entry(hose, &hose_list, list_node) { | |
159 | size = pcibios_io_size(hose); | |
160 | if (address >= hose->io_base_phys && | |
161 | address < (hose->io_base_phys + size)) { | |
162 | unsigned long base = | |
163 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
164 | ret = base + (address - hose->io_base_phys); | |
165 | break; | |
166 | } | |
167 | } | |
168 | spin_unlock(&hose_spinlock); | |
169 | ||
170 | return ret; | |
171 | } | |
172 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
173 | ||
5516b540 KG |
174 | /* |
175 | * Return the domain number for this bus. | |
176 | */ | |
177 | int pci_domain_nr(struct pci_bus *bus) | |
178 | { | |
6207e816 | 179 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 180 | |
6207e816 | 181 | return hose->global_number; |
5516b540 | 182 | } |
5516b540 | 183 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad | 184 | |
a4c9e328 KG |
185 | /* This routine is meant to be used early during boot, when the |
186 | * PCI bus numbers have not yet been assigned, and you need to | |
187 | * issue PCI config cycles to an OF device. | |
188 | * It could also be used to "fix" RTAS config cycles if you want | |
189 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
190 | * config cycles. | |
191 | */ | |
192 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
193 | { | |
a4c9e328 KG |
194 | while(node) { |
195 | struct pci_controller *hose, *tmp; | |
196 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 197 | if (hose->dn == node) |
a4c9e328 KG |
198 | return hose; |
199 | node = node->parent; | |
200 | } | |
201 | return NULL; | |
202 | } | |
203 | ||
58083dad KG |
204 | static ssize_t pci_show_devspec(struct device *dev, |
205 | struct device_attribute *attr, char *buf) | |
206 | { | |
207 | struct pci_dev *pdev; | |
208 | struct device_node *np; | |
209 | ||
210 | pdev = to_pci_dev (dev); | |
211 | np = pci_device_to_OF_node(pdev); | |
212 | if (np == NULL || np->full_name == NULL) | |
213 | return 0; | |
214 | return sprintf(buf, "%s", np->full_name); | |
215 | } | |
216 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
58083dad KG |
217 | |
218 | /* Add sysfs properties */ | |
4f3731da | 219 | int pcibios_add_platform_entries(struct pci_dev *pdev) |
58083dad | 220 | { |
4f3731da | 221 | return device_create_file(&pdev->dev, &dev_attr_devspec); |
58083dad KG |
222 | } |
223 | ||
58083dad KG |
224 | /* |
225 | * Reads the interrupt pin to determine if interrupt is use by card. | |
226 | * If the interrupt is used, then gets the interrupt line from the | |
227 | * openfirmware and sets it in the pci_dev and pci_config line. | |
228 | */ | |
4666ca2a | 229 | static int pci_read_irq_line(struct pci_dev *pci_dev) |
58083dad KG |
230 | { |
231 | struct of_irq oirq; | |
232 | unsigned int virq; | |
233 | ||
b0494bc8 | 234 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); |
58083dad KG |
235 | |
236 | #ifdef DEBUG | |
237 | memset(&oirq, 0xff, sizeof(oirq)); | |
238 | #endif | |
239 | /* Try to get a mapping from the device-tree */ | |
240 | if (of_irq_map_pci(pci_dev, &oirq)) { | |
241 | u8 line, pin; | |
242 | ||
243 | /* If that fails, lets fallback to what is in the config | |
244 | * space and map that through the default controller. We | |
245 | * also set the type to level low since that's what PCI | |
246 | * interrupts are. If your platform does differently, then | |
247 | * either provide a proper interrupt tree or don't use this | |
248 | * function. | |
249 | */ | |
250 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
251 | return -1; | |
252 | if (pin == 0) | |
253 | return -1; | |
254 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 255 | line == 0xff || line == 0) { |
58083dad KG |
256 | return -1; |
257 | } | |
b0494bc8 BH |
258 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", |
259 | line, pin); | |
58083dad KG |
260 | |
261 | virq = irq_create_mapping(NULL, line); | |
262 | if (virq != NO_IRQ) | |
ec775d0e | 263 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
58083dad | 264 | } else { |
b0494bc8 BH |
265 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
266 | oirq.size, oirq.specifier[0], oirq.specifier[1], | |
74a7f084 | 267 | of_node_full_name(oirq.controller)); |
58083dad KG |
268 | |
269 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
270 | oirq.size); | |
271 | } | |
272 | if(virq == NO_IRQ) { | |
b0494bc8 | 273 | pr_debug(" Failed to map !\n"); |
58083dad KG |
274 | return -1; |
275 | } | |
276 | ||
b0494bc8 | 277 | pr_debug(" Mapped to linux irq %d\n", virq); |
58083dad KG |
278 | |
279 | pci_dev->irq = virq; | |
280 | ||
281 | return 0; | |
282 | } | |
58083dad KG |
283 | |
284 | /* | |
285 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
286 | * modelled on the sparc64 implementation by Dave Miller. | |
287 | * -- paulus. | |
288 | */ | |
289 | ||
290 | /* | |
291 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
292 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
293 | * | |
294 | * Basically, the user finds the base address for his device which he wishes | |
295 | * to mmap. They read the 32-bit value from the config space base register, | |
296 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
297 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
298 | * | |
299 | * Returns negative error code on failure, zero on success. | |
300 | */ | |
301 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
302 | resource_size_t *offset, | |
303 | enum pci_mmap_state mmap_state) | |
304 | { | |
305 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
306 | unsigned long io_offset = 0; | |
307 | int i, res_bit; | |
308 | ||
309 | if (hose == 0) | |
310 | return NULL; /* should never happen */ | |
311 | ||
312 | /* If memory, add on the PCI bridge address offset */ | |
313 | if (mmap_state == pci_mmap_mem) { | |
314 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
315 | *offset += hose->pci_mem_offset; | |
316 | #endif | |
317 | res_bit = IORESOURCE_MEM; | |
318 | } else { | |
319 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
320 | *offset += io_offset; | |
321 | res_bit = IORESOURCE_IO; | |
322 | } | |
323 | ||
324 | /* | |
325 | * Check that the offset requested corresponds to one of the | |
326 | * resources of the device. | |
327 | */ | |
328 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
329 | struct resource *rp = &dev->resource[i]; | |
330 | int flags = rp->flags; | |
331 | ||
332 | /* treat ROM as memory (should be already) */ | |
333 | if (i == PCI_ROM_RESOURCE) | |
334 | flags |= IORESOURCE_MEM; | |
335 | ||
336 | /* Active and same type? */ | |
337 | if ((flags & res_bit) == 0) | |
338 | continue; | |
339 | ||
340 | /* In the range of this resource? */ | |
341 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
342 | continue; | |
343 | ||
344 | /* found it! construct the final physical address */ | |
345 | if (mmap_state == pci_mmap_io) | |
346 | *offset += hose->io_base_phys - io_offset; | |
347 | return rp; | |
348 | } | |
349 | ||
350 | return NULL; | |
351 | } | |
352 | ||
353 | /* | |
354 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
355 | * device mapping. | |
356 | */ | |
357 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
358 | pgprot_t protection, | |
359 | enum pci_mmap_state mmap_state, | |
360 | int write_combine) | |
361 | { | |
362 | unsigned long prot = pgprot_val(protection); | |
363 | ||
364 | /* Write combine is always 0 on non-memory space mappings. On | |
365 | * memory space, if the user didn't pass 1, we check for a | |
366 | * "prefetchable" resource. This is a bit hackish, but we use | |
367 | * this to workaround the inability of /sysfs to provide a write | |
368 | * combine bit | |
369 | */ | |
370 | if (mmap_state != pci_mmap_mem) | |
371 | write_combine = 0; | |
372 | else if (write_combine == 0) { | |
373 | if (rp->flags & IORESOURCE_PREFETCH) | |
374 | write_combine = 1; | |
375 | } | |
376 | ||
377 | /* XXX would be nice to have a way to ask for write-through */ | |
58083dad | 378 | if (write_combine) |
64b3d0e8 | 379 | return pgprot_noncached_wc(prot); |
58083dad | 380 | else |
64b3d0e8 | 381 | return pgprot_noncached(prot); |
58083dad KG |
382 | } |
383 | ||
384 | /* | |
385 | * This one is used by /dev/mem and fbdev who have no clue about the | |
386 | * PCI device, it tries to find the PCI device first and calls the | |
387 | * above routine | |
388 | */ | |
389 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
390 | unsigned long pfn, | |
391 | unsigned long size, | |
64b3d0e8 | 392 | pgprot_t prot) |
58083dad KG |
393 | { |
394 | struct pci_dev *pdev = NULL; | |
395 | struct resource *found = NULL; | |
7c12d906 | 396 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
397 | int i; |
398 | ||
399 | if (page_is_ram(pfn)) | |
64b3d0e8 | 400 | return prot; |
58083dad | 401 | |
64b3d0e8 | 402 | prot = pgprot_noncached(prot); |
58083dad KG |
403 | for_each_pci_dev(pdev) { |
404 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
405 | struct resource *rp = &pdev->resource[i]; | |
406 | int flags = rp->flags; | |
407 | ||
408 | /* Active and same type? */ | |
409 | if ((flags & IORESOURCE_MEM) == 0) | |
410 | continue; | |
411 | /* In the range of this resource? */ | |
412 | if (offset < (rp->start & PAGE_MASK) || | |
413 | offset > rp->end) | |
414 | continue; | |
415 | found = rp; | |
416 | break; | |
417 | } | |
418 | if (found) | |
419 | break; | |
420 | } | |
421 | if (found) { | |
422 | if (found->flags & IORESOURCE_PREFETCH) | |
64b3d0e8 | 423 | prot = pgprot_noncached_wc(prot); |
58083dad KG |
424 | pci_dev_put(pdev); |
425 | } | |
426 | ||
b0494bc8 | 427 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
64b3d0e8 | 428 | (unsigned long long)offset, pgprot_val(prot)); |
58083dad | 429 | |
64b3d0e8 | 430 | return prot; |
58083dad KG |
431 | } |
432 | ||
433 | ||
434 | /* | |
435 | * Perform the actual remap of the pages for a PCI device mapping, as | |
436 | * appropriate for this architecture. The region in the process to map | |
437 | * is described by vm_start and vm_end members of VMA, the base physical | |
438 | * address is found in vm_pgoff. | |
439 | * The pci device structure is provided so that architectures may make mapping | |
440 | * decisions on a per-device or per-bus basis. | |
441 | * | |
442 | * Returns a negative error code on failure, zero on success. | |
443 | */ | |
444 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
445 | enum pci_mmap_state mmap_state, int write_combine) | |
446 | { | |
7c12d906 BH |
447 | resource_size_t offset = |
448 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
58083dad KG |
449 | struct resource *rp; |
450 | int ret; | |
451 | ||
452 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
453 | if (rp == NULL) | |
454 | return -EINVAL; | |
455 | ||
456 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
457 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
458 | vma->vm_page_prot, | |
459 | mmap_state, write_combine); | |
460 | ||
461 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
462 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
463 | ||
464 | return ret; | |
465 | } | |
466 | ||
e9f82cb7 BH |
467 | /* This provides legacy IO read access on a bus */ |
468 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
469 | { | |
470 | unsigned long offset; | |
471 | struct pci_controller *hose = pci_bus_to_host(bus); | |
472 | struct resource *rp = &hose->io_resource; | |
473 | void __iomem *addr; | |
474 | ||
475 | /* Check if port can be supported by that bus. We only check | |
476 | * the ranges of the PHB though, not the bus itself as the rules | |
477 | * for forwarding legacy cycles down bridges are not our problem | |
478 | * here. So if the host bridge supports it, we do it. | |
479 | */ | |
480 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
481 | offset += port; | |
482 | ||
483 | if (!(rp->flags & IORESOURCE_IO)) | |
484 | return -ENXIO; | |
485 | if (offset < rp->start || (offset + size) > rp->end) | |
486 | return -ENXIO; | |
487 | addr = hose->io_base_virt + port; | |
488 | ||
489 | switch(size) { | |
490 | case 1: | |
491 | *((u8 *)val) = in_8(addr); | |
492 | return 1; | |
493 | case 2: | |
494 | if (port & 1) | |
495 | return -EINVAL; | |
496 | *((u16 *)val) = in_le16(addr); | |
497 | return 2; | |
498 | case 4: | |
499 | if (port & 3) | |
500 | return -EINVAL; | |
501 | *((u32 *)val) = in_le32(addr); | |
502 | return 4; | |
503 | } | |
504 | return -EINVAL; | |
505 | } | |
506 | ||
507 | /* This provides legacy IO write access on a bus */ | |
508 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
509 | { | |
510 | unsigned long offset; | |
511 | struct pci_controller *hose = pci_bus_to_host(bus); | |
512 | struct resource *rp = &hose->io_resource; | |
513 | void __iomem *addr; | |
514 | ||
515 | /* Check if port can be supported by that bus. We only check | |
516 | * the ranges of the PHB though, not the bus itself as the rules | |
517 | * for forwarding legacy cycles down bridges are not our problem | |
518 | * here. So if the host bridge supports it, we do it. | |
519 | */ | |
520 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
521 | offset += port; | |
522 | ||
523 | if (!(rp->flags & IORESOURCE_IO)) | |
524 | return -ENXIO; | |
525 | if (offset < rp->start || (offset + size) > rp->end) | |
526 | return -ENXIO; | |
527 | addr = hose->io_base_virt + port; | |
528 | ||
529 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
530 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
531 | * as a u32, which means that we have to correct the location of | |
532 | * the data read within those 32 bits for size 1 and 2 | |
533 | */ | |
534 | switch(size) { | |
535 | case 1: | |
536 | out_8(addr, val >> 24); | |
537 | return 1; | |
538 | case 2: | |
539 | if (port & 1) | |
540 | return -EINVAL; | |
541 | out_le16(addr, val >> 16); | |
542 | return 2; | |
543 | case 4: | |
544 | if (port & 3) | |
545 | return -EINVAL; | |
546 | out_le32(addr, val); | |
547 | return 4; | |
548 | } | |
549 | return -EINVAL; | |
550 | } | |
551 | ||
552 | /* This provides legacy IO or memory mmap access on a bus */ | |
553 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
554 | struct vm_area_struct *vma, | |
555 | enum pci_mmap_state mmap_state) | |
556 | { | |
557 | struct pci_controller *hose = pci_bus_to_host(bus); | |
558 | resource_size_t offset = | |
559 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
560 | resource_size_t size = vma->vm_end - vma->vm_start; | |
561 | struct resource *rp; | |
562 | ||
563 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
564 | pci_domain_nr(bus), bus->number, | |
565 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
566 | (unsigned long long)offset, | |
567 | (unsigned long long)(offset + size - 1)); | |
568 | ||
569 | if (mmap_state == pci_mmap_mem) { | |
5b11abfd BH |
570 | /* Hack alert ! |
571 | * | |
572 | * Because X is lame and can fail starting if it gets an error trying | |
573 | * to mmap legacy_mem (instead of just moving on without legacy memory | |
574 | * access) we fake it here by giving it anonymous memory, effectively | |
575 | * behaving just like /dev/zero | |
576 | */ | |
577 | if ((offset + size) > hose->isa_mem_size) { | |
578 | printk(KERN_DEBUG | |
579 | "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", | |
580 | current->comm, current->pid, pci_domain_nr(bus), bus->number); | |
581 | if (vma->vm_flags & VM_SHARED) | |
582 | return shmem_zero_setup(vma); | |
583 | return 0; | |
584 | } | |
e9f82cb7 BH |
585 | offset += hose->isa_mem_phys; |
586 | } else { | |
587 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
588 | unsigned long roffset = offset + io_offset; | |
589 | rp = &hose->io_resource; | |
590 | if (!(rp->flags & IORESOURCE_IO)) | |
591 | return -ENXIO; | |
592 | if (roffset < rp->start || (roffset + size) > rp->end) | |
593 | return -ENXIO; | |
594 | offset += hose->io_base_phys; | |
595 | } | |
596 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
597 | ||
598 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
64b3d0e8 | 599 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
e9f82cb7 BH |
600 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
601 | vma->vm_end - vma->vm_start, | |
602 | vma->vm_page_prot); | |
603 | } | |
604 | ||
58083dad KG |
605 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
606 | const struct resource *rsrc, | |
607 | resource_size_t *start, resource_size_t *end) | |
608 | { | |
609 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
610 | resource_size_t offset = 0; | |
611 | ||
612 | if (hose == NULL) | |
613 | return; | |
614 | ||
615 | if (rsrc->flags & IORESOURCE_IO) | |
616 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
617 | ||
618 | /* We pass a fully fixed up address to userland for MMIO instead of | |
619 | * a BAR value because X is lame and expects to be able to use that | |
620 | * to pass to /dev/mem ! | |
621 | * | |
622 | * That means that we'll have potentially 64 bits values where some | |
623 | * userland apps only expect 32 (like X itself since it thinks only | |
624 | * Sparc has 64 bits MMIO) but if we don't do that, we break it on | |
625 | * 32 bits CHRPs :-( | |
626 | * | |
627 | * Hopefully, the sysfs insterface is immune to that gunk. Once X | |
628 | * has been fixed (and the fix spread enough), we can re-enable the | |
629 | * 2 lines below and pass down a BAR value to userland. In that case | |
630 | * we'll also have to re-enable the matching code in | |
631 | * __pci_mmap_make_offset(). | |
632 | * | |
633 | * BenH. | |
634 | */ | |
635 | #if 0 | |
636 | else if (rsrc->flags & IORESOURCE_MEM) | |
637 | offset = hose->pci_mem_offset; | |
638 | #endif | |
639 | ||
640 | *start = rsrc->start - offset; | |
641 | *end = rsrc->end - offset; | |
642 | } | |
13dccb9e BH |
643 | |
644 | /** | |
645 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
646 | * @hose: newly allocated pci_controller to be setup | |
647 | * @dev: device node of the host bridge | |
648 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
649 | * | |
650 | * This function will parse the "ranges" property of a PCI host bridge device | |
651 | * node and setup the resource mapping of a pci controller based on its | |
652 | * content. | |
653 | * | |
654 | * Life would be boring if it wasn't for a few issues that we have to deal | |
655 | * with here: | |
656 | * | |
657 | * - We can only cope with one IO space range and up to 3 Memory space | |
658 | * ranges. However, some machines (thanks Apple !) tend to split their | |
659 | * space into lots of small contiguous ranges. So we have to coalesce. | |
660 | * | |
661 | * - We can only cope with all memory ranges having the same offset | |
662 | * between CPU addresses and PCI addresses. Unfortunately, some bridges | |
663 | * are setup for a large 1:1 mapping along with a small "window" which | |
664 | * maps PCI address 0 to some arbitrary high address of the CPU space in | |
665 | * order to give access to the ISA memory hole. | |
666 | * The way out of here that I've chosen for now is to always set the | |
667 | * offset based on the first resource found, then override it if we | |
668 | * have a different offset and the previous was set by an ISA hole. | |
669 | * | |
670 | * - Some busses have IO space not starting at 0, which causes trouble with | |
671 | * the way we do our IO resource renumbering. The code somewhat deals with | |
672 | * it for 64 bits but I would expect problems on 32 bits. | |
673 | * | |
674 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
675 | * 32 bits so we need to use 64 bits values for the parsing | |
676 | */ | |
cad5cef6 GKH |
677 | void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
678 | struct device_node *dev, int primary) | |
13dccb9e BH |
679 | { |
680 | const u32 *ranges; | |
681 | int rlen; | |
682 | int pna = of_n_addr_cells(dev); | |
683 | int np = pna + 5; | |
684 | int memno = 0, isa_hole = -1; | |
685 | u32 pci_space; | |
686 | unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; | |
687 | unsigned long long isa_mb = 0; | |
688 | struct resource *res; | |
689 | ||
690 | printk(KERN_INFO "PCI host bridge %s %s ranges:\n", | |
691 | dev->full_name, primary ? "(primary)" : ""); | |
692 | ||
693 | /* Get ranges property */ | |
694 | ranges = of_get_property(dev, "ranges", &rlen); | |
695 | if (ranges == NULL) | |
696 | return; | |
697 | ||
698 | /* Parse it */ | |
699 | while ((rlen -= np * 4) >= 0) { | |
700 | /* Read next ranges element */ | |
701 | pci_space = ranges[0]; | |
702 | pci_addr = of_read_number(ranges + 1, 2); | |
703 | cpu_addr = of_translate_address(dev, ranges + 3); | |
704 | size = of_read_number(ranges + pna + 3, 2); | |
705 | ranges += np; | |
e9f82cb7 BH |
706 | |
707 | /* If we failed translation or got a zero-sized region | |
708 | * (some FW try to feed us with non sensical zero sized regions | |
709 | * such as power3 which look like some kind of attempt at exposing | |
710 | * the VGA memory hole) | |
711 | */ | |
13dccb9e BH |
712 | if (cpu_addr == OF_BAD_ADDR || size == 0) |
713 | continue; | |
714 | ||
715 | /* Now consume following elements while they are contiguous */ | |
716 | for (; rlen >= np * sizeof(u32); | |
717 | ranges += np, rlen -= np * 4) { | |
718 | if (ranges[0] != pci_space) | |
719 | break; | |
720 | pci_next = of_read_number(ranges + 1, 2); | |
721 | cpu_next = of_translate_address(dev, ranges + 3); | |
722 | if (pci_next != pci_addr + size || | |
723 | cpu_next != cpu_addr + size) | |
724 | break; | |
725 | size += of_read_number(ranges + pna + 3, 2); | |
726 | } | |
727 | ||
728 | /* Act based on address space type */ | |
729 | res = NULL; | |
730 | switch ((pci_space >> 24) & 0x3) { | |
731 | case 1: /* PCI IO space */ | |
732 | printk(KERN_INFO | |
733 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
734 | cpu_addr, cpu_addr + size - 1, pci_addr); | |
735 | ||
736 | /* We support only one IO range */ | |
737 | if (hose->pci_io_size) { | |
738 | printk(KERN_INFO | |
739 | " \\--> Skipped (too many) !\n"); | |
740 | continue; | |
741 | } | |
742 | #ifdef CONFIG_PPC32 | |
743 | /* On 32 bits, limit I/O space to 16MB */ | |
744 | if (size > 0x01000000) | |
745 | size = 0x01000000; | |
746 | ||
747 | /* 32 bits needs to map IOs here */ | |
748 | hose->io_base_virt = ioremap(cpu_addr, size); | |
749 | ||
750 | /* Expect trouble if pci_addr is not 0 */ | |
751 | if (primary) | |
752 | isa_io_base = | |
753 | (unsigned long)hose->io_base_virt; | |
754 | #endif /* CONFIG_PPC32 */ | |
755 | /* pci_io_size and io_base_phys always represent IO | |
756 | * space starting at 0 so we factor in pci_addr | |
757 | */ | |
758 | hose->pci_io_size = pci_addr + size; | |
759 | hose->io_base_phys = cpu_addr - pci_addr; | |
760 | ||
761 | /* Build resource */ | |
762 | res = &hose->io_resource; | |
763 | res->flags = IORESOURCE_IO; | |
764 | res->start = pci_addr; | |
765 | break; | |
766 | case 2: /* PCI Memory space */ | |
67260ac9 | 767 | case 3: /* PCI 64 bits Memory space */ |
13dccb9e BH |
768 | printk(KERN_INFO |
769 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
770 | cpu_addr, cpu_addr + size - 1, pci_addr, | |
771 | (pci_space & 0x40000000) ? "Prefetch" : ""); | |
772 | ||
773 | /* We support only 3 memory ranges */ | |
774 | if (memno >= 3) { | |
775 | printk(KERN_INFO | |
776 | " \\--> Skipped (too many) !\n"); | |
777 | continue; | |
778 | } | |
779 | /* Handles ISA memory hole space here */ | |
780 | if (pci_addr == 0) { | |
781 | isa_mb = cpu_addr; | |
782 | isa_hole = memno; | |
783 | if (primary || isa_mem_base == 0) | |
784 | isa_mem_base = cpu_addr; | |
e9f82cb7 BH |
785 | hose->isa_mem_phys = cpu_addr; |
786 | hose->isa_mem_size = size; | |
13dccb9e BH |
787 | } |
788 | ||
789 | /* We get the PCI/Mem offset from the first range or | |
790 | * the, current one if the offset came from an ISA | |
791 | * hole. If they don't match, bugger. | |
792 | */ | |
793 | if (memno == 0 || | |
794 | (isa_hole >= 0 && pci_addr != 0 && | |
795 | hose->pci_mem_offset == isa_mb)) | |
796 | hose->pci_mem_offset = cpu_addr - pci_addr; | |
797 | else if (pci_addr != 0 && | |
798 | hose->pci_mem_offset != cpu_addr - pci_addr) { | |
799 | printk(KERN_INFO | |
800 | " \\--> Skipped (offset mismatch) !\n"); | |
801 | continue; | |
802 | } | |
803 | ||
804 | /* Build resource */ | |
805 | res = &hose->mem_resources[memno++]; | |
806 | res->flags = IORESOURCE_MEM; | |
807 | if (pci_space & 0x40000000) | |
808 | res->flags |= IORESOURCE_PREFETCH; | |
809 | res->start = cpu_addr; | |
810 | break; | |
811 | } | |
812 | if (res != NULL) { | |
813 | res->name = dev->full_name; | |
814 | res->end = res->start + size - 1; | |
815 | res->parent = NULL; | |
816 | res->sibling = NULL; | |
817 | res->child = NULL; | |
818 | } | |
819 | } | |
820 | ||
8db13a0e BH |
821 | /* If there's an ISA hole and the pci_mem_offset is -not- matching |
822 | * the ISA hole offset, then we need to remove the ISA hole from | |
823 | * the resource list for that brige | |
824 | */ | |
825 | if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { | |
826 | unsigned int next = isa_hole + 1; | |
827 | printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); | |
828 | if (next < memno) | |
829 | memmove(&hose->mem_resources[isa_hole], | |
830 | &hose->mem_resources[next], | |
831 | sizeof(struct resource) * (memno - next)); | |
832 | hose->mem_resources[--memno].flags = 0; | |
13dccb9e BH |
833 | } |
834 | } | |
fa462f2d BH |
835 | |
836 | /* Decide whether to display the domain number in /proc */ | |
837 | int pci_proc_domain(struct pci_bus *bus) | |
838 | { | |
839 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1fd0f525 | 840 | |
0e47ff1c | 841 | if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) |
fa462f2d | 842 | return 0; |
0e47ff1c | 843 | if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) |
fa462f2d BH |
844 | return hose->global_number != 0; |
845 | return 1; | |
fa462f2d BH |
846 | } |
847 | ||
d82fb31a KSS |
848 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
849 | { | |
850 | if (ppc_md.pcibios_root_bridge_prepare) | |
851 | return ppc_md.pcibios_root_bridge_prepare(bridge); | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
bf5e2ba2 BH |
856 | /* This header fixup will do the resource fixup for all devices as they are |
857 | * probed, but not for bridge ranges | |
858 | */ | |
cad5cef6 | 859 | static void pcibios_fixup_resources(struct pci_dev *dev) |
bf5e2ba2 BH |
860 | { |
861 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
862 | int i; | |
863 | ||
864 | if (!hose) { | |
865 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
866 | pci_name(dev)); | |
867 | return; | |
868 | } | |
869 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
870 | struct resource *res = dev->resource + i; | |
871 | if (!res->flags) | |
872 | continue; | |
48c2ce97 BH |
873 | |
874 | /* If we're going to re-assign everything, we mark all resources | |
875 | * as unset (and 0-base them). In addition, we mark BARs starting | |
876 | * at 0 as unset as well, except if PCI_PROBE_ONLY is also set | |
877 | * since in that case, we don't want to re-assign anything | |
7f172890 | 878 | */ |
48c2ce97 BH |
879 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || |
880 | (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { | |
881 | /* Only print message if not re-assigning */ | |
882 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) | |
883 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " | |
884 | "is unassigned\n", | |
885 | pci_name(dev), i, | |
886 | (unsigned long long)res->start, | |
887 | (unsigned long long)res->end, | |
888 | (unsigned int)res->flags); | |
bf5e2ba2 BH |
889 | res->end -= res->start; |
890 | res->start = 0; | |
891 | res->flags |= IORESOURCE_UNSET; | |
892 | continue; | |
893 | } | |
894 | ||
6c5705fe | 895 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", |
bf5e2ba2 BH |
896 | pci_name(dev), i, |
897 | (unsigned long long)res->start,\ | |
898 | (unsigned long long)res->end, | |
899 | (unsigned int)res->flags); | |
bf5e2ba2 BH |
900 | } |
901 | ||
902 | /* Call machine specific resource fixup */ | |
903 | if (ppc_md.pcibios_fixup_resources) | |
904 | ppc_md.pcibios_fixup_resources(dev); | |
905 | } | |
906 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
907 | ||
b5561511 BH |
908 | /* This function tries to figure out if a bridge resource has been initialized |
909 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
910 | * things go more smoothly when it gets it right. It should covers cases such | |
911 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
912 | */ | |
cad5cef6 GKH |
913 | static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, |
914 | struct resource *res) | |
bf5e2ba2 | 915 | { |
be8cbcd8 | 916 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 917 | struct pci_dev *dev = bus->self; |
b5561511 BH |
918 | resource_size_t offset; |
919 | u16 command; | |
920 | int i; | |
bf5e2ba2 | 921 | |
b5561511 | 922 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
0e47ff1c | 923 | if (pci_has_flag(PCI_PROBE_ONLY)) |
b5561511 | 924 | return 0; |
bf5e2ba2 | 925 | |
b5561511 BH |
926 | /* Job is a bit different between memory and IO */ |
927 | if (res->flags & IORESOURCE_MEM) { | |
928 | /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been | |
929 | * initialized by somebody | |
930 | */ | |
931 | if (res->start != hose->pci_mem_offset) | |
932 | return 0; | |
bf5e2ba2 | 933 | |
b5561511 BH |
934 | /* The BAR is 0, let's check if memory decoding is enabled on |
935 | * the bridge. If not, we consider it unassigned | |
936 | */ | |
937 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
938 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
939 | return 1; | |
be8cbcd8 | 940 | |
b5561511 BH |
941 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
942 | * resources covers that starting address (0 then it's good enough for | |
943 | * us for memory | |
944 | */ | |
945 | for (i = 0; i < 3; i++) { | |
946 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
947 | hose->mem_resources[i].start == hose->pci_mem_offset) | |
948 | return 0; | |
949 | } | |
950 | ||
951 | /* Well, it starts at 0 and we know it will collide so we may as | |
952 | * well consider it as unassigned. That covers the Apple case. | |
953 | */ | |
954 | return 1; | |
955 | } else { | |
956 | /* If the BAR is non-0, then we consider it assigned */ | |
957 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
958 | if (((res->start - offset) & 0xfffffffful) != 0) | |
959 | return 0; | |
960 | ||
961 | /* Here, we are a bit different than memory as typically IO space | |
962 | * starting at low addresses -is- valid. What we do instead if that | |
963 | * we consider as unassigned anything that doesn't have IO enabled | |
964 | * in the PCI command register, and that's it. | |
965 | */ | |
966 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
967 | if (command & PCI_COMMAND_IO) | |
968 | return 0; | |
969 | ||
970 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
971 | * it unassigned | |
972 | */ | |
973 | return 1; | |
974 | } | |
975 | } | |
976 | ||
977 | /* Fixup resources of a PCI<->PCI bridge */ | |
cad5cef6 | 978 | static void pcibios_fixup_bridge(struct pci_bus *bus) |
b5561511 BH |
979 | { |
980 | struct resource *res; | |
981 | int i; | |
982 | ||
983 | struct pci_dev *dev = bus->self; | |
984 | ||
89a74ecc BH |
985 | pci_bus_for_each_resource(bus, res, i) { |
986 | if (!res || !res->flags) | |
b5561511 BH |
987 | continue; |
988 | if (i >= 3 && bus->self->transparent) | |
989 | continue; | |
990 | ||
cf1a4cf8 GS |
991 | /* If we're going to reassign everything, we can |
992 | * shrink the P2P resource to have size as being | |
993 | * of 0 in order to save space. | |
48c2ce97 BH |
994 | */ |
995 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { | |
996 | res->flags |= IORESOURCE_UNSET; | |
48c2ce97 | 997 | res->start = 0; |
cf1a4cf8 | 998 | res->end = -1; |
48c2ce97 BH |
999 | continue; |
1000 | } | |
1001 | ||
6c5705fe | 1002 | pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", |
b5561511 BH |
1003 | pci_name(dev), i, |
1004 | (unsigned long long)res->start,\ | |
1005 | (unsigned long long)res->end, | |
1006 | (unsigned int)res->flags); | |
bf5e2ba2 | 1007 | |
b5561511 BH |
1008 | /* Try to detect uninitialized P2P bridge resources, |
1009 | * and clear them out so they get re-assigned later | |
1010 | */ | |
1011 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
1012 | res->flags = 0; | |
1013 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
bf5e2ba2 BH |
1014 | } |
1015 | } | |
b5561511 BH |
1016 | } |
1017 | ||
cad5cef6 | 1018 | void pcibios_setup_bus_self(struct pci_bus *bus) |
8b8da358 | 1019 | { |
7eef440a | 1020 | /* Fix up the bus resources for P2P bridges */ |
8b8da358 BH |
1021 | if (bus->self != NULL) |
1022 | pcibios_fixup_bridge(bus); | |
1023 | ||
1024 | /* Platform specific bus fixups. This is currently only used | |
7eef440a | 1025 | * by fsl_pci and I'm hoping to get rid of it at some point |
8b8da358 BH |
1026 | */ |
1027 | if (ppc_md.pcibios_fixup_bus) | |
1028 | ppc_md.pcibios_fixup_bus(bus); | |
1029 | ||
1030 | /* Setup bus DMA mappings */ | |
1031 | if (ppc_md.pci_dma_bus_setup) | |
1032 | ppc_md.pci_dma_bus_setup(bus); | |
1033 | } | |
1034 | ||
37f02195 YC |
1035 | void pcibios_setup_device(struct pci_dev *dev) |
1036 | { | |
1037 | /* Fixup NUMA node as it may not be setup yet by the generic | |
1038 | * code and is needed by the DMA init | |
1039 | */ | |
1040 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
1041 | ||
1042 | /* Hook up default DMA ops */ | |
1043 | set_dma_ops(&dev->dev, pci_dma_ops); | |
1044 | set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); | |
1045 | ||
1046 | /* Additional platform DMA/iommu setup */ | |
1047 | if (ppc_md.pci_dma_dev_setup) | |
1048 | ppc_md.pci_dma_dev_setup(dev); | |
1049 | ||
1050 | /* Read default IRQs and fixup if necessary */ | |
1051 | pci_read_irq_line(dev); | |
1052 | if (ppc_md.pci_irq_fixup) | |
1053 | ppc_md.pci_irq_fixup(dev); | |
1054 | } | |
1055 | ||
cad5cef6 | 1056 | void pcibios_setup_bus_devices(struct pci_bus *bus) |
7eef440a BH |
1057 | { |
1058 | struct pci_dev *dev; | |
1059 | ||
1060 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
1061 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
1062 | ||
1063 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
2d1c8618 BH |
1064 | /* Cardbus can call us to add new devices to a bus, so ignore |
1065 | * those who are already fully discovered | |
1066 | */ | |
1067 | if (dev->is_added) | |
1068 | continue; | |
1069 | ||
37f02195 | 1070 | pcibios_setup_device(dev); |
7eef440a BH |
1071 | } |
1072 | } | |
1073 | ||
79c8be83 MS |
1074 | void pcibios_set_master(struct pci_dev *dev) |
1075 | { | |
1076 | /* No special bus mastering setup handling */ | |
1077 | } | |
1078 | ||
cad5cef6 | 1079 | void pcibios_fixup_bus(struct pci_bus *bus) |
bf5e2ba2 BH |
1080 | { |
1081 | /* When called from the generic PCI probe, read PCI<->PCI bridge | |
7eef440a | 1082 | * bases. This is -not- called when generating the PCI tree from |
8b8da358 | 1083 | * the OF device-tree. |
bf5e2ba2 BH |
1084 | */ |
1085 | if (bus->self != NULL) | |
1086 | pci_read_bridge_bases(bus); | |
bf5e2ba2 | 1087 | |
8b8da358 BH |
1088 | /* Now fixup the bus bus */ |
1089 | pcibios_setup_bus_self(bus); | |
1090 | ||
1091 | /* Now fixup devices on that bus */ | |
1092 | pcibios_setup_bus_devices(bus); | |
bf5e2ba2 | 1093 | } |
8b8da358 | 1094 | EXPORT_SYMBOL(pcibios_fixup_bus); |
3fd94c6b | 1095 | |
cad5cef6 | 1096 | void pci_fixup_cardbus(struct pci_bus *bus) |
2d1c8618 BH |
1097 | { |
1098 | /* Now fixup devices on that bus */ | |
1099 | pcibios_setup_bus_devices(bus); | |
1100 | } | |
1101 | ||
1102 | ||
3fd94c6b BH |
1103 | static int skip_isa_ioresource_align(struct pci_dev *dev) |
1104 | { | |
0e47ff1c | 1105 | if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && |
3fd94c6b BH |
1106 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) |
1107 | return 1; | |
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | /* | |
1112 | * We need to avoid collisions with `mirrored' VGA ports | |
1113 | * and other strange ISA hardware, so we always want the | |
1114 | * addresses to be allocated in the 0x000-0x0ff region | |
1115 | * modulo 0x400. | |
1116 | * | |
1117 | * Why? Because some silly external IO cards only decode | |
1118 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1119 | * is reserved for motherboard devices that decode all 16 | |
1120 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1121 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1122 | * which might have be mirrored at 0x0100-0x03ff.. | |
1123 | */ | |
3b7a17fc | 1124 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
3fd94c6b BH |
1125 | resource_size_t size, resource_size_t align) |
1126 | { | |
1127 | struct pci_dev *dev = data; | |
b26b2d49 | 1128 | resource_size_t start = res->start; |
3fd94c6b BH |
1129 | |
1130 | if (res->flags & IORESOURCE_IO) { | |
3fd94c6b | 1131 | if (skip_isa_ioresource_align(dev)) |
b26b2d49 DB |
1132 | return start; |
1133 | if (start & 0x300) | |
3fd94c6b | 1134 | start = (start + 0x3ff) & ~0x3ff; |
3fd94c6b | 1135 | } |
b26b2d49 DB |
1136 | |
1137 | return start; | |
3fd94c6b BH |
1138 | } |
1139 | EXPORT_SYMBOL(pcibios_align_resource); | |
1140 | ||
1141 | /* | |
1142 | * Reparent resource children of pr that conflict with res | |
1143 | * under res, and make res replace those children. | |
1144 | */ | |
0f6023d5 | 1145 | static int reparent_resources(struct resource *parent, |
3fd94c6b BH |
1146 | struct resource *res) |
1147 | { | |
1148 | struct resource *p, **pp; | |
1149 | struct resource **firstpp = NULL; | |
1150 | ||
1151 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1152 | if (p->end < res->start) | |
1153 | continue; | |
1154 | if (res->end < p->start) | |
1155 | break; | |
1156 | if (p->start < res->start || p->end > res->end) | |
1157 | return -1; /* not completely contained */ | |
1158 | if (firstpp == NULL) | |
1159 | firstpp = pp; | |
1160 | } | |
1161 | if (firstpp == NULL) | |
1162 | return -1; /* didn't find any conflicting entries? */ | |
1163 | res->parent = parent; | |
1164 | res->child = *firstpp; | |
1165 | res->sibling = *pp; | |
1166 | *firstpp = res; | |
1167 | *pp = NULL; | |
1168 | for (p = res->child; p != NULL; p = p->sibling) { | |
1169 | p->parent = res; | |
b0494bc8 BH |
1170 | pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", |
1171 | p->name, | |
1172 | (unsigned long long)p->start, | |
1173 | (unsigned long long)p->end, res->name); | |
3fd94c6b BH |
1174 | } |
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | /* | |
1179 | * Handle resources of PCI devices. If the world were perfect, we could | |
1180 | * just allocate all the resource regions and do nothing more. It isn't. | |
1181 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1182 | * require us to know lots of host bridge internals. So we attempt to | |
1183 | * keep as much of the original configuration as possible, but tweak it | |
1184 | * when it's found to be wrong. | |
1185 | * | |
1186 | * Known BIOS problems we have to work around: | |
1187 | * - I/O or memory regions not configured | |
1188 | * - regions configured, but not enabled in the command register | |
1189 | * - bogus I/O addresses above 64K used | |
1190 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1191 | * the fact the PCI specs explicitly allow address decoders to be | |
1192 | * shared between expansion ROMs and other resource regions, it's | |
1193 | * at least dangerous) | |
1194 | * | |
1195 | * Our solution: | |
1196 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1197 | * This gives us fixed barriers on where we can allocate. | |
1198 | * (2) Allocate resources for all enabled devices. If there is | |
1199 | * a collision, just mark the resource as unallocated. Also | |
1200 | * disable expansion ROMs during this step. | |
1201 | * (3) Try to allocate resources for disabled devices. If the | |
1202 | * resources were assigned correctly, everything goes well, | |
1203 | * if they weren't, they won't disturb allocation of other | |
1204 | * resources. | |
1205 | * (4) Assign new addresses to resources which were either | |
1206 | * not configured at all or misconfigured. If explicitly | |
1207 | * requested by the user, configure expansion ROM address | |
1208 | * as well. | |
1209 | */ | |
1210 | ||
e90a1318 | 1211 | void pcibios_allocate_bus_resources(struct pci_bus *bus) |
3fd94c6b | 1212 | { |
e90a1318 | 1213 | struct pci_bus *b; |
3fd94c6b BH |
1214 | int i; |
1215 | struct resource *res, *pr; | |
1216 | ||
b5ae5f91 BH |
1217 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
1218 | pci_domain_nr(bus), bus->number); | |
1219 | ||
89a74ecc BH |
1220 | pci_bus_for_each_resource(bus, res, i) { |
1221 | if (!res || !res->flags || res->start > res->end || res->parent) | |
e90a1318 | 1222 | continue; |
48c2ce97 BH |
1223 | |
1224 | /* If the resource was left unset at this point, we clear it */ | |
1225 | if (res->flags & IORESOURCE_UNSET) | |
1226 | goto clear_resource; | |
1227 | ||
e90a1318 NF |
1228 | if (bus->parent == NULL) |
1229 | pr = (res->flags & IORESOURCE_IO) ? | |
1230 | &ioport_resource : &iomem_resource; | |
1231 | else { | |
e90a1318 NF |
1232 | pr = pci_find_parent_resource(bus->self, res); |
1233 | if (pr == res) { | |
1234 | /* this happens when the generic PCI | |
1235 | * code (wrongly) decides that this | |
1236 | * bridge is transparent -- paulus | |
3fd94c6b | 1237 | */ |
e90a1318 | 1238 | continue; |
3fd94c6b | 1239 | } |
e90a1318 | 1240 | } |
3fd94c6b | 1241 | |
b0494bc8 BH |
1242 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " |
1243 | "[0x%x], parent %p (%s)\n", | |
1244 | bus->self ? pci_name(bus->self) : "PHB", | |
1245 | bus->number, i, | |
1246 | (unsigned long long)res->start, | |
1247 | (unsigned long long)res->end, | |
1248 | (unsigned int)res->flags, | |
1249 | pr, (pr && pr->name) ? pr->name : "nil"); | |
e90a1318 NF |
1250 | |
1251 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
1252 | if (request_resource(pr, res) == 0) | |
1253 | continue; | |
1254 | /* | |
1255 | * Must be a conflict with an existing entry. | |
1256 | * Move that entry (or entries) under the | |
1257 | * bridge resource and try again. | |
1258 | */ | |
1259 | if (reparent_resources(pr, res) == 0) | |
1260 | continue; | |
3fd94c6b | 1261 | } |
48c2ce97 BH |
1262 | pr_warning("PCI: Cannot allocate resource region " |
1263 | "%d of PCI bridge %d, will remap\n", i, bus->number); | |
1264 | clear_resource: | |
cf1a4cf8 GS |
1265 | /* The resource might be figured out when doing |
1266 | * reassignment based on the resources required | |
1267 | * by the downstream PCI devices. Here we set | |
1268 | * the size of the resource to be 0 in order to | |
1269 | * save more space. | |
1270 | */ | |
1271 | res->start = 0; | |
1272 | res->end = -1; | |
e90a1318 | 1273 | res->flags = 0; |
3fd94c6b | 1274 | } |
e90a1318 NF |
1275 | |
1276 | list_for_each_entry(b, &bus->children, node) | |
1277 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1278 | } |
1279 | ||
cad5cef6 | 1280 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1281 | { |
1282 | struct resource *pr, *r = &dev->resource[idx]; | |
1283 | ||
b0494bc8 BH |
1284 | pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", |
1285 | pci_name(dev), idx, | |
1286 | (unsigned long long)r->start, | |
1287 | (unsigned long long)r->end, | |
1288 | (unsigned int)r->flags); | |
3fd94c6b BH |
1289 | |
1290 | pr = pci_find_parent_resource(dev, r); | |
1291 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1292 | request_resource(pr, r) < 0) { | |
1293 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1294 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1295 | if (pr) | |
b0494bc8 BH |
1296 | pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", |
1297 | pr, | |
1298 | (unsigned long long)pr->start, | |
1299 | (unsigned long long)pr->end, | |
1300 | (unsigned int)pr->flags); | |
3fd94c6b BH |
1301 | /* We'll assign a new address later */ |
1302 | r->flags |= IORESOURCE_UNSET; | |
1303 | r->end -= r->start; | |
1304 | r->start = 0; | |
1305 | } | |
1306 | } | |
1307 | ||
1308 | static void __init pcibios_allocate_resources(int pass) | |
1309 | { | |
1310 | struct pci_dev *dev = NULL; | |
1311 | int idx, disabled; | |
1312 | u16 command; | |
1313 | struct resource *r; | |
1314 | ||
1315 | for_each_pci_dev(dev) { | |
1316 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
ad892a63 | 1317 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { |
3fd94c6b BH |
1318 | r = &dev->resource[idx]; |
1319 | if (r->parent) /* Already allocated */ | |
1320 | continue; | |
1321 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1322 | continue; /* Not assigned at all */ | |
ad892a63 BH |
1323 | /* We only allocate ROMs on pass 1 just in case they |
1324 | * have been screwed up by firmware | |
1325 | */ | |
1326 | if (idx == PCI_ROM_RESOURCE ) | |
1327 | disabled = 1; | |
3fd94c6b BH |
1328 | if (r->flags & IORESOURCE_IO) |
1329 | disabled = !(command & PCI_COMMAND_IO); | |
1330 | else | |
1331 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1332 | if (pass == disabled) |
1333 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1334 | } |
1335 | if (pass) | |
1336 | continue; | |
1337 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
ad892a63 | 1338 | if (r->flags) { |
3fd94c6b BH |
1339 | /* Turn the ROM off, leave the resource region, |
1340 | * but keep it unregistered. | |
1341 | */ | |
1342 | u32 reg; | |
3fd94c6b | 1343 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
ad892a63 BH |
1344 | if (reg & PCI_ROM_ADDRESS_ENABLE) { |
1345 | pr_debug("PCI: Switching off ROM of %s\n", | |
1346 | pci_name(dev)); | |
1347 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1348 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1349 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1350 | } | |
3fd94c6b BH |
1351 | } |
1352 | } | |
1353 | } | |
1354 | ||
c1f34302 BH |
1355 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) |
1356 | { | |
1357 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1358 | resource_size_t offset; | |
1359 | struct resource *res, *pres; | |
1360 | int i; | |
1361 | ||
1362 | pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); | |
1363 | ||
1364 | /* Check for IO */ | |
1365 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1366 | goto no_io; | |
1367 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1368 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1369 | BUG_ON(res == NULL); | |
1370 | res->name = "Legacy IO"; | |
1371 | res->flags = IORESOURCE_IO; | |
1372 | res->start = offset; | |
1373 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1374 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1375 | if (request_resource(&hose->io_resource, res)) { | |
1376 | printk(KERN_DEBUG | |
1377 | "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", | |
1378 | pci_domain_nr(bus), bus->number, res); | |
1379 | kfree(res); | |
1380 | } | |
1381 | ||
1382 | no_io: | |
1383 | /* Check for memory */ | |
1384 | offset = hose->pci_mem_offset; | |
1385 | pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); | |
1386 | for (i = 0; i < 3; i++) { | |
1387 | pres = &hose->mem_resources[i]; | |
1388 | if (!(pres->flags & IORESOURCE_MEM)) | |
1389 | continue; | |
1390 | pr_debug("hose mem res: %pR\n", pres); | |
1391 | if ((pres->start - offset) <= 0xa0000 && | |
1392 | (pres->end - offset) >= 0xbffff) | |
1393 | break; | |
1394 | } | |
1395 | if (i >= 3) | |
1396 | return; | |
1397 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1398 | BUG_ON(res == NULL); | |
1399 | res->name = "Legacy VGA memory"; | |
1400 | res->flags = IORESOURCE_MEM; | |
1401 | res->start = 0xa0000 + offset; | |
1402 | res->end = 0xbffff + offset; | |
1403 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1404 | if (request_resource(pres, res)) { | |
1405 | printk(KERN_DEBUG | |
1406 | "PCI %04x:%02x Cannot reserve VGA memory %pR\n", | |
1407 | pci_domain_nr(bus), bus->number, res); | |
1408 | kfree(res); | |
1409 | } | |
1410 | } | |
1411 | ||
3fd94c6b BH |
1412 | void __init pcibios_resource_survey(void) |
1413 | { | |
e90a1318 NF |
1414 | struct pci_bus *b; |
1415 | ||
48c2ce97 | 1416 | /* Allocate and assign resources */ |
e90a1318 NF |
1417 | list_for_each_entry(b, &pci_root_buses, node) |
1418 | pcibios_allocate_bus_resources(b); | |
48c2ce97 BH |
1419 | pcibios_allocate_resources(0); |
1420 | pcibios_allocate_resources(1); | |
3fd94c6b | 1421 | |
c1f34302 BH |
1422 | /* Before we start assigning unassigned resource, we try to reserve |
1423 | * the low IO area and the VGA memory area if they intersect the | |
1424 | * bus available resources to avoid allocating things on top of them | |
1425 | */ | |
0e47ff1c | 1426 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
c1f34302 BH |
1427 | list_for_each_entry(b, &pci_root_buses, node) |
1428 | pcibios_reserve_legacy_regions(b); | |
1429 | } | |
1430 | ||
1431 | /* Now, if the platform didn't decide to blindly trust the firmware, | |
1432 | * we proceed to assigning things that were left unassigned | |
1433 | */ | |
0e47ff1c | 1434 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
a77acda0 | 1435 | pr_debug("PCI: Assigning unassigned resources...\n"); |
3fd94c6b BH |
1436 | pci_assign_unassigned_resources(); |
1437 | } | |
1438 | ||
1439 | /* Call machine dependent fixup */ | |
1440 | if (ppc_md.pcibios_fixup) | |
1441 | ppc_md.pcibios_fixup(); | |
1442 | } | |
1443 | ||
fd6852c8 | 1444 | /* This is used by the PCI hotplug driver to allocate resource |
3fd94c6b | 1445 | * of newly plugged busses. We can try to consolidate with the |
fd6852c8 BH |
1446 | * rest of the code later, for now, keep it as-is as our main |
1447 | * resource allocation function doesn't deal with sub-trees yet. | |
3fd94c6b | 1448 | */ |
baf75b0a | 1449 | void pcibios_claim_one_bus(struct pci_bus *bus) |
3fd94c6b BH |
1450 | { |
1451 | struct pci_dev *dev; | |
1452 | struct pci_bus *child_bus; | |
1453 | ||
1454 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1455 | int i; | |
1456 | ||
1457 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1458 | struct resource *r = &dev->resource[i]; | |
1459 | ||
1460 | if (r->parent || !r->start || !r->flags) | |
1461 | continue; | |
fd6852c8 BH |
1462 | |
1463 | pr_debug("PCI: Claiming %s: " | |
1464 | "Resource %d: %016llx..%016llx [%x]\n", | |
1465 | pci_name(dev), i, | |
1466 | (unsigned long long)r->start, | |
1467 | (unsigned long long)r->end, | |
1468 | (unsigned int)r->flags); | |
1469 | ||
3fd94c6b BH |
1470 | pci_claim_resource(dev, i); |
1471 | } | |
1472 | } | |
1473 | ||
1474 | list_for_each_entry(child_bus, &bus->children, node) | |
1475 | pcibios_claim_one_bus(child_bus); | |
1476 | } | |
fd6852c8 BH |
1477 | |
1478 | ||
1479 | /* pcibios_finish_adding_to_bus | |
1480 | * | |
1481 | * This is to be called by the hotplug code after devices have been | |
1482 | * added to a bus, this include calling it for a PHB that is just | |
1483 | * being added | |
1484 | */ | |
1485 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1486 | { | |
1487 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1488 | pci_domain_nr(bus), bus->number); | |
1489 | ||
1490 | /* Allocate bus and devices resources */ | |
1491 | pcibios_allocate_bus_resources(bus); | |
1492 | pcibios_claim_one_bus(bus); | |
1493 | ||
6a040ce7 TLSC |
1494 | /* Fixup EEH */ |
1495 | eeh_add_device_tree_late(bus); | |
1496 | ||
fd6852c8 BH |
1497 | /* Add new devices to global lists. Register in proc, sysfs. */ |
1498 | pci_bus_add_devices(bus); | |
1499 | ||
6a040ce7 TLSC |
1500 | /* sysfs files should only be added after devices are added */ |
1501 | eeh_add_sysfs_files(bus); | |
fd6852c8 BH |
1502 | } |
1503 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1504 | ||
549beb9b BH |
1505 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1506 | { | |
549beb9b BH |
1507 | if (ppc_md.pcibios_enable_device_hook) |
1508 | if (ppc_md.pcibios_enable_device_hook(dev)) | |
1509 | return -EINVAL; | |
1510 | ||
37f02195 YC |
1511 | /* avoid pcie irq fix up impact on cardbus */ |
1512 | if (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS) | |
1513 | pcibios_setup_device(dev); | |
1514 | ||
7cfb5f9a | 1515 | return pci_enable_resources(dev, mask); |
549beb9b | 1516 | } |
53280323 | 1517 | |
38973ba7 BH |
1518 | resource_size_t pcibios_io_space_offset(struct pci_controller *hose) |
1519 | { | |
1520 | return (unsigned long) hose->io_base_virt - _IO_BASE; | |
1521 | } | |
1522 | ||
cad5cef6 GKH |
1523 | static void pcibios_setup_phb_resources(struct pci_controller *hose, |
1524 | struct list_head *resources) | |
53280323 | 1525 | { |
53280323 BH |
1526 | struct resource *res; |
1527 | int i; | |
1528 | ||
1529 | /* Hookup PHB IO resource */ | |
45a709f8 | 1530 | res = &hose->io_resource; |
53280323 BH |
1531 | |
1532 | if (!res->flags) { | |
1533 | printk(KERN_WARNING "PCI: I/O resource not set for host" | |
1534 | " bridge %s (domain %d)\n", | |
1535 | hose->dn->full_name, hose->global_number); | |
1536 | #ifdef CONFIG_PPC32 | |
1537 | /* Workaround for lack of IO resource only on 32-bit */ | |
1538 | res->start = (unsigned long)hose->io_base_virt - isa_io_base; | |
1539 | res->end = res->start + IO_SPACE_LIMIT; | |
1540 | res->flags = IORESOURCE_IO; | |
1541 | #endif /* CONFIG_PPC32 */ | |
1542 | } | |
1543 | ||
1544 | pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", | |
1545 | (unsigned long long)res->start, | |
1546 | (unsigned long long)res->end, | |
1547 | (unsigned long)res->flags); | |
38973ba7 | 1548 | pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose)); |
53280323 BH |
1549 | |
1550 | /* Hookup PHB Memory resources */ | |
1551 | for (i = 0; i < 3; ++i) { | |
1552 | res = &hose->mem_resources[i]; | |
1553 | if (!res->flags) { | |
1554 | if (i > 0) | |
1555 | continue; | |
1556 | printk(KERN_ERR "PCI: Memory resource 0 not set for " | |
1557 | "host bridge %s (domain %d)\n", | |
1558 | hose->dn->full_name, hose->global_number); | |
1559 | #ifdef CONFIG_PPC32 | |
1560 | /* Workaround for lack of MEM resource only on 32-bit */ | |
1561 | res->start = hose->pci_mem_offset; | |
1562 | res->end = (resource_size_t)-1LL; | |
1563 | res->flags = IORESOURCE_MEM; | |
1564 | #endif /* CONFIG_PPC32 */ | |
1565 | } | |
53280323 BH |
1566 | |
1567 | pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, | |
1568 | (unsigned long long)res->start, | |
1569 | (unsigned long long)res->end, | |
1570 | (unsigned long)res->flags); | |
6c5705fe | 1571 | pci_add_resource_offset(resources, res, hose->pci_mem_offset); |
53280323 BH |
1572 | } |
1573 | ||
1574 | pr_debug("PCI: PHB MEM offset = %016llx\n", | |
1575 | (unsigned long long)hose->pci_mem_offset); | |
1576 | pr_debug("PCI: PHB IO offset = %08lx\n", | |
1577 | (unsigned long)hose->io_base_virt - _IO_BASE); | |
1578 | ||
1579 | } | |
89c2dd62 KG |
1580 | |
1581 | /* | |
1582 | * Null PCI config access functions, for the case when we can't | |
1583 | * find a hose. | |
1584 | */ | |
1585 | #define NULL_PCI_OP(rw, size, type) \ | |
1586 | static int \ | |
1587 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1588 | { \ | |
1589 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1590 | } | |
1591 | ||
1592 | static int | |
1593 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1594 | int len, u32 *val) | |
1595 | { | |
1596 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1597 | } | |
1598 | ||
1599 | static int | |
1600 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1601 | int len, u32 val) | |
1602 | { | |
1603 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1604 | } | |
1605 | ||
1606 | static struct pci_ops null_pci_ops = | |
1607 | { | |
1608 | .read = null_read_config, | |
1609 | .write = null_write_config, | |
1610 | }; | |
1611 | ||
1612 | /* | |
1613 | * These functions are used early on before PCI scanning is done | |
1614 | * and all of the pci_dev and pci_bus structures have been created. | |
1615 | */ | |
1616 | static struct pci_bus * | |
1617 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1618 | { | |
1619 | static struct pci_bus bus; | |
1620 | ||
1621 | if (hose == 0) { | |
1622 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); | |
1623 | } | |
1624 | bus.number = busnr; | |
1625 | bus.sysdata = hose; | |
1626 | bus.ops = hose? hose->ops: &null_pci_ops; | |
1627 | return &bus; | |
1628 | } | |
1629 | ||
1630 | #define EARLY_PCI_OP(rw, size, type) \ | |
1631 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1632 | int devfn, int offset, type value) \ | |
1633 | { \ | |
1634 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1635 | devfn, offset, value); \ | |
1636 | } | |
1637 | ||
1638 | EARLY_PCI_OP(read, byte, u8 *) | |
1639 | EARLY_PCI_OP(read, word, u16 *) | |
1640 | EARLY_PCI_OP(read, dword, u32 *) | |
1641 | EARLY_PCI_OP(write, byte, u8) | |
1642 | EARLY_PCI_OP(write, word, u16) | |
1643 | EARLY_PCI_OP(write, dword, u32) | |
1644 | ||
1645 | extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); | |
1646 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, | |
1647 | int cap) | |
1648 | { | |
1649 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1650 | } | |
0ed2c722 | 1651 | |
98d9f30c BH |
1652 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
1653 | { | |
1654 | struct pci_controller *hose = bus->sysdata; | |
1655 | ||
1656 | return of_node_get(hose->dn); | |
1657 | } | |
1658 | ||
0ed2c722 GL |
1659 | /** |
1660 | * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus | |
1661 | * @hose: Pointer to the PCI host controller instance structure | |
0ed2c722 | 1662 | */ |
cad5cef6 | 1663 | void pcibios_scan_phb(struct pci_controller *hose) |
0ed2c722 | 1664 | { |
45a709f8 | 1665 | LIST_HEAD(resources); |
0ed2c722 GL |
1666 | struct pci_bus *bus; |
1667 | struct device_node *node = hose->dn; | |
1668 | int mode; | |
1669 | ||
74a7f084 | 1670 | pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); |
0ed2c722 | 1671 | |
45a709f8 BH |
1672 | /* Get some IO space for the new PHB */ |
1673 | pcibios_setup_phb_io_space(hose); | |
1674 | ||
1675 | /* Wire up PHB bus resources */ | |
1676 | pcibios_setup_phb_resources(hose, &resources); | |
1677 | ||
be8e60d8 YL |
1678 | hose->busn.start = hose->first_busno; |
1679 | hose->busn.end = hose->last_busno; | |
1680 | hose->busn.flags = IORESOURCE_BUS; | |
1681 | pci_add_resource(&resources, &hose->busn); | |
1682 | ||
0ed2c722 | 1683 | /* Create an empty bus for the toplevel */ |
45a709f8 BH |
1684 | bus = pci_create_root_bus(hose->parent, hose->first_busno, |
1685 | hose->ops, hose, &resources); | |
0ed2c722 GL |
1686 | if (bus == NULL) { |
1687 | pr_err("Failed to create bus for PCI domain %04x\n", | |
1688 | hose->global_number); | |
45a709f8 | 1689 | pci_free_resource_list(&resources); |
0ed2c722 GL |
1690 | return; |
1691 | } | |
0ed2c722 GL |
1692 | hose->bus = bus; |
1693 | ||
0ed2c722 GL |
1694 | /* Get probe mode and perform scan */ |
1695 | mode = PCI_PROBE_NORMAL; | |
1696 | if (node && ppc_md.pci_probe_mode) | |
1697 | mode = ppc_md.pci_probe_mode(bus); | |
1698 | pr_debug(" probe mode: %d\n", mode); | |
be8e60d8 | 1699 | if (mode == PCI_PROBE_DEVTREE) |
0ed2c722 | 1700 | of_scan_bus(node, bus); |
0ed2c722 | 1701 | |
be8e60d8 YL |
1702 | if (mode == PCI_PROBE_NORMAL) { |
1703 | pci_bus_update_busn_res_end(bus, 255); | |
1704 | hose->last_busno = pci_scan_child_bus(bus); | |
1705 | pci_bus_update_busn_res_end(bus, hose->last_busno); | |
1706 | } | |
781fb7a3 | 1707 | |
491b98c3 BH |
1708 | /* Platform gets a chance to do some global fixups before |
1709 | * we proceed to resource allocation | |
1710 | */ | |
1711 | if (ppc_md.pcibios_fixup_phb) | |
1712 | ppc_md.pcibios_fixup_phb(hose); | |
1713 | ||
781fb7a3 | 1714 | /* Configure PCI Express settings */ |
bb36c445 | 1715 | if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { |
781fb7a3 BH |
1716 | struct pci_bus *child; |
1717 | list_for_each_entry(child, &bus->children, node) { | |
1718 | struct pci_dev *self = child->self; | |
1719 | if (!self) | |
1720 | continue; | |
1721 | pcie_bus_configure_settings(child, self->pcie_mpss); | |
1722 | } | |
1723 | } | |
0ed2c722 | 1724 | } |
c065488f KG |
1725 | |
1726 | static void fixup_hide_host_resource_fsl(struct pci_dev *dev) | |
1727 | { | |
1728 | int i, class = dev->class >> 8; | |
05737c7c JJ |
1729 | /* When configured as agent, programing interface = 1 */ |
1730 | int prog_if = dev->class & 0xf; | |
c065488f KG |
1731 | |
1732 | if ((class == PCI_CLASS_PROCESSOR_POWERPC || | |
1733 | class == PCI_CLASS_BRIDGE_OTHER) && | |
1734 | (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && | |
05737c7c | 1735 | (prog_if == 0) && |
c065488f KG |
1736 | (dev->bus->parent == NULL)) { |
1737 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1738 | dev->resource[i].start = 0; | |
1739 | dev->resource[i].end = 0; | |
1740 | dev->resource[i].flags = 0; | |
1741 | } | |
1742 | } | |
1743 | } | |
1744 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
1745 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
c2e1d845 BK |
1746 | |
1747 | static void fixup_vga(struct pci_dev *pdev) | |
1748 | { | |
1749 | u16 cmd; | |
1750 | ||
1751 | pci_read_config_word(pdev, PCI_COMMAND, &cmd); | |
1752 | if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) | |
1753 | vga_set_default_device(pdev); | |
1754 | ||
1755 | } | |
1756 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, | |
1757 | PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); |