Commit | Line | Data |
---|---|---|
e05b3b4a PM |
1 | /* |
2 | * Common pmac/prep/chrp pci routines. -- Cort | |
3 | */ | |
4 | ||
e05b3b4a PM |
5 | #include <linux/kernel.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/string.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/capability.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/bootmem.h> | |
6e99e458 | 14 | #include <linux/irq.h> |
f90bb153 | 15 | #include <linux/list.h> |
e05b3b4a PM |
16 | |
17 | #include <asm/processor.h> | |
18 | #include <asm/io.h> | |
19 | #include <asm/prom.h> | |
20 | #include <asm/sections.h> | |
21 | #include <asm/pci-bridge.h> | |
22 | #include <asm/byteorder.h> | |
e05b3b4a PM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/machdep.h> | |
25 | ||
26 | #undef DEBUG | |
27 | ||
28 | #ifdef DEBUG | |
29 | #define DBG(x...) printk(x) | |
30 | #else | |
31 | #define DBG(x...) | |
32 | #endif | |
33 | ||
34 | unsigned long isa_io_base = 0; | |
35 | unsigned long isa_mem_base = 0; | |
36 | unsigned long pci_dram_offset = 0; | |
37 | int pcibios_assign_bus_offset = 1; | |
38 | ||
39 | void pcibios_make_OF_bus_map(void); | |
40 | ||
41 | static int pci_relocate_bridge_resource(struct pci_bus *bus, int i); | |
42 | static int probe_resource(struct pci_bus *parent, struct resource *pr, | |
43 | struct resource *res, struct resource **conflict); | |
44 | static void update_bridge_base(struct pci_bus *bus, int i); | |
45 | static void pcibios_fixup_resources(struct pci_dev* dev); | |
46 | static void fixup_broken_pcnet32(struct pci_dev* dev); | |
47 | static int reparent_resources(struct resource *parent, struct resource *res); | |
48 | static void fixup_cpc710_pci64(struct pci_dev* dev); | |
49 | #ifdef CONFIG_PPC_OF | |
50 | static u8* pci_to_OF_bus_map; | |
51 | #endif | |
52 | ||
53 | /* By default, we don't re-assign bus numbers. We do this only on | |
54 | * some pmacs | |
55 | */ | |
56 | int pci_assign_all_buses; | |
57 | ||
a4c9e328 | 58 | LIST_HEAD(hose_list); |
e05b3b4a PM |
59 | |
60 | static int pci_bus_count; | |
61 | ||
62 | static void | |
63 | fixup_broken_pcnet32(struct pci_dev* dev) | |
64 | { | |
65 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | |
66 | dev->vendor = PCI_VENDOR_ID_AMD; | |
67 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | |
68 | } | |
69 | } | |
70 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | |
71 | ||
72 | static void | |
73 | fixup_cpc710_pci64(struct pci_dev* dev) | |
74 | { | |
75 | /* Hide the PCI64 BARs from the kernel as their content doesn't | |
76 | * fit well in the resource management | |
77 | */ | |
78 | dev->resource[0].start = dev->resource[0].end = 0; | |
79 | dev->resource[0].flags = 0; | |
80 | dev->resource[1].start = dev->resource[1].end = 0; | |
81 | dev->resource[1].flags = 0; | |
82 | } | |
83 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64); | |
84 | ||
85 | static void | |
86 | pcibios_fixup_resources(struct pci_dev *dev) | |
87 | { | |
88 | struct pci_controller* hose = (struct pci_controller *)dev->sysdata; | |
89 | int i; | |
90 | unsigned long offset; | |
91 | ||
92 | if (!hose) { | |
93 | printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev)); | |
94 | return; | |
95 | } | |
96 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
97 | struct resource *res = dev->resource + i; | |
98 | if (!res->flags) | |
99 | continue; | |
100 | if (res->end == 0xffffffff) { | |
685143ac | 101 | DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n", |
872455e2 | 102 | pci_name(dev), i, (u64)res->start, (u64)res->end); |
e05b3b4a PM |
103 | res->end -= res->start; |
104 | res->start = 0; | |
105 | res->flags |= IORESOURCE_UNSET; | |
106 | continue; | |
107 | } | |
108 | offset = 0; | |
109 | if (res->flags & IORESOURCE_MEM) { | |
110 | offset = hose->pci_mem_offset; | |
111 | } else if (res->flags & IORESOURCE_IO) { | |
112 | offset = (unsigned long) hose->io_base_virt | |
113 | - isa_io_base; | |
114 | } | |
115 | if (offset != 0) { | |
116 | res->start += offset; | |
117 | res->end += offset; | |
872455e2 SS |
118 | DBG("Fixup res %d (%lx) of dev %s: %llx -> %llx\n", |
119 | i, res->flags, pci_name(dev), | |
120 | (u64)res->start - offset, (u64)res->start); | |
e05b3b4a PM |
121 | } |
122 | } | |
123 | ||
124 | /* Call machine specific resource fixup */ | |
125 | if (ppc_md.pcibios_fixup_resources) | |
126 | ppc_md.pcibios_fixup_resources(dev); | |
127 | } | |
128 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
129 | ||
130 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
131 | struct resource *res) | |
132 | { | |
133 | unsigned long offset = 0; | |
134 | struct pci_controller *hose = dev->sysdata; | |
135 | ||
136 | if (hose && res->flags & IORESOURCE_IO) | |
137 | offset = (unsigned long)hose->io_base_virt - isa_io_base; | |
138 | else if (hose && res->flags & IORESOURCE_MEM) | |
139 | offset = hose->pci_mem_offset; | |
140 | region->start = res->start - offset; | |
141 | region->end = res->end - offset; | |
142 | } | |
143 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
144 | ||
145 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
146 | struct pci_bus_region *region) | |
147 | { | |
148 | unsigned long offset = 0; | |
149 | struct pci_controller *hose = dev->sysdata; | |
150 | ||
151 | if (hose && res->flags & IORESOURCE_IO) | |
152 | offset = (unsigned long)hose->io_base_virt - isa_io_base; | |
153 | else if (hose && res->flags & IORESOURCE_MEM) | |
154 | offset = hose->pci_mem_offset; | |
155 | res->start = region->start + offset; | |
156 | res->end = region->end + offset; | |
157 | } | |
158 | EXPORT_SYMBOL(pcibios_bus_to_resource); | |
159 | ||
160 | /* | |
161 | * We need to avoid collisions with `mirrored' VGA ports | |
162 | * and other strange ISA hardware, so we always want the | |
163 | * addresses to be allocated in the 0x000-0x0ff region | |
164 | * modulo 0x400. | |
165 | * | |
166 | * Why? Because some silly external IO cards only decode | |
167 | * the low 10 bits of the IO address. The 0x00-0xff region | |
168 | * is reserved for motherboard devices that decode all 16 | |
169 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
170 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
171 | * which might have be mirrored at 0x0100-0x03ff.. | |
172 | */ | |
e31dd6e4 GKH |
173 | void pcibios_align_resource(void *data, struct resource *res, |
174 | resource_size_t size, resource_size_t align) | |
e05b3b4a PM |
175 | { |
176 | struct pci_dev *dev = data; | |
177 | ||
178 | if (res->flags & IORESOURCE_IO) { | |
e31dd6e4 | 179 | resource_size_t start = res->start; |
e05b3b4a PM |
180 | |
181 | if (size > 0x100) { | |
182 | printk(KERN_ERR "PCI: I/O Region %s/%d too large" | |
685143ac | 183 | " (%lld bytes)\n", pci_name(dev), |
e31dd6e4 | 184 | dev->resource - res, (unsigned long long)size); |
e05b3b4a PM |
185 | } |
186 | ||
187 | if (start & 0x300) { | |
188 | start = (start + 0x3ff) & ~0x3ff; | |
189 | res->start = start; | |
190 | } | |
191 | } | |
192 | } | |
193 | EXPORT_SYMBOL(pcibios_align_resource); | |
194 | ||
195 | /* | |
196 | * Handle resources of PCI devices. If the world were perfect, we could | |
197 | * just allocate all the resource regions and do nothing more. It isn't. | |
198 | * On the other hand, we cannot just re-allocate all devices, as it would | |
199 | * require us to know lots of host bridge internals. So we attempt to | |
200 | * keep as much of the original configuration as possible, but tweak it | |
201 | * when it's found to be wrong. | |
202 | * | |
203 | * Known BIOS problems we have to work around: | |
204 | * - I/O or memory regions not configured | |
205 | * - regions configured, but not enabled in the command register | |
206 | * - bogus I/O addresses above 64K used | |
207 | * - expansion ROMs left enabled (this may sound harmless, but given | |
208 | * the fact the PCI specs explicitly allow address decoders to be | |
209 | * shared between expansion ROMs and other resource regions, it's | |
210 | * at least dangerous) | |
211 | * | |
212 | * Our solution: | |
213 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
214 | * This gives us fixed barriers on where we can allocate. | |
215 | * (2) Allocate resources for all enabled devices. If there is | |
216 | * a collision, just mark the resource as unallocated. Also | |
217 | * disable expansion ROMs during this step. | |
218 | * (3) Try to allocate resources for disabled devices. If the | |
219 | * resources were assigned correctly, everything goes well, | |
220 | * if they weren't, they won't disturb allocation of other | |
221 | * resources. | |
222 | * (4) Assign new addresses to resources which were either | |
223 | * not configured at all or misconfigured. If explicitly | |
224 | * requested by the user, configure expansion ROM address | |
225 | * as well. | |
226 | */ | |
227 | ||
228 | static void __init | |
229 | pcibios_allocate_bus_resources(struct list_head *bus_list) | |
230 | { | |
231 | struct pci_bus *bus; | |
232 | int i; | |
233 | struct resource *res, *pr; | |
234 | ||
235 | /* Depth-First Search on bus tree */ | |
236 | list_for_each_entry(bus, bus_list, node) { | |
237 | for (i = 0; i < 4; ++i) { | |
238 | if ((res = bus->resource[i]) == NULL || !res->flags | |
239 | || res->start > res->end) | |
240 | continue; | |
241 | if (bus->parent == NULL) | |
242 | pr = (res->flags & IORESOURCE_IO)? | |
243 | &ioport_resource: &iomem_resource; | |
244 | else { | |
245 | pr = pci_find_parent_resource(bus->self, res); | |
246 | if (pr == res) { | |
247 | /* this happens when the generic PCI | |
248 | * code (wrongly) decides that this | |
249 | * bridge is transparent -- paulus | |
250 | */ | |
251 | continue; | |
252 | } | |
253 | } | |
254 | ||
685143ac | 255 | DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n", |
872455e2 | 256 | (u64)res->start, (u64)res->end, res->flags, pr); |
e05b3b4a PM |
257 | if (pr) { |
258 | if (request_resource(pr, res) == 0) | |
259 | continue; | |
260 | /* | |
261 | * Must be a conflict with an existing entry. | |
262 | * Move that entry (or entries) under the | |
263 | * bridge resource and try again. | |
264 | */ | |
265 | if (reparent_resources(pr, res) == 0) | |
266 | continue; | |
267 | } | |
268 | printk(KERN_ERR "PCI: Cannot allocate resource region " | |
269 | "%d of PCI bridge %d\n", i, bus->number); | |
270 | if (pci_relocate_bridge_resource(bus, i)) | |
271 | bus->resource[i] = NULL; | |
272 | } | |
273 | pcibios_allocate_bus_resources(&bus->children); | |
274 | } | |
275 | } | |
276 | ||
277 | /* | |
278 | * Reparent resource children of pr that conflict with res | |
279 | * under res, and make res replace those children. | |
280 | */ | |
281 | static int __init | |
282 | reparent_resources(struct resource *parent, struct resource *res) | |
283 | { | |
284 | struct resource *p, **pp; | |
285 | struct resource **firstpp = NULL; | |
286 | ||
287 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
288 | if (p->end < res->start) | |
289 | continue; | |
290 | if (res->end < p->start) | |
291 | break; | |
292 | if (p->start < res->start || p->end > res->end) | |
293 | return -1; /* not completely contained */ | |
294 | if (firstpp == NULL) | |
295 | firstpp = pp; | |
296 | } | |
297 | if (firstpp == NULL) | |
298 | return -1; /* didn't find any conflicting entries? */ | |
299 | res->parent = parent; | |
300 | res->child = *firstpp; | |
301 | res->sibling = *pp; | |
302 | *firstpp = res; | |
303 | *pp = NULL; | |
304 | for (p = res->child; p != NULL; p = p->sibling) { | |
305 | p->parent = res; | |
685143ac | 306 | DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n", |
872455e2 | 307 | p->name, (u64)p->start, (u64)p->end, res->name); |
e05b3b4a PM |
308 | } |
309 | return 0; | |
310 | } | |
311 | ||
312 | /* | |
313 | * A bridge has been allocated a range which is outside the range | |
314 | * of its parent bridge, so it needs to be moved. | |
315 | */ | |
316 | static int __init | |
317 | pci_relocate_bridge_resource(struct pci_bus *bus, int i) | |
318 | { | |
319 | struct resource *res, *pr, *conflict; | |
320 | unsigned long try, size; | |
321 | int j; | |
322 | struct pci_bus *parent = bus->parent; | |
323 | ||
324 | if (parent == NULL) { | |
325 | /* shouldn't ever happen */ | |
326 | printk(KERN_ERR "PCI: can't move host bridge resource\n"); | |
327 | return -1; | |
328 | } | |
329 | res = bus->resource[i]; | |
330 | if (res == NULL) | |
331 | return -1; | |
332 | pr = NULL; | |
333 | for (j = 0; j < 4; j++) { | |
334 | struct resource *r = parent->resource[j]; | |
335 | if (!r) | |
336 | continue; | |
337 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
338 | continue; | |
339 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) { | |
340 | pr = r; | |
341 | break; | |
342 | } | |
343 | if (res->flags & IORESOURCE_PREFETCH) | |
344 | pr = r; | |
345 | } | |
346 | if (pr == NULL) | |
347 | return -1; | |
348 | size = res->end - res->start; | |
349 | if (pr->start > pr->end || size > pr->end - pr->start) | |
350 | return -1; | |
351 | try = pr->end; | |
352 | for (;;) { | |
353 | res->start = try - size; | |
354 | res->end = try; | |
355 | if (probe_resource(bus->parent, pr, res, &conflict) == 0) | |
356 | break; | |
357 | if (conflict->start <= pr->start + size) | |
358 | return -1; | |
359 | try = conflict->start - 1; | |
360 | } | |
361 | if (request_resource(pr, res)) { | |
685143ac | 362 | DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n", |
872455e2 | 363 | (u64)res->start, (u64)res->end); |
e05b3b4a PM |
364 | return -1; /* "can't happen" */ |
365 | } | |
366 | update_bridge_base(bus, i); | |
685143ac GKH |
367 | printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n", |
368 | bus->number, i, (unsigned long long)res->start, | |
369 | (unsigned long long)res->end); | |
e05b3b4a PM |
370 | return 0; |
371 | } | |
372 | ||
373 | static int __init | |
374 | probe_resource(struct pci_bus *parent, struct resource *pr, | |
375 | struct resource *res, struct resource **conflict) | |
376 | { | |
377 | struct pci_bus *bus; | |
378 | struct pci_dev *dev; | |
379 | struct resource *r; | |
380 | int i; | |
381 | ||
382 | for (r = pr->child; r != NULL; r = r->sibling) { | |
383 | if (r->end >= res->start && res->end >= r->start) { | |
384 | *conflict = r; | |
385 | return 1; | |
386 | } | |
387 | } | |
388 | list_for_each_entry(bus, &parent->children, node) { | |
389 | for (i = 0; i < 4; ++i) { | |
390 | if ((r = bus->resource[i]) == NULL) | |
391 | continue; | |
392 | if (!r->flags || r->start > r->end || r == res) | |
393 | continue; | |
394 | if (pci_find_parent_resource(bus->self, r) != pr) | |
395 | continue; | |
396 | if (r->end >= res->start && res->end >= r->start) { | |
397 | *conflict = r; | |
398 | return 1; | |
399 | } | |
400 | } | |
401 | } | |
402 | list_for_each_entry(dev, &parent->devices, bus_list) { | |
403 | for (i = 0; i < 6; ++i) { | |
404 | r = &dev->resource[i]; | |
405 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
406 | continue; | |
407 | if (pci_find_parent_resource(dev, r) != pr) | |
408 | continue; | |
409 | if (r->end >= res->start && res->end >= r->start) { | |
410 | *conflict = r; | |
411 | return 1; | |
412 | } | |
413 | } | |
414 | } | |
415 | return 0; | |
416 | } | |
417 | ||
418 | static void __init | |
419 | update_bridge_base(struct pci_bus *bus, int i) | |
420 | { | |
421 | struct resource *res = bus->resource[i]; | |
422 | u8 io_base_lo, io_limit_lo; | |
423 | u16 mem_base, mem_limit; | |
424 | u16 cmd; | |
425 | unsigned long start, end, off; | |
426 | struct pci_dev *dev = bus->self; | |
427 | struct pci_controller *hose = dev->sysdata; | |
428 | ||
429 | if (!hose) { | |
430 | printk("update_bridge_base: no hose?\n"); | |
431 | return; | |
432 | } | |
433 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
434 | pci_write_config_word(dev, PCI_COMMAND, | |
435 | cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); | |
436 | if (res->flags & IORESOURCE_IO) { | |
437 | off = (unsigned long) hose->io_base_virt - isa_io_base; | |
438 | start = res->start - off; | |
439 | end = res->end - off; | |
440 | io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK; | |
441 | io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK; | |
60b2a46c | 442 | if (end > 0xffff) |
e05b3b4a | 443 | io_base_lo |= PCI_IO_RANGE_TYPE_32; |
60b2a46c | 444 | else |
e05b3b4a | 445 | io_base_lo |= PCI_IO_RANGE_TYPE_16; |
60b2a46c RV |
446 | pci_write_config_word(dev, PCI_IO_BASE_UPPER16, |
447 | start >> 16); | |
448 | pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, | |
449 | end >> 16); | |
e05b3b4a PM |
450 | pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo); |
451 | pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo); | |
452 | ||
453 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) | |
454 | == IORESOURCE_MEM) { | |
455 | off = hose->pci_mem_offset; | |
456 | mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK; | |
457 | mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK; | |
458 | pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); | |
459 | pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); | |
460 | ||
461 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) | |
462 | == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) { | |
463 | off = hose->pci_mem_offset; | |
464 | mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK; | |
465 | mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK; | |
466 | pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base); | |
467 | pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); | |
468 | ||
469 | } else { | |
470 | DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", | |
471 | pci_name(dev), i, res->flags); | |
472 | } | |
473 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
474 | } | |
475 | ||
476 | static inline void alloc_resource(struct pci_dev *dev, int idx) | |
477 | { | |
478 | struct resource *pr, *r = &dev->resource[idx]; | |
479 | ||
685143ac | 480 | DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n", |
872455e2 | 481 | pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags); |
e05b3b4a PM |
482 | pr = pci_find_parent_resource(dev, r); |
483 | if (!pr || request_resource(pr, r) < 0) { | |
484 | printk(KERN_ERR "PCI: Cannot allocate resource region %d" | |
485 | " of device %s\n", idx, pci_name(dev)); | |
486 | if (pr) | |
685143ac | 487 | DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n", |
872455e2 | 488 | pr, (u64)pr->start, (u64)pr->end, pr->flags); |
e05b3b4a PM |
489 | /* We'll assign a new address later */ |
490 | r->flags |= IORESOURCE_UNSET; | |
491 | r->end -= r->start; | |
492 | r->start = 0; | |
493 | } | |
494 | } | |
495 | ||
496 | static void __init | |
497 | pcibios_allocate_resources(int pass) | |
498 | { | |
499 | struct pci_dev *dev = NULL; | |
500 | int idx, disabled; | |
501 | u16 command; | |
502 | struct resource *r; | |
503 | ||
504 | for_each_pci_dev(dev) { | |
505 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
506 | for (idx = 0; idx < 6; idx++) { | |
507 | r = &dev->resource[idx]; | |
508 | if (r->parent) /* Already allocated */ | |
509 | continue; | |
510 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
511 | continue; /* Not assigned at all */ | |
512 | if (r->flags & IORESOURCE_IO) | |
513 | disabled = !(command & PCI_COMMAND_IO); | |
514 | else | |
515 | disabled = !(command & PCI_COMMAND_MEMORY); | |
516 | if (pass == disabled) | |
517 | alloc_resource(dev, idx); | |
518 | } | |
519 | if (pass) | |
520 | continue; | |
521 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
522 | if (r->flags & IORESOURCE_ROM_ENABLE) { | |
523 | /* Turn the ROM off, leave the resource region, but keep it unregistered. */ | |
524 | u32 reg; | |
525 | DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); | |
526 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
527 | pci_read_config_dword(dev, dev->rom_base_reg, ®); | |
528 | pci_write_config_dword(dev, dev->rom_base_reg, | |
529 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
530 | } | |
531 | } | |
532 | } | |
533 | ||
534 | static void __init | |
535 | pcibios_assign_resources(void) | |
536 | { | |
537 | struct pci_dev *dev = NULL; | |
538 | int idx; | |
539 | struct resource *r; | |
540 | ||
541 | for_each_pci_dev(dev) { | |
542 | int class = dev->class >> 8; | |
543 | ||
544 | /* Don't touch classless devices and host bridges */ | |
545 | if (!class || class == PCI_CLASS_BRIDGE_HOST) | |
546 | continue; | |
547 | ||
548 | for (idx = 0; idx < 6; idx++) { | |
549 | r = &dev->resource[idx]; | |
550 | ||
551 | /* | |
552 | * We shall assign a new address to this resource, | |
553 | * either because the BIOS (sic) forgot to do so | |
554 | * or because we have decided the old address was | |
555 | * unusable for some reason. | |
556 | */ | |
557 | if ((r->flags & IORESOURCE_UNSET) && r->end && | |
558 | (!ppc_md.pcibios_enable_device_hook || | |
559 | !ppc_md.pcibios_enable_device_hook(dev, 1))) { | |
560 | r->flags &= ~IORESOURCE_UNSET; | |
561 | pci_assign_resource(dev, idx); | |
562 | } | |
563 | } | |
564 | ||
565 | #if 0 /* don't assign ROMs */ | |
566 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
567 | r->end -= r->start; | |
568 | r->start = 0; | |
569 | if (r->end) | |
570 | pci_assign_resource(dev, PCI_ROM_RESOURCE); | |
571 | #endif | |
572 | } | |
573 | } | |
574 | ||
e05b3b4a PM |
575 | #ifdef CONFIG_PPC_OF |
576 | /* | |
577 | * Functions below are used on OpenFirmware machines. | |
578 | */ | |
579 | static void | |
580 | make_one_node_map(struct device_node* node, u8 pci_bus) | |
581 | { | |
a7f67bdf | 582 | const int *bus_range; |
e05b3b4a PM |
583 | int len; |
584 | ||
585 | if (pci_bus >= pci_bus_count) | |
586 | return; | |
e2eb6392 | 587 | bus_range = of_get_property(node, "bus-range", &len); |
e05b3b4a PM |
588 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
589 | printk(KERN_WARNING "Can't get bus-range for %s, " | |
590 | "assuming it starts at 0\n", node->full_name); | |
591 | pci_to_OF_bus_map[pci_bus] = 0; | |
592 | } else | |
593 | pci_to_OF_bus_map[pci_bus] = bus_range[0]; | |
594 | ||
595 | for (node=node->child; node != 0;node = node->sibling) { | |
596 | struct pci_dev* dev; | |
a7f67bdf | 597 | const unsigned int *class_code, *reg; |
e05b3b4a | 598 | |
e2eb6392 | 599 | class_code = of_get_property(node, "class-code", NULL); |
e05b3b4a PM |
600 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
601 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
602 | continue; | |
e2eb6392 | 603 | reg = of_get_property(node, "reg", NULL); |
e05b3b4a PM |
604 | if (!reg) |
605 | continue; | |
ab462768 AC |
606 | dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff)); |
607 | if (!dev || !dev->subordinate) { | |
608 | pci_dev_put(dev); | |
e05b3b4a | 609 | continue; |
ab462768 | 610 | } |
e05b3b4a | 611 | make_one_node_map(node, dev->subordinate->number); |
ab462768 | 612 | pci_dev_put(dev); |
e05b3b4a PM |
613 | } |
614 | } | |
615 | ||
616 | void | |
617 | pcibios_make_OF_bus_map(void) | |
618 | { | |
619 | int i; | |
a4c9e328 | 620 | struct pci_controller *hose, *tmp; |
a7f67bdf | 621 | struct property *map_prop; |
8c8dc322 | 622 | struct device_node *dn; |
e05b3b4a | 623 | |
5cbded58 | 624 | pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL); |
e05b3b4a PM |
625 | if (!pci_to_OF_bus_map) { |
626 | printk(KERN_ERR "Can't allocate OF bus map !\n"); | |
627 | return; | |
628 | } | |
629 | ||
630 | /* We fill the bus map with invalid values, that helps | |
631 | * debugging. | |
632 | */ | |
633 | for (i=0; i<pci_bus_count; i++) | |
634 | pci_to_OF_bus_map[i] = 0xff; | |
635 | ||
636 | /* For each hose, we begin searching bridges */ | |
a4c9e328 | 637 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
e05b3b4a PM |
638 | struct device_node* node; |
639 | node = (struct device_node *)hose->arch_data; | |
640 | if (!node) | |
641 | continue; | |
642 | make_one_node_map(node, hose->first_busno); | |
643 | } | |
8c8dc322 SR |
644 | dn = of_find_node_by_path("/"); |
645 | map_prop = of_find_property(dn, "pci-OF-bus-map", NULL); | |
a7f67bdf JK |
646 | if (map_prop) { |
647 | BUG_ON(pci_bus_count > map_prop->length); | |
648 | memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count); | |
649 | } | |
8c8dc322 | 650 | of_node_put(dn); |
e05b3b4a PM |
651 | #ifdef DEBUG |
652 | printk("PCI->OF bus map:\n"); | |
653 | for (i=0; i<pci_bus_count; i++) { | |
654 | if (pci_to_OF_bus_map[i] == 0xff) | |
655 | continue; | |
656 | printk("%d -> %d\n", i, pci_to_OF_bus_map[i]); | |
657 | } | |
658 | #endif | |
659 | } | |
660 | ||
661 | typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data); | |
662 | ||
663 | static struct device_node* | |
664 | scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data) | |
665 | { | |
666 | struct device_node* sub_node; | |
667 | ||
668 | for (; node != 0;node = node->sibling) { | |
a7f67bdf | 669 | const unsigned int *class_code; |
e05b3b4a PM |
670 | |
671 | if (filter(node, data)) | |
672 | return node; | |
673 | ||
674 | /* For PCI<->PCI bridges or CardBus bridges, we go down | |
675 | * Note: some OFs create a parent node "multifunc-device" as | |
676 | * a fake root for all functions of a multi-function device, | |
677 | * we go down them as well. | |
678 | */ | |
e2eb6392 | 679 | class_code = of_get_property(node, "class-code", NULL); |
e05b3b4a PM |
680 | if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
681 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) && | |
682 | strcmp(node->name, "multifunc-device")) | |
683 | continue; | |
684 | sub_node = scan_OF_pci_childs(node->child, filter, data); | |
685 | if (sub_node) | |
686 | return sub_node; | |
687 | } | |
688 | return NULL; | |
689 | } | |
690 | ||
dae4828d BH |
691 | static struct device_node *scan_OF_for_pci_dev(struct device_node *parent, |
692 | unsigned int devfn) | |
e05b3b4a | 693 | { |
dae4828d BH |
694 | struct device_node *np = NULL; |
695 | const u32 *reg; | |
696 | unsigned int psize; | |
697 | ||
698 | while ((np = of_get_next_child(parent, np)) != NULL) { | |
e2eb6392 | 699 | reg = of_get_property(np, "reg", &psize); |
dae4828d BH |
700 | if (reg == NULL || psize < 4) |
701 | continue; | |
702 | if (((reg[0] >> 8) & 0xff) == devfn) | |
703 | return np; | |
704 | } | |
705 | return NULL; | |
e05b3b4a PM |
706 | } |
707 | ||
dae4828d BH |
708 | |
709 | static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus) | |
e05b3b4a | 710 | { |
dae4828d BH |
711 | struct device_node *parent, *np; |
712 | ||
713 | /* Are we a root bus ? */ | |
714 | if (bus->self == NULL || bus->parent == NULL) { | |
0b1d40c4 | 715 | struct pci_controller *hose = pci_bus_to_host(bus); |
dae4828d BH |
716 | if (hose == NULL) |
717 | return NULL; | |
718 | return of_node_get(hose->arch_data); | |
719 | } | |
720 | ||
721 | /* not a root bus, we need to get our parent */ | |
722 | parent = scan_OF_for_pci_bus(bus->parent); | |
723 | if (parent == NULL) | |
724 | return NULL; | |
725 | ||
726 | /* now iterate for children for a match */ | |
727 | np = scan_OF_for_pci_dev(parent, bus->self->devfn); | |
728 | of_node_put(parent); | |
729 | ||
dae4828d | 730 | return np; |
e05b3b4a PM |
731 | } |
732 | ||
733 | /* | |
734 | * Scans the OF tree for a device node matching a PCI device | |
735 | */ | |
736 | struct device_node * | |
737 | pci_busdev_to_OF_node(struct pci_bus *bus, int devfn) | |
738 | { | |
dae4828d | 739 | struct device_node *parent, *np; |
e05b3b4a PM |
740 | |
741 | if (!have_of) | |
742 | return NULL; | |
e05b3b4a | 743 | |
dae4828d BH |
744 | DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn); |
745 | parent = scan_OF_for_pci_bus(bus); | |
746 | if (parent == NULL) | |
e05b3b4a | 747 | return NULL; |
dae4828d BH |
748 | DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>"); |
749 | np = scan_OF_for_pci_dev(parent, devfn); | |
750 | of_node_put(parent); | |
751 | DBG(" result is %s\n", np ? np->full_name : "<NULL>"); | |
752 | ||
753 | /* XXX most callers don't release the returned node | |
754 | * mostly because ppc64 doesn't increase the refcount, | |
755 | * we need to fix that. | |
e05b3b4a | 756 | */ |
dae4828d | 757 | return np; |
e05b3b4a PM |
758 | } |
759 | EXPORT_SYMBOL(pci_busdev_to_OF_node); | |
760 | ||
761 | struct device_node* | |
762 | pci_device_to_OF_node(struct pci_dev *dev) | |
763 | { | |
764 | return pci_busdev_to_OF_node(dev->bus, dev->devfn); | |
765 | } | |
766 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
767 | ||
e05b3b4a PM |
768 | static int |
769 | find_OF_pci_device_filter(struct device_node* node, void* data) | |
770 | { | |
771 | return ((void *)node == data); | |
772 | } | |
773 | ||
774 | /* | |
775 | * Returns the PCI device matching a given OF node | |
776 | */ | |
777 | int | |
778 | pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn) | |
779 | { | |
a7f67bdf | 780 | const unsigned int *reg; |
e05b3b4a PM |
781 | struct pci_controller* hose; |
782 | struct pci_dev* dev = NULL; | |
783 | ||
784 | if (!have_of) | |
785 | return -ENODEV; | |
786 | /* Make sure it's really a PCI device */ | |
787 | hose = pci_find_hose_for_OF_device(node); | |
788 | if (!hose || !hose->arch_data) | |
789 | return -ENODEV; | |
790 | if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child, | |
791 | find_OF_pci_device_filter, (void *)node)) | |
792 | return -ENODEV; | |
e2eb6392 | 793 | reg = of_get_property(node, "reg", NULL); |
e05b3b4a PM |
794 | if (!reg) |
795 | return -ENODEV; | |
796 | *bus = (reg[0] >> 16) & 0xff; | |
797 | *devfn = ((reg[0] >> 8) & 0xff); | |
798 | ||
799 | /* Ok, here we need some tweak. If we have already renumbered | |
800 | * all busses, we can't rely on the OF bus number any more. | |
801 | * the pci_to_OF_bus_map is not enough as several PCI busses | |
802 | * may match the same OF bus number. | |
803 | */ | |
804 | if (!pci_to_OF_bus_map) | |
805 | return 0; | |
806 | ||
807 | for_each_pci_dev(dev) | |
808 | if (pci_to_OF_bus_map[dev->bus->number] == *bus && | |
809 | dev->devfn == *devfn) { | |
810 | *bus = dev->bus->number; | |
811 | pci_dev_put(dev); | |
812 | return 0; | |
813 | } | |
814 | ||
815 | return -ENODEV; | |
816 | } | |
817 | EXPORT_SYMBOL(pci_device_from_OF_node); | |
818 | ||
819 | void __init | |
820 | pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
821 | struct device_node *dev, int primary) | |
822 | { | |
823 | static unsigned int static_lc_ranges[256] __initdata; | |
a7f67bdf JK |
824 | const unsigned int *dt_ranges; |
825 | unsigned int *lc_ranges, *ranges, *prev, size; | |
e05b3b4a PM |
826 | int rlen = 0, orig_rlen; |
827 | int memno = 0; | |
828 | struct resource *res; | |
a8bda5dd | 829 | int np, na = of_n_addr_cells(dev); |
e05b3b4a PM |
830 | np = na + 5; |
831 | ||
832 | /* First we try to merge ranges to fix a problem with some pmacs | |
833 | * that can have more than 3 ranges, fortunately using contiguous | |
834 | * addresses -- BenH | |
835 | */ | |
e2eb6392 | 836 | dt_ranges = of_get_property(dev, "ranges", &rlen); |
e05b3b4a PM |
837 | if (!dt_ranges) |
838 | return; | |
839 | /* Sanity check, though hopefully that never happens */ | |
840 | if (rlen > sizeof(static_lc_ranges)) { | |
841 | printk(KERN_WARNING "OF ranges property too large !\n"); | |
842 | rlen = sizeof(static_lc_ranges); | |
843 | } | |
844 | lc_ranges = static_lc_ranges; | |
845 | memcpy(lc_ranges, dt_ranges, rlen); | |
846 | orig_rlen = rlen; | |
847 | ||
848 | /* Let's work on a copy of the "ranges" property instead of damaging | |
849 | * the device-tree image in memory | |
850 | */ | |
851 | ranges = lc_ranges; | |
852 | prev = NULL; | |
853 | while ((rlen -= np * sizeof(unsigned int)) >= 0) { | |
854 | if (prev) { | |
855 | if (prev[0] == ranges[0] && prev[1] == ranges[1] && | |
856 | (prev[2] + prev[na+4]) == ranges[2] && | |
857 | (prev[na+2] + prev[na+4]) == ranges[na+2]) { | |
858 | prev[na+4] += ranges[na+4]; | |
859 | ranges[0] = 0; | |
860 | ranges += np; | |
861 | continue; | |
862 | } | |
863 | } | |
864 | prev = ranges; | |
865 | ranges += np; | |
866 | } | |
867 | ||
868 | /* | |
869 | * The ranges property is laid out as an array of elements, | |
870 | * each of which comprises: | |
871 | * cells 0 - 2: a PCI address | |
872 | * cells 3 or 3+4: a CPU physical address | |
873 | * (size depending on dev->n_addr_cells) | |
874 | * cells 4+5 or 5+6: the size of the range | |
875 | */ | |
876 | ranges = lc_ranges; | |
877 | rlen = orig_rlen; | |
878 | while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) { | |
879 | res = NULL; | |
880 | size = ranges[na+4]; | |
881 | switch ((ranges[0] >> 24) & 0x3) { | |
882 | case 1: /* I/O space */ | |
883 | if (ranges[2] != 0) | |
884 | break; | |
885 | hose->io_base_phys = ranges[na+2]; | |
886 | /* limit I/O space to 16MB */ | |
887 | if (size > 0x01000000) | |
888 | size = 0x01000000; | |
889 | hose->io_base_virt = ioremap(ranges[na+2], size); | |
890 | if (primary) | |
891 | isa_io_base = (unsigned long) hose->io_base_virt; | |
892 | res = &hose->io_resource; | |
893 | res->flags = IORESOURCE_IO; | |
894 | res->start = ranges[2]; | |
685143ac | 895 | DBG("PCI: IO 0x%llx -> 0x%llx\n", |
872455e2 | 896 | (u64)res->start, (u64)res->start + size - 1); |
e05b3b4a PM |
897 | break; |
898 | case 2: /* memory space */ | |
899 | memno = 0; | |
900 | if (ranges[1] == 0 && ranges[2] == 0 | |
901 | && ranges[na+4] <= (16 << 20)) { | |
902 | /* 1st 16MB, i.e. ISA memory area */ | |
903 | if (primary) | |
904 | isa_mem_base = ranges[na+2]; | |
905 | memno = 1; | |
906 | } | |
907 | while (memno < 3 && hose->mem_resources[memno].flags) | |
908 | ++memno; | |
909 | if (memno == 0) | |
910 | hose->pci_mem_offset = ranges[na+2] - ranges[2]; | |
911 | if (memno < 3) { | |
912 | res = &hose->mem_resources[memno]; | |
913 | res->flags = IORESOURCE_MEM; | |
914 | if(ranges[0] & 0x40000000) | |
915 | res->flags |= IORESOURCE_PREFETCH; | |
916 | res->start = ranges[na+2]; | |
685143ac | 917 | DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno, |
872455e2 | 918 | (u64)res->start, (u64)res->start + size - 1); |
e05b3b4a PM |
919 | } |
920 | break; | |
921 | } | |
922 | if (res != NULL) { | |
923 | res->name = dev->full_name; | |
924 | res->end = res->start + size - 1; | |
925 | res->parent = NULL; | |
926 | res->sibling = NULL; | |
927 | res->child = NULL; | |
928 | } | |
929 | ranges += np; | |
930 | } | |
931 | } | |
932 | ||
933 | /* We create the "pci-OF-bus-map" property now so it appears in the | |
934 | * /proc device tree | |
935 | */ | |
936 | void __init | |
937 | pci_create_OF_bus_map(void) | |
938 | { | |
939 | struct property* of_prop; | |
8c8dc322 SR |
940 | struct device_node *dn; |
941 | ||
e05b3b4a | 942 | of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256); |
8c8dc322 SR |
943 | if (!of_prop) |
944 | return; | |
945 | dn = of_find_node_by_path("/"); | |
946 | if (dn) { | |
e05b3b4a PM |
947 | memset(of_prop, -1, sizeof(struct property) + 256); |
948 | of_prop->name = "pci-OF-bus-map"; | |
949 | of_prop->length = 256; | |
1a38147e | 950 | of_prop->value = &of_prop[1]; |
8c8dc322 SR |
951 | prom_add_property(dn, of_prop); |
952 | of_node_put(dn); | |
e05b3b4a PM |
953 | } |
954 | } | |
955 | ||
e05b3b4a PM |
956 | #else /* CONFIG_PPC_OF */ |
957 | void pcibios_make_OF_bus_map(void) | |
958 | { | |
959 | } | |
960 | #endif /* CONFIG_PPC_OF */ | |
961 | ||
e05b3b4a PM |
962 | #ifdef CONFIG_PPC_PMAC |
963 | /* | |
964 | * This set of routines checks for PCI<->PCI bridges that have closed | |
965 | * IO resources and have child devices. It tries to re-open an IO | |
966 | * window on them. | |
967 | * | |
968 | * This is a _temporary_ fix to workaround a problem with Apple's OF | |
969 | * closing IO windows on P2P bridges when the OF drivers of cards | |
970 | * below this bridge don't claim any IO range (typically ATI or | |
971 | * Adaptec). | |
972 | * | |
973 | * A more complete fix would be to use drivers/pci/setup-bus.c, which | |
974 | * involves a working pcibios_fixup_pbus_ranges(), some more care about | |
975 | * ordering when creating the host bus resources, and maybe a few more | |
976 | * minor tweaks | |
977 | */ | |
978 | ||
979 | /* Initialize bridges with base/limit values we have collected */ | |
980 | static void __init | |
981 | do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga) | |
982 | { | |
983 | struct pci_dev *bridge = bus->self; | |
984 | struct pci_controller* hose = (struct pci_controller *)bridge->sysdata; | |
985 | u32 l; | |
986 | u16 w; | |
987 | struct resource res; | |
988 | ||
989 | if (bus->resource[0] == NULL) | |
990 | return; | |
991 | res = *(bus->resource[0]); | |
992 | ||
993 | DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge)); | |
994 | res.start -= ((unsigned long) hose->io_base_virt - isa_io_base); | |
995 | res.end -= ((unsigned long) hose->io_base_virt - isa_io_base); | |
685143ac | 996 | DBG(" IO window: %016llx-%016llx\n", res.start, res.end); |
e05b3b4a PM |
997 | |
998 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
999 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); | |
1000 | l &= 0xffff000f; | |
1001 | l |= (res.start >> 8) & 0x00f0; | |
1002 | l |= res.end & 0xf000; | |
1003 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
1004 | ||
1005 | if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
1006 | l = (res.start >> 16) | (res.end & 0xffff0000); | |
1007 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l); | |
1008 | } | |
1009 | ||
1010 | pci_read_config_word(bridge, PCI_COMMAND, &w); | |
1011 | w |= PCI_COMMAND_IO; | |
1012 | pci_write_config_word(bridge, PCI_COMMAND, w); | |
1013 | ||
1014 | #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */ | |
1015 | if (enable_vga) { | |
1016 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w); | |
1017 | w |= PCI_BRIDGE_CTL_VGA; | |
1018 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w); | |
1019 | } | |
1020 | #endif | |
1021 | } | |
1022 | ||
1023 | /* This function is pretty basic and actually quite broken for the | |
1024 | * general case, it's enough for us right now though. It's supposed | |
1025 | * to tell us if we need to open an IO range at all or not and what | |
1026 | * size. | |
1027 | */ | |
1028 | static int __init | |
1029 | check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga) | |
1030 | { | |
1031 | struct pci_dev *dev; | |
1032 | int i; | |
1033 | int rc = 0; | |
1034 | ||
0f582bc1 PM |
1035 | #define push_end(res, mask) do { \ |
1036 | BUG_ON((mask+1) & mask); \ | |
1037 | res->end = (res->end + mask) | mask; \ | |
1038 | } while (0) | |
e05b3b4a PM |
1039 | |
1040 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1041 | u16 class = dev->class >> 8; | |
1042 | ||
1043 | if (class == PCI_CLASS_DISPLAY_VGA || | |
1044 | class == PCI_CLASS_NOT_DEFINED_VGA) | |
1045 | *found_vga = 1; | |
1046 | if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate) | |
1047 | rc |= check_for_io_childs(dev->subordinate, res, found_vga); | |
1048 | if (class == PCI_CLASS_BRIDGE_CARDBUS) | |
1049 | push_end(res, 0xfff); | |
1050 | ||
1051 | for (i=0; i<PCI_NUM_RESOURCES; i++) { | |
1052 | struct resource *r; | |
1053 | unsigned long r_size; | |
1054 | ||
1055 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI | |
1056 | && i >= PCI_BRIDGE_RESOURCES) | |
1057 | continue; | |
1058 | r = &dev->resource[i]; | |
1059 | r_size = r->end - r->start; | |
1060 | if (r_size < 0xfff) | |
1061 | r_size = 0xfff; | |
1062 | if (r->flags & IORESOURCE_IO && (r_size) != 0) { | |
1063 | rc = 1; | |
1064 | push_end(res, r_size); | |
1065 | } | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | return rc; | |
1070 | } | |
1071 | ||
1072 | /* Here we scan all P2P bridges of a given level that have a closed | |
1073 | * IO window. Note that the test for the presence of a VGA card should | |
1074 | * be improved to take into account already configured P2P bridges, | |
1075 | * currently, we don't see them and might end up configuring 2 bridges | |
1076 | * with VGA pass through enabled | |
1077 | */ | |
1078 | static void __init | |
1079 | do_fixup_p2p_level(struct pci_bus *bus) | |
1080 | { | |
1081 | struct pci_bus *b; | |
1082 | int i, parent_io; | |
1083 | int has_vga = 0; | |
1084 | ||
1085 | for (parent_io=0; parent_io<4; parent_io++) | |
1086 | if (bus->resource[parent_io] | |
1087 | && bus->resource[parent_io]->flags & IORESOURCE_IO) | |
1088 | break; | |
1089 | if (parent_io >= 4) | |
1090 | return; | |
1091 | ||
1092 | list_for_each_entry(b, &bus->children, node) { | |
1093 | struct pci_dev *d = b->self; | |
1094 | struct pci_controller* hose = (struct pci_controller *)d->sysdata; | |
1095 | struct resource *res = b->resource[0]; | |
1096 | struct resource tmp_res; | |
1097 | unsigned long max; | |
1098 | int found_vga = 0; | |
1099 | ||
1100 | memset(&tmp_res, 0, sizeof(tmp_res)); | |
1101 | tmp_res.start = bus->resource[parent_io]->start; | |
1102 | ||
1103 | /* We don't let low addresses go through that closed P2P bridge, well, | |
1104 | * that may not be necessary but I feel safer that way | |
1105 | */ | |
1106 | if (tmp_res.start == 0) | |
1107 | tmp_res.start = 0x1000; | |
1108 | ||
1109 | if (!list_empty(&b->devices) && res && res->flags == 0 && | |
1110 | res != bus->resource[parent_io] && | |
1111 | (d->class >> 8) == PCI_CLASS_BRIDGE_PCI && | |
1112 | check_for_io_childs(b, &tmp_res, &found_vga)) { | |
1113 | u8 io_base_lo; | |
1114 | ||
1115 | printk(KERN_INFO "Fixing up IO bus %s\n", b->name); | |
1116 | ||
1117 | if (found_vga) { | |
1118 | if (has_vga) { | |
1119 | printk(KERN_WARNING "Skipping VGA, already active" | |
1120 | " on bus segment\n"); | |
1121 | found_vga = 0; | |
1122 | } else | |
1123 | has_vga = 1; | |
1124 | } | |
1125 | pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo); | |
1126 | ||
1127 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) | |
1128 | max = ((unsigned long) hose->io_base_virt | |
1129 | - isa_io_base) + 0xffffffff; | |
1130 | else | |
1131 | max = ((unsigned long) hose->io_base_virt | |
1132 | - isa_io_base) + 0xffff; | |
1133 | ||
1134 | *res = tmp_res; | |
1135 | res->flags = IORESOURCE_IO; | |
1136 | res->name = b->name; | |
1137 | ||
1138 | /* Find a resource in the parent where we can allocate */ | |
1139 | for (i = 0 ; i < 4; i++) { | |
1140 | struct resource *r = bus->resource[i]; | |
1141 | if (!r) | |
1142 | continue; | |
1143 | if ((r->flags & IORESOURCE_IO) == 0) | |
1144 | continue; | |
685143ac GKH |
1145 | DBG("Trying to allocate from %016llx, size %016llx from parent" |
1146 | " res %d: %016llx -> %016llx\n", | |
e05b3b4a PM |
1147 | res->start, res->end, i, r->start, r->end); |
1148 | ||
1149 | if (allocate_resource(r, res, res->end + 1, res->start, max, | |
1150 | res->end + 1, NULL, NULL) < 0) { | |
1151 | DBG("Failed !\n"); | |
1152 | continue; | |
1153 | } | |
1154 | do_update_p2p_io_resource(b, found_vga); | |
1155 | break; | |
1156 | } | |
1157 | } | |
1158 | do_fixup_p2p_level(b); | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | static void | |
1163 | pcibios_fixup_p2p_bridges(void) | |
1164 | { | |
1165 | struct pci_bus *b; | |
1166 | ||
1167 | list_for_each_entry(b, &pci_root_buses, node) | |
1168 | do_fixup_p2p_level(b); | |
1169 | } | |
1170 | ||
1171 | #endif /* CONFIG_PPC_PMAC */ | |
1172 | ||
1173 | static int __init | |
1174 | pcibios_init(void) | |
1175 | { | |
a4c9e328 | 1176 | struct pci_controller *hose, *tmp; |
e05b3b4a | 1177 | struct pci_bus *bus; |
a4c9e328 | 1178 | int next_busno = 0; |
e05b3b4a PM |
1179 | |
1180 | printk(KERN_INFO "PCI: Probing PCI hardware\n"); | |
1181 | ||
1182 | /* Scan all of the recorded PCI controllers. */ | |
a4c9e328 | 1183 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
e05b3b4a PM |
1184 | if (pci_assign_all_buses) |
1185 | hose->first_busno = next_busno; | |
1186 | hose->last_busno = 0xff; | |
803d4573 BH |
1187 | bus = pci_scan_bus_parented(hose->parent, hose->first_busno, |
1188 | hose->ops, hose); | |
1189 | if (bus) | |
1190 | pci_bus_add_devices(bus); | |
e05b3b4a PM |
1191 | hose->last_busno = bus->subordinate; |
1192 | if (pci_assign_all_buses || next_busno <= hose->last_busno) | |
1193 | next_busno = hose->last_busno + pcibios_assign_bus_offset; | |
1194 | } | |
1195 | pci_bus_count = next_busno; | |
1196 | ||
1197 | /* OpenFirmware based machines need a map of OF bus | |
1198 | * numbers vs. kernel bus numbers since we may have to | |
1199 | * remap them. | |
1200 | */ | |
1201 | if (pci_assign_all_buses && have_of) | |
1202 | pcibios_make_OF_bus_map(); | |
1203 | ||
e05b3b4a PM |
1204 | /* Call machine dependent fixup */ |
1205 | if (ppc_md.pcibios_fixup) | |
1206 | ppc_md.pcibios_fixup(); | |
1207 | ||
1208 | /* Allocate and assign resources */ | |
1209 | pcibios_allocate_bus_resources(&pci_root_buses); | |
1210 | pcibios_allocate_resources(0); | |
1211 | pcibios_allocate_resources(1); | |
1212 | #ifdef CONFIG_PPC_PMAC | |
1213 | pcibios_fixup_p2p_bridges(); | |
1214 | #endif /* CONFIG_PPC_PMAC */ | |
1215 | pcibios_assign_resources(); | |
1216 | ||
1217 | /* Call machine dependent post-init code */ | |
1218 | if (ppc_md.pcibios_after_init) | |
1219 | ppc_md.pcibios_after_init(); | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | subsys_initcall(pcibios_init); | |
1225 | ||
e05b3b4a PM |
1226 | void __init pcibios_fixup_bus(struct pci_bus *bus) |
1227 | { | |
1228 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; | |
1229 | unsigned long io_offset; | |
1230 | struct resource *res; | |
f90bb153 | 1231 | struct pci_dev *dev; |
e05b3b4a PM |
1232 | int i; |
1233 | ||
1234 | io_offset = (unsigned long)hose->io_base_virt - isa_io_base; | |
1235 | if (bus->parent == NULL) { | |
1236 | /* This is a host bridge - fill in its resources */ | |
1237 | hose->bus = bus; | |
1238 | ||
1239 | bus->resource[0] = res = &hose->io_resource; | |
1240 | if (!res->flags) { | |
1241 | if (io_offset) | |
1242 | printk(KERN_ERR "I/O resource not set for host" | |
5516b540 | 1243 | " bridge %d\n", hose->global_number); |
e05b3b4a PM |
1244 | res->start = 0; |
1245 | res->end = IO_SPACE_LIMIT; | |
1246 | res->flags = IORESOURCE_IO; | |
1247 | } | |
1248 | res->start += io_offset; | |
1249 | res->end += io_offset; | |
1250 | ||
1251 | for (i = 0; i < 3; ++i) { | |
1252 | res = &hose->mem_resources[i]; | |
1253 | if (!res->flags) { | |
1254 | if (i > 0) | |
1255 | continue; | |
1256 | printk(KERN_ERR "Memory resource not set for " | |
5516b540 | 1257 | "host bridge %d\n", hose->global_number); |
e05b3b4a PM |
1258 | res->start = hose->pci_mem_offset; |
1259 | res->end = ~0U; | |
1260 | res->flags = IORESOURCE_MEM; | |
1261 | } | |
1262 | bus->resource[i+1] = res; | |
1263 | } | |
1264 | } else { | |
1265 | /* This is a subordinate bridge */ | |
1266 | pci_read_bridge_bases(bus); | |
1267 | ||
1268 | for (i = 0; i < 4; ++i) { | |
1269 | if ((res = bus->resource[i]) == NULL) | |
1270 | continue; | |
6d8ff10c | 1271 | if (!res->flags || bus->self->transparent) |
e05b3b4a PM |
1272 | continue; |
1273 | if (io_offset && (res->flags & IORESOURCE_IO)) { | |
1274 | res->start += io_offset; | |
1275 | res->end += io_offset; | |
1276 | } else if (hose->pci_mem_offset | |
1277 | && (res->flags & IORESOURCE_MEM)) { | |
1278 | res->start += hose->pci_mem_offset; | |
1279 | res->end += hose->pci_mem_offset; | |
1280 | } | |
1281 | } | |
1282 | } | |
1283 | ||
f90bb153 | 1284 | /* Platform specific bus fixups */ |
e05b3b4a PM |
1285 | if (ppc_md.pcibios_fixup_bus) |
1286 | ppc_md.pcibios_fixup_bus(bus); | |
f90bb153 BH |
1287 | |
1288 | /* Read default IRQs and fixup if necessary */ | |
1289 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1290 | pci_read_irq_line(dev); | |
1291 | if (ppc_md.pci_irq_fixup) | |
1292 | ppc_md.pci_irq_fixup(dev); | |
1293 | } | |
e05b3b4a PM |
1294 | } |
1295 | ||
e05b3b4a PM |
1296 | /* the next one is stolen from the alpha port... */ |
1297 | void __init | |
1298 | pcibios_update_irq(struct pci_dev *dev, int irq) | |
1299 | { | |
1300 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
1301 | /* XXX FIXME - update OF device tree node interrupt property */ | |
1302 | } | |
1303 | ||
1304 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
1305 | { | |
1306 | u16 cmd, old_cmd; | |
1307 | int idx; | |
1308 | struct resource *r; | |
1309 | ||
1310 | if (ppc_md.pcibios_enable_device_hook) | |
1311 | if (ppc_md.pcibios_enable_device_hook(dev, 0)) | |
1312 | return -EINVAL; | |
1313 | ||
1314 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1315 | old_cmd = cmd; | |
1316 | for (idx=0; idx<6; idx++) { | |
1317 | r = &dev->resource[idx]; | |
1318 | if (r->flags & IORESOURCE_UNSET) { | |
1319 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); | |
1320 | return -EINVAL; | |
1321 | } | |
1322 | if (r->flags & IORESOURCE_IO) | |
1323 | cmd |= PCI_COMMAND_IO; | |
1324 | if (r->flags & IORESOURCE_MEM) | |
1325 | cmd |= PCI_COMMAND_MEMORY; | |
1326 | } | |
1327 | if (cmd != old_cmd) { | |
1328 | printk("PCI: Enabling device %s (%04x -> %04x)\n", | |
1329 | pci_name(dev), old_cmd, cmd); | |
1330 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1331 | } | |
1332 | return 0; | |
1333 | } | |
1334 | ||
0b1d40c4 | 1335 | static struct pci_controller* |
e05b3b4a PM |
1336 | pci_bus_to_hose(int bus) |
1337 | { | |
a4c9e328 | 1338 | struct pci_controller *hose, *tmp; |
e05b3b4a | 1339 | |
a4c9e328 | 1340 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) |
e05b3b4a PM |
1341 | if (bus >= hose->first_busno && bus <= hose->last_busno) |
1342 | return hose; | |
1343 | return NULL; | |
1344 | } | |
1345 | ||
e05b3b4a PM |
1346 | /* Provide information on locations of various I/O regions in physical |
1347 | * memory. Do this on a per-card basis so that we choose the right | |
1348 | * root bridge. | |
1349 | * Note that the returned IO or memory base is a physical address | |
1350 | */ | |
1351 | ||
1352 | long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) | |
1353 | { | |
1354 | struct pci_controller* hose; | |
1355 | long result = -EOPNOTSUPP; | |
1356 | ||
1357 | /* Argh ! Please forgive me for that hack, but that's the | |
1358 | * simplest way to get existing XFree to not lockup on some | |
1359 | * G5 machines... So when something asks for bus 0 io base | |
1360 | * (bus 0 is HT root), we return the AGP one instead. | |
1361 | */ | |
1362 | #ifdef CONFIG_PPC_PMAC | |
e8222502 | 1363 | if (machine_is(powermac) && machine_is_compatible("MacRISC4")) |
e05b3b4a PM |
1364 | if (bus == 0) |
1365 | bus = 0xf0; | |
1366 | #endif /* CONFIG_PPC_PMAC */ | |
1367 | ||
1368 | hose = pci_bus_to_hose(bus); | |
1369 | if (!hose) | |
1370 | return -ENODEV; | |
1371 | ||
1372 | switch (which) { | |
1373 | case IOBASE_BRIDGE_NUMBER: | |
1374 | return (long)hose->first_busno; | |
1375 | case IOBASE_MEMORY: | |
1376 | return (long)hose->pci_mem_offset; | |
1377 | case IOBASE_IO: | |
1378 | return (long)hose->io_base_phys; | |
1379 | case IOBASE_ISA_IO: | |
1380 | return (long)isa_io_base; | |
1381 | case IOBASE_ISA_MEM: | |
1382 | return (long)isa_mem_base; | |
1383 | } | |
1384 | ||
1385 | return result; | |
1386 | } | |
1387 | ||
e05b3b4a PM |
1388 | unsigned long pci_address_to_pio(phys_addr_t address) |
1389 | { | |
a4c9e328 | 1390 | struct pci_controller *hose, *tmp; |
e05b3b4a | 1391 | |
a4c9e328 | 1392 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
e05b3b4a PM |
1393 | unsigned int size = hose->io_resource.end - |
1394 | hose->io_resource.start + 1; | |
1395 | if (address >= hose->io_base_phys && | |
1396 | address < (hose->io_base_phys + size)) { | |
1397 | unsigned long base = | |
1398 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
1399 | return base + (address - hose->io_base_phys); | |
1400 | } | |
1401 | } | |
1402 | return (unsigned int)-1; | |
1403 | } | |
1404 | EXPORT_SYMBOL(pci_address_to_pio); | |
1405 | ||
1406 | /* | |
1407 | * Null PCI config access functions, for the case when we can't | |
1408 | * find a hose. | |
1409 | */ | |
1410 | #define NULL_PCI_OP(rw, size, type) \ | |
1411 | static int \ | |
1412 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1413 | { \ | |
1414 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1415 | } | |
1416 | ||
1417 | static int | |
1418 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1419 | int len, u32 *val) | |
1420 | { | |
1421 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1422 | } | |
1423 | ||
1424 | static int | |
1425 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1426 | int len, u32 val) | |
1427 | { | |
1428 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1429 | } | |
1430 | ||
1431 | static struct pci_ops null_pci_ops = | |
1432 | { | |
1433 | null_read_config, | |
1434 | null_write_config | |
1435 | }; | |
1436 | ||
1437 | /* | |
1438 | * These functions are used early on before PCI scanning is done | |
1439 | * and all of the pci_dev and pci_bus structures have been created. | |
1440 | */ | |
1441 | static struct pci_bus * | |
1442 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1443 | { | |
1444 | static struct pci_bus bus; | |
1445 | ||
1446 | if (hose == 0) { | |
1447 | hose = pci_bus_to_hose(busnr); | |
1448 | if (hose == 0) | |
1449 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); | |
1450 | } | |
1451 | bus.number = busnr; | |
1452 | bus.sysdata = hose; | |
1453 | bus.ops = hose? hose->ops: &null_pci_ops; | |
1454 | return &bus; | |
1455 | } | |
1456 | ||
1457 | #define EARLY_PCI_OP(rw, size, type) \ | |
1458 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1459 | int devfn, int offset, type value) \ | |
1460 | { \ | |
1461 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1462 | devfn, offset, value); \ | |
1463 | } | |
1464 | ||
1465 | EARLY_PCI_OP(read, byte, u8 *) | |
1466 | EARLY_PCI_OP(read, word, u16 *) | |
1467 | EARLY_PCI_OP(read, dword, u32 *) | |
1468 | EARLY_PCI_OP(write, byte, u8) | |
1469 | EARLY_PCI_OP(write, word, u16) | |
1470 | EARLY_PCI_OP(write, dword, u32) |