[deliverable/linux.git] / arch / powerpc / kernel / pci_32.c

/*
 * Common pmac/prep/chrp pci routines. -- Cort
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/capability.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <linux/list.h>

#include <asm/processor.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/sections.h>
#include <asm/pci-bridge.h>
#include <asm/byteorder.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>

#undef DEBUG

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

unsigned long isa_io_base     = 0;
unsigned long pci_dram_offset = 0;
int pcibios_assign_bus_offset = 1;

void pcibios_make_OF_bus_map(void);

static void fixup_broken_pcnet32(struct pci_dev* dev);
static void fixup_cpc710_pci64(struct pci_dev* dev);
#ifdef CONFIG_PPC_OF
static u8* pci_to_OF_bus_map;
#endif

/* By default, we don't re-assign bus numbers. We do this only on
 * some pmacs
 */
static int pci_assign_all_buses;

LIST_HEAD(hose_list);

static int pci_bus_count;

static void
fixup_hide_host_resource_fsl(struct pci_dev* dev)
{
	int i, class = dev->class >> 8;

	if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
		(dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
		(dev->bus->parent == NULL)) {
		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 

static void
fixup_broken_pcnet32(struct pci_dev* dev)
{
	if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
		dev->vendor = PCI_VENDOR_ID_AMD;
		pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT,	PCI_ANY_ID,			fixup_broken_pcnet32);

static void
fixup_cpc710_pci64(struct pci_dev* dev)
{
	/* Hide the PCI64 BARs from the kernel as their content doesn't
	 * fit well in the resource management
	 */
	dev->resource[0].start = dev->resource[0].end = 0;
	dev->resource[0].flags = 0;
	dev->resource[1].start = dev->resource[1].end = 0;
	dev->resource[1].flags = 0;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CPC710_PCI64,	fixup_cpc710_pci64);


void __init
update_bridge_resource(struct pci_dev *dev, struct resource *res)
{
	u8 io_base_lo, io_limit_lo;
	u16 mem_base, mem_limit;
	u16 cmd;
	resource_size_t start, end, off;
	struct pci_controller *hose = dev->sysdata;

	if (!hose) {
		printk("update_bridge_base: no hose?\n");
		return;
	}
	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	pci_write_config_word(dev, PCI_COMMAND,
			      cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
	if (res->flags & IORESOURCE_IO) {
		off = (unsigned long) hose->io_base_virt - isa_io_base;
		start = res->start - off;
		end = res->end - off;
		io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
		io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
		if (end > 0xffff)
			io_base_lo |= PCI_IO_RANGE_TYPE_32;
		else
			io_base_lo |= PCI_IO_RANGE_TYPE_16;
		pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
				start >> 16);
		pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
				end >> 16);
		pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
		pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);

	} else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
		   == IORESOURCE_MEM) {
		off = hose->pci_mem_offset;
		mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
		mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
		pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
		pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);

	} else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
		   == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
		off = hose->pci_mem_offset;
		mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
		mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
		pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
		pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);

	} else {
		DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
		    pci_name(dev), res->flags);
	}
	pci_write_config_word(dev, PCI_COMMAND, cmd);
}


#ifdef CONFIG_PPC_OF
/*
 * Functions below are used on OpenFirmware machines.
 */
static void
make_one_node_map(struct device_node* node, u8 pci_bus)
{
	const int *bus_range;
	int len;

	if (pci_bus >= pci_bus_count)
		return;
	bus_range = of_get_property(node, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int)) {
		printk(KERN_WARNING "Can't get bus-range for %s, "
		       "assuming it starts at 0\n", node->full_name);
		pci_to_OF_bus_map[pci_bus] = 0;
	} else
		pci_to_OF_bus_map[pci_bus] = bus_range[0];

	for (node=node->child; node != 0;node = node->sibling) {
		struct pci_dev* dev;
		const unsigned int *class_code, *reg;
	
		class_code = of_get_property(node, "class-code", NULL);
		if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
			(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
			continue;
		reg = of_get_property(node, "reg", NULL);
		if (!reg)
			continue;
		dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
		if (!dev || !dev->subordinate) {
			pci_dev_put(dev);
			continue;
		}
		make_one_node_map(node, dev->subordinate->number);
		pci_dev_put(dev);
	}
}
	
void
pcibios_make_OF_bus_map(void)
{
	int i;
	struct pci_controller *hose, *tmp;
	struct property *map_prop;
	struct device_node *dn;

	pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
	if (!pci_to_OF_bus_map) {
		printk(KERN_ERR "Can't allocate OF bus map !\n");
		return;
	}

	/* We fill the bus map with invalid values, that helps
	 * debugging.
	 */
	for (i=0; i<pci_bus_count; i++)
		pci_to_OF_bus_map[i] = 0xff;

	/* For each hose, we begin searching bridges */
	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		struct device_node* node = hose->dn;

		if (!node)
			continue;
		make_one_node_map(node, hose->first_busno);
	}
	dn = of_find_node_by_path("/");
	map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
	if (map_prop) {
		BUG_ON(pci_bus_count > map_prop->length);
		memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
	}
	of_node_put(dn);
#ifdef DEBUG
	printk("PCI->OF bus map:\n");
	for (i=0; i<pci_bus_count; i++) {
		if (pci_to_OF_bus_map[i] == 0xff)
			continue;
		printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
	}
#endif
}

typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);

static struct device_node*
scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
{
	struct device_node* sub_node;

	for (; node != 0;node = node->sibling) {
		const unsigned int *class_code;
	
		if (filter(node, data))
			return node;

		/* For PCI<->PCI bridges or CardBus bridges, we go down
		 * Note: some OFs create a parent node "multifunc-device" as
		 * a fake root for all functions of a multi-function device,
		 * we go down them as well.
		 */
		class_code = of_get_property(node, "class-code", NULL);
		if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
			(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
			strcmp(node->name, "multifunc-device"))
			continue;
		sub_node = scan_OF_pci_childs(node->child, filter, data);
		if (sub_node)
			return sub_node;
	}
	return NULL;
}

static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
					       unsigned int devfn)
{
	struct device_node *np = NULL;
	const u32 *reg;
	unsigned int psize;

	while ((np = of_get_next_child(parent, np)) != NULL) {
		reg = of_get_property(np, "reg", &psize);
		if (reg == NULL || psize < 4)
			continue;
		if (((reg[0] >> 8) & 0xff) == devfn)
			return np;
	}
	return NULL;
}


static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
{
	struct device_node *parent, *np;

	/* Are we a root bus ? */
	if (bus->self == NULL || bus->parent == NULL) {
		struct pci_controller *hose = pci_bus_to_host(bus);
		if (hose == NULL)
			return NULL;
		return of_node_get(hose->dn);
	}

	/* not a root bus, we need to get our parent */
	parent = scan_OF_for_pci_bus(bus->parent);
	if (parent == NULL)
		return NULL;

	/* now iterate for children for a match */
	np = scan_OF_for_pci_dev(parent, bus->self->devfn);
	of_node_put(parent);

	return np;
}

/*
 * Scans the OF tree for a device node matching a PCI device
 */
struct device_node *
pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
{
	struct device_node *parent, *np;

	if (!have_of)
		return NULL;

	DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
	parent = scan_OF_for_pci_bus(bus);
	if (parent == NULL)
		return NULL;
	DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
	np = scan_OF_for_pci_dev(parent, devfn);
	of_node_put(parent);
	DBG(" result is %s\n", np ? np->full_name : "<NULL>");

	/* XXX most callers don't release the returned node
	 * mostly because ppc64 doesn't increase the refcount,
	 * we need to fix that.
	 */
	return np;
}
EXPORT_SYMBOL(pci_busdev_to_OF_node);

struct device_node*
pci_device_to_OF_node(struct pci_dev *dev)
{
	return pci_busdev_to_OF_node(dev->bus, dev->devfn);
}
EXPORT_SYMBOL(pci_device_to_OF_node);

static int
find_OF_pci_device_filter(struct device_node* node, void* data)
{
	return ((void *)node == data);
}

/*
 * Returns the PCI device matching a given OF node
 */
int
pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
{
	const unsigned int *reg;
	struct pci_controller* hose;
	struct pci_dev* dev = NULL;
	
	if (!have_of)
		return -ENODEV;
	/* Make sure it's really a PCI device */
	hose = pci_find_hose_for_OF_device(node);
	if (!hose || !hose->dn)
		return -ENODEV;
	if (!scan_OF_pci_childs(hose->dn->child,
			find_OF_pci_device_filter, (void *)node))
		return -ENODEV;
	reg = of_get_property(node, "reg", NULL);
	if (!reg)
		return -ENODEV;
	*bus = (reg[0] >> 16) & 0xff;
	*devfn = ((reg[0] >> 8) & 0xff);

	/* Ok, here we need some tweak. If we have already renumbered
	 * all busses, we can't rely on the OF bus number any more.
	 * the pci_to_OF_bus_map is not enough as several PCI busses
	 * may match the same OF bus number.
	 */
	if (!pci_to_OF_bus_map)
		return 0;

	for_each_pci_dev(dev)
		if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
				dev->devfn == *devfn) {
			*bus = dev->bus->number;
			pci_dev_put(dev);
			return 0;
		}

	return -ENODEV;
}
EXPORT_SYMBOL(pci_device_from_OF_node);

/* We create the "pci-OF-bus-map" property now so it appears in the
 * /proc device tree
 */
void __init
pci_create_OF_bus_map(void)
{
	struct property* of_prop;
	struct device_node *dn;

	of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
	if (!of_prop)
		return;
	dn = of_find_node_by_path("/");
	if (dn) {
		memset(of_prop, -1, sizeof(struct property) + 256);
		of_prop->name = "pci-OF-bus-map";
		of_prop->length = 256;
		of_prop->value = &of_prop[1];
		prom_add_property(dn, of_prop);
		of_node_put(dn);
	}
}

#else /* CONFIG_PPC_OF */
void pcibios_make_OF_bus_map(void)
{
}
#endif /* CONFIG_PPC_OF */

static int __init pcibios_init(void)
{
	struct pci_controller *hose, *tmp;
	struct pci_bus *bus;
	int next_busno = 0;

	printk(KERN_INFO "PCI: Probing PCI hardware\n");

	if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_BUS)
		pci_assign_all_buses = 1;

	/* Scan all of the recorded PCI controllers.  */
	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		if (pci_assign_all_buses)
			hose->first_busno = next_busno;
		hose->last_busno = 0xff;
		bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
					    hose->ops, hose);
		if (bus) {
			pci_bus_add_devices(bus);
			hose->last_busno = bus->subordinate;
		}
		if (pci_assign_all_buses || next_busno <= hose->last_busno)
			next_busno = hose->last_busno + pcibios_assign_bus_offset;
	}
	pci_bus_count = next_busno;

	/* OpenFirmware based machines need a map of OF bus
	 * numbers vs. kernel bus numbers since we may have to
	 * remap them.
	 */
	if (pci_assign_all_buses && have_of)
		pcibios_make_OF_bus_map();

	/* Call common code to handle resource allocation */
	pcibios_resource_survey();

	/* Call machine dependent post-init code */
	if (ppc_md.pcibios_after_init)
		ppc_md.pcibios_after_init();

	return 0;
}

subsys_initcall(pcibios_init);

void __devinit pcibios_do_bus_setup(struct pci_bus *bus)
{
	struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
	unsigned long io_offset;
	struct resource *res;
	int i;

	/* Hookup PHB resources */
	io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
	if (bus->parent == NULL) {
		/* This is a host bridge - fill in its resources */
		hose->bus = bus;

		bus->resource[0] = res = &hose->io_resource;
		if (!res->flags) {
			if (io_offset)
				printk(KERN_ERR "I/O resource not set for host"
				       " bridge %d\n", hose->global_number);
			res->start = 0;
			res->end = IO_SPACE_LIMIT;
			res->flags = IORESOURCE_IO;
		}
		res->start = (res->start + io_offset) & 0xffffffffu;
		res->end = (res->end + io_offset) & 0xffffffffu;

		for (i = 0; i < 3; ++i) {
			res = &hose->mem_resources[i];
			if (!res->flags) {
				if (i > 0)
					continue;
				printk(KERN_ERR "Memory resource not set for "
				       "host bridge %d\n", hose->global_number);
				res->start = hose->pci_mem_offset;
				res->end = ~0U;
				res->flags = IORESOURCE_MEM;
			}
			bus->resource[i+1] = res;
		}
	}
}

/* the next one is stolen from the alpha port... */
void __init
pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	/* XXX FIXME - update OF device tree node interrupt property */
}

static struct pci_controller*
pci_bus_to_hose(int bus)
{
	struct pci_controller *hose, *tmp;

	list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
		if (bus >= hose->first_busno && bus <= hose->last_busno)
			return hose;
	return NULL;
}

/* Provide information on locations of various I/O regions in physical
 * memory.  Do this on a per-card basis so that we choose the right
 * root bridge.
 * Note that the returned IO or memory base is a physical address
 */

long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
{
	struct pci_controller* hose;
	long result = -EOPNOTSUPP;

	hose = pci_bus_to_hose(bus);
	if (!hose)
		return -ENODEV;

	switch (which) {
	case IOBASE_BRIDGE_NUMBER:
		return (long)hose->first_busno;
	case IOBASE_MEMORY:
		return (long)hose->pci_mem_offset;
	case IOBASE_IO:
		return (long)hose->io_base_phys;
	case IOBASE_ISA_IO:
		return (long)isa_io_base;
	case IOBASE_ISA_MEM:
		return (long)isa_mem_base;
	}

	return result;
}

unsigned long pci_address_to_pio(phys_addr_t address)
{
	struct pci_controller *hose, *tmp;

	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		unsigned int size = hose->io_resource.end -
			hose->io_resource.start + 1;
		if (address >= hose->io_base_phys &&
		    address < (hose->io_base_phys + size)) {
			unsigned long base =
				(unsigned long)hose->io_base_virt - _IO_BASE;
			return base + (address - hose->io_base_phys);
		}
	}
	return (unsigned int)-1;
}
EXPORT_SYMBOL(pci_address_to_pio);

/*
 * Null PCI config access functions, for the case when we can't
 * find a hose.
 */
#define NULL_PCI_OP(rw, size, type)					\
static int								\
null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)	\
{									\
	return PCIBIOS_DEVICE_NOT_FOUND;    				\
}

static int
null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
		 int len, u32 *val)
{
	return PCIBIOS_DEVICE_NOT_FOUND;
}

static int
null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
		  int len, u32 val)
{
	return PCIBIOS_DEVICE_NOT_FOUND;
}

static struct pci_ops null_pci_ops =
{
	.read = null_read_config,
	.write = null_write_config,
};

/*
 * These functions are used early on before PCI scanning is done
 * and all of the pci_dev and pci_bus structures have been created.
 */
static struct pci_bus *
fake_pci_bus(struct pci_controller *hose, int busnr)
{
	static struct pci_bus bus;

	if (hose == 0) {
		hose = pci_bus_to_hose(busnr);
		if (hose == 0)
			printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
	}
	bus.number = busnr;
	bus.sysdata = hose;
	bus.ops = hose? hose->ops: &null_pci_ops;
	return &bus;
}

#define EARLY_PCI_OP(rw, size, type)					\
int early_##rw##_config_##size(struct pci_controller *hose, int bus,	\
			       int devfn, int offset, type value)	\
{									\
	return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),	\
					    devfn, offset, value);	\
}

EARLY_PCI_OP(read, byte, u8 *)
EARLY_PCI_OP(read, word, u16 *)
EARLY_PCI_OP(read, dword, u32 *)
EARLY_PCI_OP(write, byte, u8)
EARLY_PCI_OP(write, word, u16)
EARLY_PCI_OP(write, dword, u32)

extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
int early_find_capability(struct pci_controller *hose, int bus, int devfn,
			  int cap)
{
	return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
}
Commit	Line	Data
e05b3b4a PM	1	/*
	2	* Common pmac/prep/chrp pci routines. -- Cort
	3	*/
	4
e05b3b4a PM	5	#include <linux/kernel.h>
	6	#include <linux/pci.h>
	7	#include <linux/delay.h>
	8	#include <linux/string.h>
	9	#include <linux/init.h>
	10	#include <linux/capability.h>
	11	#include <linux/sched.h>
	12	#include <linux/errno.h>
	13	#include <linux/bootmem.h>
6e99e458	14	#include <linux/irq.h>
f90bb153	15	#include <linux/list.h>
e05b3b4a PM	16
	17	#include <asm/processor.h>
	18	#include <asm/io.h>
	19	#include <asm/prom.h>
	20	#include <asm/sections.h>
	21	#include <asm/pci-bridge.h>
	22	#include <asm/byteorder.h>
e05b3b4a PM	23	#include <asm/uaccess.h>
	24	#include <asm/machdep.h>
	25
	26	#undef DEBUG
	27
	28	#ifdef DEBUG
	29	#define DBG(x...) printk(x)
	30	#else
	31	#define DBG(x...)
	32	#endif
	33
	34	unsigned long isa_io_base = 0;
e05b3b4a PM	35	unsigned long pci_dram_offset = 0;
	36	int pcibios_assign_bus_offset = 1;
	37
	38	void pcibios_make_OF_bus_map(void);
	39
e05b3b4a	40	static void fixup_broken_pcnet32(struct pci_dev* dev);
e05b3b4a PM	41	static void fixup_cpc710_pci64(struct pci_dev* dev);
	42	#ifdef CONFIG_PPC_OF
	43	static u8* pci_to_OF_bus_map;
	44	#endif
	45
	46	/* By default, we don't re-assign bus numbers. We do this only on
	47	* some pmacs
	48	*/
fc3fb71c	49	static int pci_assign_all_buses;
e05b3b4a	50
a4c9e328	51	LIST_HEAD(hose_list);
e05b3b4a PM	52
	53	static int pci_bus_count;
	54
2052d6d2 KG	55	static void
	56	fixup_hide_host_resource_fsl(struct pci_dev* dev)
	57	{
	58	int i, class = dev->class >> 8;
	59
	60	if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
	61	(dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
	62	(dev->bus->parent == NULL)) {
	63	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	64	dev->resource[i].start = 0;
	65	dev->resource[i].end = 0;
	66	dev->resource[i].flags = 0;
	67	}
	68	}
	69	}
	70	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
	71	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
	72
e05b3b4a PM	73	static void
	74	fixup_broken_pcnet32(struct pci_dev* dev)
	75	{
	76	if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
	77	dev->vendor = PCI_VENDOR_ID_AMD;
	78	pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
	79	}
	80	}
	81	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
	82
	83	static void
	84	fixup_cpc710_pci64(struct pci_dev* dev)
	85	{
	86	/* Hide the PCI64 BARs from the kernel as their content doesn't
	87	* fit well in the resource management
	88	*/
	89	dev->resource[0].start = dev->resource[0].end = 0;
	90	dev->resource[0].flags = 0;
	91	dev->resource[1].start = dev->resource[1].end = 0;
	92	dev->resource[1].flags = 0;
	93	}
	94	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
	95
e05b3b4a	96
f64fddbe KG	97	void __init
f64fddbe KG	98	update_bridge_resource(struct pci_dev dev, struct resource res)
e05b3b4a	99	{
e05b3b4a PM	100	u8 io_base_lo, io_limit_lo;
	101	u16 mem_base, mem_limit;
	102	u16 cmd;
05d3957e	103	resource_size_t start, end, off;
e05b3b4a PM	104	struct pci_controller *hose = dev->sysdata;
	105
	106	if (!hose) {
	107	printk("update_bridge_base: no hose?\n");
	108	return;
	109	}
	110	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	111	pci_write_config_word(dev, PCI_COMMAND,
	112	cmd & ~(PCI_COMMAND_IO \| PCI_COMMAND_MEMORY));
	113	if (res->flags & IORESOURCE_IO) {
	114	off = (unsigned long) hose->io_base_virt - isa_io_base;
	115	start = res->start - off;
	116	end = res->end - off;
	117	io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
	118	io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
60b2a46c	119	if (end > 0xffff)
e05b3b4a	120	io_base_lo \|= PCI_IO_RANGE_TYPE_32;
60b2a46c	121	else
e05b3b4a	122	io_base_lo \|= PCI_IO_RANGE_TYPE_16;
60b2a46c RV	123	pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
	124	start >> 16);
	125	pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
	126	end >> 16);
e05b3b4a PM	127	pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
	128	pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
	129
	130	} else if ((res->flags & (IORESOURCE_MEM \| IORESOURCE_PREFETCH))
	131	== IORESOURCE_MEM) {
	132	off = hose->pci_mem_offset;
	133	mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
	134	mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
	135	pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
	136	pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
	137
	138	} else if ((res->flags & (IORESOURCE_MEM \| IORESOURCE_PREFETCH))
	139	== (IORESOURCE_MEM \| IORESOURCE_PREFETCH)) {
	140	off = hose->pci_mem_offset;
	141	mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
	142	mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
	143	pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
	144	pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
	145
	146	} else {
f64fddbe KG	147	DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
f64fddbe KG	148	pci_name(dev), res->flags);
e05b3b4a PM	149	}
	150	pci_write_config_word(dev, PCI_COMMAND, cmd);
	151	}
	152
e05b3b4a	153
e05b3b4a PM	154	#ifdef CONFIG_PPC_OF
	155	/*
	156	* Functions below are used on OpenFirmware machines.
	157	*/
	158	static void
	159	make_one_node_map(struct device_node* node, u8 pci_bus)
	160	{
a7f67bdf	161	const int *bus_range;
e05b3b4a PM	162	int len;
	163
	164	if (pci_bus >= pci_bus_count)
	165	return;
e2eb6392	166	bus_range = of_get_property(node, "bus-range", &len);
e05b3b4a PM	167	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	168	printk(KERN_WARNING "Can't get bus-range for %s, "
	169	"assuming it starts at 0\n", node->full_name);
	170	pci_to_OF_bus_map[pci_bus] = 0;
	171	} else
	172	pci_to_OF_bus_map[pci_bus] = bus_range[0];
	173
	174	for (node=node->child; node != 0;node = node->sibling) {
	175	struct pci_dev* dev;
a7f67bdf	176	const unsigned int class_code, reg;
e05b3b4a	177
e2eb6392	178	class_code = of_get_property(node, "class-code", NULL);
e05b3b4a PM	179	if (!class_code \|\| ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
	180	(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
	181	continue;
e2eb6392	182	reg = of_get_property(node, "reg", NULL);
e05b3b4a PM	183	if (!reg)
e05b3b4a PM	184	continue;
ab462768 AC	185	dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
	186	if (!dev \|\| !dev->subordinate) {
	187	pci_dev_put(dev);
e05b3b4a	188	continue;
ab462768	189	}
e05b3b4a	190	make_one_node_map(node, dev->subordinate->number);
ab462768	191	pci_dev_put(dev);
e05b3b4a PM	192	}
	193	}
	194
	195	void
	196	pcibios_make_OF_bus_map(void)
	197	{
	198	int i;
a4c9e328	199	struct pci_controller hose, tmp;
a7f67bdf	200	struct property *map_prop;
8c8dc322	201	struct device_node *dn;
e05b3b4a	202
5cbded58	203	pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
e05b3b4a PM	204	if (!pci_to_OF_bus_map) {
	205	printk(KERN_ERR "Can't allocate OF bus map !\n");
	206	return;
	207	}
	208
	209	/* We fill the bus map with invalid values, that helps
	210	* debugging.
	211	*/
	212	for (i=0; i<pci_bus_count; i++)
	213	pci_to_OF_bus_map[i] = 0xff;
	214
	215	/* For each hose, we begin searching bridges */
a4c9e328	216	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
44ef3390 SR	217	struct device_node* node = hose->dn;
44ef3390 SR	218
e05b3b4a PM	219	if (!node)
	220	continue;
	221	make_one_node_map(node, hose->first_busno);
	222	}
8c8dc322 SR	223	dn = of_find_node_by_path("/");
8c8dc322 SR	224	map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
a7f67bdf JK	225	if (map_prop) {
	226	BUG_ON(pci_bus_count > map_prop->length);
	227	memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
	228	}
8c8dc322	229	of_node_put(dn);
e05b3b4a PM	230	#ifdef DEBUG
	231	printk("PCI->OF bus map:\n");
	232	for (i=0; i<pci_bus_count; i++) {
	233	if (pci_to_OF_bus_map[i] == 0xff)
	234	continue;
	235	printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
	236	}
	237	#endif
	238	}
	239
	240	typedef int (pci_OF_scan_iterator)(struct device_node node, void* data);
	241
	242	static struct device_node*
	243	scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
	244	{
	245	struct device_node* sub_node;
	246
	247	for (; node != 0;node = node->sibling) {
a7f67bdf	248	const unsigned int *class_code;
e05b3b4a PM	249
	250	if (filter(node, data))
	251	return node;
	252
	253	/* For PCI<->PCI bridges or CardBus bridges, we go down
	254	* Note: some OFs create a parent node "multifunc-device" as
	255	* a fake root for all functions of a multi-function device,
	256	* we go down them as well.
	257	*/
e2eb6392	258	class_code = of_get_property(node, "class-code", NULL);
e05b3b4a PM	259	if ((!class_code \|\| ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
	260	(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
	261	strcmp(node->name, "multifunc-device"))
	262	continue;
	263	sub_node = scan_OF_pci_childs(node->child, filter, data);
	264	if (sub_node)
	265	return sub_node;
	266	}
	267	return NULL;
	268	}
	269
dae4828d BH	270	static struct device_node scan_OF_for_pci_dev(struct device_node parent,
dae4828d BH	271	unsigned int devfn)
e05b3b4a	272	{
dae4828d BH	273	struct device_node *np = NULL;
	274	const u32 *reg;
	275	unsigned int psize;
	276
	277	while ((np = of_get_next_child(parent, np)) != NULL) {
e2eb6392	278	reg = of_get_property(np, "reg", &psize);
dae4828d BH	279	if (reg == NULL \|\| psize < 4)
	280	continue;
	281	if (((reg[0] >> 8) & 0xff) == devfn)
	282	return np;
	283	}
	284	return NULL;
e05b3b4a PM	285	}
e05b3b4a PM	286
dae4828d BH	287
dae4828d BH	288	static struct device_node scan_OF_for_pci_bus(struct pci_bus bus)
e05b3b4a	289	{
dae4828d BH	290	struct device_node parent, np;
	291
	292	/* Are we a root bus ? */
	293	if (bus->self == NULL \|\| bus->parent == NULL) {
0b1d40c4	294	struct pci_controller *hose = pci_bus_to_host(bus);
dae4828d BH	295	if (hose == NULL)
dae4828d BH	296	return NULL;
44ef3390	297	return of_node_get(hose->dn);
dae4828d BH	298	}
	299
	300	/* not a root bus, we need to get our parent */
	301	parent = scan_OF_for_pci_bus(bus->parent);
	302	if (parent == NULL)
	303	return NULL;
	304
	305	/* now iterate for children for a match */
	306	np = scan_OF_for_pci_dev(parent, bus->self->devfn);
	307	of_node_put(parent);
	308
dae4828d	309	return np;
e05b3b4a PM	310	}
	311
	312	/*
	313	* Scans the OF tree for a device node matching a PCI device
	314	*/
	315	struct device_node *
	316	pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
	317	{
dae4828d	318	struct device_node parent, np;
e05b3b4a PM	319
	320	if (!have_of)
	321	return NULL;
e05b3b4a	322
dae4828d BH	323	DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
	324	parent = scan_OF_for_pci_bus(bus);
	325	if (parent == NULL)
e05b3b4a	326	return NULL;
dae4828d BH	327	DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
	328	np = scan_OF_for_pci_dev(parent, devfn);
	329	of_node_put(parent);
	330	DBG(" result is %s\n", np ? np->full_name : "<NULL>");
	331
	332	/* XXX most callers don't release the returned node
	333	* mostly because ppc64 doesn't increase the refcount,
	334	* we need to fix that.
e05b3b4a	335	*/
dae4828d	336	return np;
e05b3b4a PM	337	}
	338	EXPORT_SYMBOL(pci_busdev_to_OF_node);
	339
	340	struct device_node*
	341	pci_device_to_OF_node(struct pci_dev *dev)
	342	{
	343	return pci_busdev_to_OF_node(dev->bus, dev->devfn);
	344	}
	345	EXPORT_SYMBOL(pci_device_to_OF_node);
	346
e05b3b4a PM	347	static int
	348	find_OF_pci_device_filter(struct device_node* node, void* data)
	349	{
	350	return ((void *)node == data);
	351	}
	352
	353	/*
	354	* Returns the PCI device matching a given OF node
	355	*/
	356	int
	357	pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
	358	{
a7f67bdf	359	const unsigned int *reg;
e05b3b4a PM	360	struct pci_controller* hose;
	361	struct pci_dev* dev = NULL;
	362
	363	if (!have_of)
	364	return -ENODEV;
	365	/* Make sure it's really a PCI device */
	366	hose = pci_find_hose_for_OF_device(node);
44ef3390	367	if (!hose \|\| !hose->dn)
e05b3b4a	368	return -ENODEV;
44ef3390	369	if (!scan_OF_pci_childs(hose->dn->child,
e05b3b4a PM	370	find_OF_pci_device_filter, (void *)node))
e05b3b4a PM	371	return -ENODEV;
e2eb6392	372	reg = of_get_property(node, "reg", NULL);
e05b3b4a PM	373	if (!reg)
	374	return -ENODEV;
	375	*bus = (reg[0] >> 16) & 0xff;
	376	*devfn = ((reg[0] >> 8) & 0xff);
	377
	378	/* Ok, here we need some tweak. If we have already renumbered
	379	* all busses, we can't rely on the OF bus number any more.
	380	* the pci_to_OF_bus_map is not enough as several PCI busses
	381	* may match the same OF bus number.
	382	*/
	383	if (!pci_to_OF_bus_map)
	384	return 0;
	385
	386	for_each_pci_dev(dev)
	387	if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
	388	dev->devfn == *devfn) {
	389	*bus = dev->bus->number;
	390	pci_dev_put(dev);
	391	return 0;
	392	}
	393
	394	return -ENODEV;
	395	}
	396	EXPORT_SYMBOL(pci_device_from_OF_node);
	397
e05b3b4a PM	398	/* We create the "pci-OF-bus-map" property now so it appears in the
	399	* /proc device tree
	400	*/
	401	void __init
	402	pci_create_OF_bus_map(void)
	403	{
	404	struct property* of_prop;
8c8dc322 SR	405	struct device_node *dn;
8c8dc322 SR	406
e05b3b4a	407	of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
8c8dc322 SR	408	if (!of_prop)
	409	return;
	410	dn = of_find_node_by_path("/");
	411	if (dn) {
e05b3b4a PM	412	memset(of_prop, -1, sizeof(struct property) + 256);
	413	of_prop->name = "pci-OF-bus-map";
	414	of_prop->length = 256;
1a38147e	415	of_prop->value = &of_prop[1];
8c8dc322 SR	416	prom_add_property(dn, of_prop);
8c8dc322 SR	417	of_node_put(dn);
e05b3b4a PM	418	}
	419	}
	420
e05b3b4a PM	421	#else /* CONFIG_PPC_OF */
	422	void pcibios_make_OF_bus_map(void)
	423	{
	424	}
	425	#endif /* CONFIG_PPC_OF */
	426
3fd94c6b	427	static int __init pcibios_init(void)
e05b3b4a	428	{
a4c9e328	429	struct pci_controller hose, tmp;
e05b3b4a	430	struct pci_bus *bus;
a4c9e328	431	int next_busno = 0;
e05b3b4a PM	432
	433	printk(KERN_INFO "PCI: Probing PCI hardware\n");
	434
fc3fb71c BH	435	if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_BUS)
	436	pci_assign_all_buses = 1;
	437
e05b3b4a	438	/* Scan all of the recorded PCI controllers. */
a4c9e328	439	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
e05b3b4a PM	440	if (pci_assign_all_buses)
	441	hose->first_busno = next_busno;
	442	hose->last_busno = 0xff;
803d4573 BH	443	bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
803d4573 BH	444	hose->ops, hose);
b1b166b7	445	if (bus) {
803d4573	446	pci_bus_add_devices(bus);
b1b166b7 BH	447	hose->last_busno = bus->subordinate;
b1b166b7 BH	448	}
e05b3b4a PM	449	if (pci_assign_all_buses \|\| next_busno <= hose->last_busno)
	450	next_busno = hose->last_busno + pcibios_assign_bus_offset;
	451	}
	452	pci_bus_count = next_busno;
	453
	454	/* OpenFirmware based machines need a map of OF bus
	455	* numbers vs. kernel bus numbers since we may have to
	456	* remap them.
	457	*/
	458	if (pci_assign_all_buses && have_of)
	459	pcibios_make_OF_bus_map();
	460
3fd94c6b BH	461	/* Call common code to handle resource allocation */
3fd94c6b BH	462	pcibios_resource_survey();
e05b3b4a PM	463
	464	/* Call machine dependent post-init code */
	465	if (ppc_md.pcibios_after_init)
	466	ppc_md.pcibios_after_init();
	467
	468	return 0;
	469	}
	470
	471	subsys_initcall(pcibios_init);
	472
bf5e2ba2	473	void __devinit pcibios_do_bus_setup(struct pci_bus *bus)
e05b3b4a PM	474	{
	475	struct pci_controller hose = (struct pci_controller ) bus->sysdata;
	476	unsigned long io_offset;
	477	struct resource *res;
	478	int i;
	479
bf5e2ba2	480	/* Hookup PHB resources */
e05b3b4a PM	481	io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
	482	if (bus->parent == NULL) {
	483	/* This is a host bridge - fill in its resources */
	484	hose->bus = bus;
	485
	486	bus->resource[0] = res = &hose->io_resource;
	487	if (!res->flags) {
	488	if (io_offset)
	489	printk(KERN_ERR "I/O resource not set for host"
5516b540	490	" bridge %d\n", hose->global_number);
e05b3b4a PM	491	res->start = 0;
	492	res->end = IO_SPACE_LIMIT;
	493	res->flags = IORESOURCE_IO;
	494	}
05d3957e BH	495	res->start = (res->start + io_offset) & 0xffffffffu;
05d3957e BH	496	res->end = (res->end + io_offset) & 0xffffffffu;
e05b3b4a PM	497
	498	for (i = 0; i < 3; ++i) {
	499	res = &hose->mem_resources[i];
	500	if (!res->flags) {
	501	if (i > 0)
	502	continue;
	503	printk(KERN_ERR "Memory resource not set for "
5516b540	504	"host bridge %d\n", hose->global_number);
e05b3b4a PM	505	res->start = hose->pci_mem_offset;
	506	res->end = ~0U;
	507	res->flags = IORESOURCE_MEM;
	508	}
	509	bus->resource[i+1] = res;
	510	}
f90bb153	511	}
e05b3b4a PM	512	}
e05b3b4a PM	513
e05b3b4a PM	514	/* the next one is stolen from the alpha port... */
	515	void __init
	516	pcibios_update_irq(struct pci_dev *dev, int irq)
	517	{
	518	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	519	/* XXX FIXME - update OF device tree node interrupt property */
	520	}
	521
0b1d40c4	522	static struct pci_controller*
e05b3b4a PM	523	pci_bus_to_hose(int bus)
e05b3b4a PM	524	{
a4c9e328	525	struct pci_controller hose, tmp;
e05b3b4a	526
a4c9e328	527	list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
e05b3b4a PM	528	if (bus >= hose->first_busno && bus <= hose->last_busno)
	529	return hose;
	530	return NULL;
	531	}
	532
e05b3b4a PM	533	/* Provide information on locations of various I/O regions in physical
	534	* memory. Do this on a per-card basis so that we choose the right
	535	* root bridge.
	536	* Note that the returned IO or memory base is a physical address
	537	*/
	538
	539	long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
	540	{
	541	struct pci_controller* hose;
	542	long result = -EOPNOTSUPP;
	543
e05b3b4a PM	544	hose = pci_bus_to_hose(bus);
	545	if (!hose)
	546	return -ENODEV;
	547
	548	switch (which) {
	549	case IOBASE_BRIDGE_NUMBER:
	550	return (long)hose->first_busno;
	551	case IOBASE_MEMORY:
	552	return (long)hose->pci_mem_offset;
	553	case IOBASE_IO:
	554	return (long)hose->io_base_phys;
	555	case IOBASE_ISA_IO:
	556	return (long)isa_io_base;
	557	case IOBASE_ISA_MEM:
	558	return (long)isa_mem_base;
	559	}
	560
	561	return result;
	562	}
	563
e05b3b4a PM	564	unsigned long pci_address_to_pio(phys_addr_t address)
e05b3b4a PM	565	{
a4c9e328	566	struct pci_controller hose, tmp;
e05b3b4a	567
a4c9e328	568	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
e05b3b4a PM	569	unsigned int size = hose->io_resource.end -
	570	hose->io_resource.start + 1;
	571	if (address >= hose->io_base_phys &&
	572	address < (hose->io_base_phys + size)) {
	573	unsigned long base =
	574	(unsigned long)hose->io_base_virt - _IO_BASE;
	575	return base + (address - hose->io_base_phys);
	576	}
	577	}
	578	return (unsigned int)-1;
	579	}
	580	EXPORT_SYMBOL(pci_address_to_pio);
	581
	582	/*
	583	* Null PCI config access functions, for the case when we can't
	584	* find a hose.
	585	*/
	586	#define NULL_PCI_OP(rw, size, type) \
	587	static int \
	588	null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
	589	{ \
	590	return PCIBIOS_DEVICE_NOT_FOUND; \
	591	}
	592
	593	static int
	594	null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
	595	int len, u32 *val)
	596	{
	597	return PCIBIOS_DEVICE_NOT_FOUND;
	598	}
	599
	600	static int
	601	null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
	602	int len, u32 val)
	603	{
	604	return PCIBIOS_DEVICE_NOT_FOUND;
	605	}
	606
	607	static struct pci_ops null_pci_ops =
	608	{
6127d1c0 NL	609	.read = null_read_config,
6127d1c0 NL	610	.write = null_write_config,
e05b3b4a PM	611	};
	612
	613	/*
	614	* These functions are used early on before PCI scanning is done
	615	* and all of the pci_dev and pci_bus structures have been created.
	616	*/
	617	static struct pci_bus *
	618	fake_pci_bus(struct pci_controller *hose, int busnr)
	619	{
	620	static struct pci_bus bus;
	621
	622	if (hose == 0) {
	623	hose = pci_bus_to_hose(busnr);
	624	if (hose == 0)
	625	printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
	626	}
	627	bus.number = busnr;
	628	bus.sysdata = hose;
	629	bus.ops = hose? hose->ops: &null_pci_ops;
	630	return &bus;
	631	}
	632
	633	#define EARLY_PCI_OP(rw, size, type) \
	634	int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
	635	int devfn, int offset, type value) \
	636	{ \
	637	return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
	638	devfn, offset, value); \
	639	}
	640
	641	EARLY_PCI_OP(read, byte, u8 *)
	642	EARLY_PCI_OP(read, word, u16 *)
	643	EARLY_PCI_OP(read, dword, u32 *)
	644	EARLY_PCI_OP(write, byte, u8)
	645	EARLY_PCI_OP(write, word, u16)
	646	EARLY_PCI_OP(write, dword, u32)
38805e5f KG	647
	648	extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
	649	int early_find_capability(struct pci_controller *hose, int bus, int devfn,
	650	int cap)
	651	{
	652	return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
	653	}