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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / powerpc / kernel / ptrace.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
b123923d 11 * and Paul Mackerras (paulus@samba.org).
1da177e4
LT		 12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
1da177e4
LT		 22#include <linux/errno.h>
23#include <linux/ptrace.h>
f65255e8 24#include <linux/regset.h>
4f72c427 25#include <linux/tracehook.h>
3caf06c6 26#include <linux/elf.h>
1da177e4
LT		 27#include <linux/user.h>
28#include <linux/security.h>
7ed20e1a 29#include <linux/signal.h>
ea9c102c
DW		 30#include <linux/seccomp.h>
31#include <linux/audit.h>
02424d89 32#include <trace/syscall.h>
5aae8a53
P		 33#include <linux/hw_breakpoint.h>
34#include <linux/perf_event.h>
1da177e4
LT		 35
36#include <asm/uaccess.h>
37#include <asm/page.h>
38#include <asm/pgtable.h>
ae3a197e 39#include <asm/switch_to.h>
21a62902 40
02424d89
IM		 41#define CREATE_TRACE_POINTS
42#include <trace/events/syscalls.h>
43
359e4284
MS		 44/*
45 * The parameter save area on the stack is used to store arguments being passed
46 * to callee function and is located at fixed offset from stack pointer.
47 */
48#ifdef CONFIG_PPC32
49#define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
50#else /* CONFIG_PPC32 */
51#define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
52#endif
53
54struct pt_regs_offset {
55 const char *name;
56 int offset;
57};
58
59#define STR(s) #s /* convert to string */
60#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
61#define GPR_OFFSET_NAME(num) \
62 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
63#define REG_OFFSET_END {.name = NULL, .offset = 0}
64
65static const struct pt_regs_offset regoffset_table[] = {
66 GPR_OFFSET_NAME(0),
67 GPR_OFFSET_NAME(1),
68 GPR_OFFSET_NAME(2),
69 GPR_OFFSET_NAME(3),
70 GPR_OFFSET_NAME(4),
71 GPR_OFFSET_NAME(5),
72 GPR_OFFSET_NAME(6),
73 GPR_OFFSET_NAME(7),
74 GPR_OFFSET_NAME(8),
75 GPR_OFFSET_NAME(9),
76 GPR_OFFSET_NAME(10),
77 GPR_OFFSET_NAME(11),
78 GPR_OFFSET_NAME(12),
79 GPR_OFFSET_NAME(13),
80 GPR_OFFSET_NAME(14),
81 GPR_OFFSET_NAME(15),
82 GPR_OFFSET_NAME(16),
83 GPR_OFFSET_NAME(17),
84 GPR_OFFSET_NAME(18),
85 GPR_OFFSET_NAME(19),
86 GPR_OFFSET_NAME(20),
87 GPR_OFFSET_NAME(21),
88 GPR_OFFSET_NAME(22),
89 GPR_OFFSET_NAME(23),
90 GPR_OFFSET_NAME(24),
91 GPR_OFFSET_NAME(25),
92 GPR_OFFSET_NAME(26),
93 GPR_OFFSET_NAME(27),
94 GPR_OFFSET_NAME(28),
95 GPR_OFFSET_NAME(29),
96 GPR_OFFSET_NAME(30),
97 GPR_OFFSET_NAME(31),
98 REG_OFFSET_NAME(nip),
99 REG_OFFSET_NAME(msr),
100 REG_OFFSET_NAME(ctr),
101 REG_OFFSET_NAME(link),
102 REG_OFFSET_NAME(xer),
103 REG_OFFSET_NAME(ccr),
104#ifdef CONFIG_PPC64
105 REG_OFFSET_NAME(softe),
106#else
107 REG_OFFSET_NAME(mq),
108#endif
109 REG_OFFSET_NAME(trap),
110 REG_OFFSET_NAME(dar),
111 REG_OFFSET_NAME(dsisr),
112 REG_OFFSET_END,
113};
114
115/**
116 * regs_query_register_offset() - query register offset from its name
117 * @name: the name of a register
118 *
119 * regs_query_register_offset() returns the offset of a register in struct
120 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
121 */
122int regs_query_register_offset(const char *name)
123{
124 const struct pt_regs_offset *roff;
125 for (roff = regoffset_table; roff->name != NULL; roff++)
126 if (!strcmp(roff->name, name))
127 return roff->offset;
128 return -EINVAL;
129}
130
131/**
132 * regs_query_register_name() - query register name from its offset
133 * @offset: the offset of a register in struct pt_regs.
134 *
135 * regs_query_register_name() returns the name of a register from its
136 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
137 */
138const char *regs_query_register_name(unsigned int offset)
139{
140 const struct pt_regs_offset *roff;
141 for (roff = regoffset_table; roff->name != NULL; roff++)
142 if (roff->offset == offset)
143 return roff->name;
144 return NULL;
145}
146
abd06505
BH		 147/*
148 * does not yet catch signals sent when the child dies.
149 * in exit.c or in signal.c.
150 */
151
152/*
153 * Set of msr bits that gdb can change on behalf of a process.
154 */
172ae2e7 155#ifdef CONFIG_PPC_ADV_DEBUG_REGS
abd06505 156#define MSR_DEBUGCHANGE 0
1da177e4 157#else
abd06505 158#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
1da177e4 159#endif
acd89828 160
1da177e4 161/*
abd06505 162 * Max register writeable via put_reg
1da177e4 163 */
abd06505
BH		 164#ifdef CONFIG_PPC32
165#define PT_MAX_PUT_REG PT_MQ
166#else
167#define PT_MAX_PUT_REG PT_CCR
168#endif
1da177e4 169
26f77130
RM		 170static unsigned long get_user_msr(struct task_struct *task)
171{
172 return task->thread.regs->msr | task->thread.fpexc_mode;
173}
174
175static int set_user_msr(struct task_struct *task, unsigned long msr)
176{
177 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
178 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
179 return 0;
180}
181
182/*
183 * We prevent mucking around with the reserved area of trap
184 * which are used internally by the kernel.
185 */
186static int set_user_trap(struct task_struct *task, unsigned long trap)
187{
188 task->thread.regs->trap = trap & 0xfff0;
189 return 0;
190}
191
865418d8
BH		 192/*
193 * Get contents of register REGNO in task TASK.
194 */
195unsigned long ptrace_get_reg(struct task_struct *task, int regno)
196{
865418d8
BH		 197 if (task->thread.regs == NULL)
198 return -EIO;
199
26f77130
RM		 200 if (regno == PT_MSR)
201 return get_user_msr(task);
865418d8
BH		 202
203 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
204 return ((unsigned long *)task->thread.regs)[regno];
205
206 return -EIO;
207}
208
209/*
210 * Write contents of register REGNO in task TASK.
211 */
212int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
213{
214 if (task->thread.regs == NULL)
215 return -EIO;
216
26f77130
RM		 217 if (regno == PT_MSR)
218 return set_user_msr(task, data);
219 if (regno == PT_TRAP)
220 return set_user_trap(task, data);
221
222 if (regno <= PT_MAX_PUT_REG) {
865418d8
BH		 223 ((unsigned long *)task->thread.regs)[regno] = data;
224 return 0;
225 }
226 return -EIO;
227}
228
44dd3f50
RM		 229static int gpr_get(struct task_struct *target, const struct user_regset *regset,
230 unsigned int pos, unsigned int count,
231 void *kbuf, void __user *ubuf)
232{
a71f5d5d 233 int i, ret;
44dd3f50
RM		 234
235 if (target->thread.regs == NULL)
236 return -EIO;
237
a71f5d5d
MW		 238 if (!FULL_REGS(target->thread.regs)) {
239 /* We have a partial register set. Fill 14-31 with bogus values */
240 for (i = 14; i < 32; i++)
241 target->thread.regs->gpr[i] = NV_REG_POISON;
242 }
44dd3f50
RM		 243
244 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
245 target->thread.regs,
246 0, offsetof(struct pt_regs, msr));
247 if (!ret) {
248 unsigned long msr = get_user_msr(target);
249 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
250 offsetof(struct pt_regs, msr),
251 offsetof(struct pt_regs, msr) +
252 sizeof(msr));
253 }
254
255 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
256 offsetof(struct pt_regs, msr) + sizeof(long));
257
258 if (!ret)
259 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
260 &target->thread.regs->orig_gpr3,
261 offsetof(struct pt_regs, orig_gpr3),
262 sizeof(struct pt_regs));
263 if (!ret)
264 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
265 sizeof(struct pt_regs), -1);
266
267 return ret;
268}
269
270static int gpr_set(struct task_struct *target, const struct user_regset *regset,
271 unsigned int pos, unsigned int count,
272 const void *kbuf, const void __user *ubuf)
273{
274 unsigned long reg;
275 int ret;
276
277 if (target->thread.regs == NULL)
278 return -EIO;
279
280 CHECK_FULL_REGS(target->thread.regs);
281
282 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
283 target->thread.regs,
284 0, PT_MSR * sizeof(reg));
285
286 if (!ret && count > 0) {
287 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
288 PT_MSR * sizeof(reg),
289 (PT_MSR + 1) * sizeof(reg));
290 if (!ret)
291 ret = set_user_msr(target, reg);
292 }
293
294 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
295 offsetof(struct pt_regs, msr) + sizeof(long));
296
297 if (!ret)
298 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
299 &target->thread.regs->orig_gpr3,
300 PT_ORIG_R3 * sizeof(reg),
301 (PT_MAX_PUT_REG + 1) * sizeof(reg));
302
303 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
304 ret = user_regset_copyin_ignore(
305 &pos, &count, &kbuf, &ubuf,
306 (PT_MAX_PUT_REG + 1) * sizeof(reg),
307 PT_TRAP * sizeof(reg));
308
309 if (!ret && count > 0) {
310 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
311 PT_TRAP * sizeof(reg),
312 (PT_TRAP + 1) * sizeof(reg));
313 if (!ret)
314 ret = set_user_trap(target, reg);
315 }
316
317 if (!ret)
318 ret = user_regset_copyin_ignore(
319 &pos, &count, &kbuf, &ubuf,
320 (PT_TRAP + 1) * sizeof(reg), -1);
321
322 return ret;
323}
865418d8 324
f65255e8
RM		 325static int fpr_get(struct task_struct *target, const struct user_regset *regset,
326 unsigned int pos, unsigned int count,
327 void *kbuf, void __user *ubuf)
328{
c6e6771b
MN		 329#ifdef CONFIG_VSX
330 double buf[33];
331 int i;
332#endif
f65255e8
RM		 333 flush_fp_to_thread(target);
334
c6e6771b
MN		 335#ifdef CONFIG_VSX
336 /* copy to local buffer then write that out */
337 for (i = 0; i < 32 ; i++)
338 buf[i] = target->thread.TS_FPR(i);
339 memcpy(&buf[32], &target->thread.fpscr, sizeof(double));
340 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
341
342#else
f65255e8 343 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
9c75a31c 344 offsetof(struct thread_struct, TS_FPR(32)));
f65255e8
RM		 345
346 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
347 &target->thread.fpr, 0, -1);
c6e6771b 348#endif
f65255e8
RM		 349}
350
351static int fpr_set(struct task_struct *target, const struct user_regset *regset,
352 unsigned int pos, unsigned int count,
353 const void *kbuf, const void __user *ubuf)
354{
c6e6771b
MN		 355#ifdef CONFIG_VSX
356 double buf[33];
357 int i;
358#endif
f65255e8
RM		 359 flush_fp_to_thread(target);
360
c6e6771b
MN		 361#ifdef CONFIG_VSX
362 /* copy to local buffer then write that out */
363 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
364 if (i)
365 return i;
366 for (i = 0; i < 32 ; i++)
367 target->thread.TS_FPR(i) = buf[i];
368 memcpy(&target->thread.fpscr, &buf[32], sizeof(double));
369 return 0;
370#else
f65255e8 371 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
9c75a31c 372 offsetof(struct thread_struct, TS_FPR(32)));
f65255e8
RM		 373
374 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
375 &target->thread.fpr, 0, -1);
c6e6771b 376#endif
f65255e8
RM		 377}
378
865418d8
BH		 379#ifdef CONFIG_ALTIVEC
380/*
381 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
382 * The transfer totals 34 quadword. Quadwords 0-31 contain the
383 * corresponding vector registers. Quadword 32 contains the vscr as the
384 * last word (offset 12) within that quadword. Quadword 33 contains the
385 * vrsave as the first word (offset 0) within the quadword.
386 *
387 * This definition of the VMX state is compatible with the current PPC32
388 * ptrace interface. This allows signal handling and ptrace to use the
389 * same structures. This also simplifies the implementation of a bi-arch
390 * (combined (32- and 64-bit) gdb.
391 */
392
3caf06c6
RM		 393static int vr_active(struct task_struct *target,
394 const struct user_regset *regset)
395{
396 flush_altivec_to_thread(target);
397 return target->thread.used_vr ? regset->n : 0;
398}
399
400static int vr_get(struct task_struct *target, const struct user_regset *regset,
401 unsigned int pos, unsigned int count,
402 void *kbuf, void __user *ubuf)
403{
404 int ret;
405
406 flush_altivec_to_thread(target);
407
408 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
409 offsetof(struct thread_struct, vr[32]));
410
411 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
412 &target->thread.vr, 0,
413 33 * sizeof(vector128));
414 if (!ret) {
415 /*
416 * Copy out only the low-order word of vrsave.
417 */
418 union {
419 elf_vrreg_t reg;
420 u32 word;
421 } vrsave;
422 memset(&vrsave, 0, sizeof(vrsave));
423 vrsave.word = target->thread.vrsave;
424 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
425 33 * sizeof(vector128), -1);
426 }
427
428 return ret;
429}
430
431static int vr_set(struct task_struct *target, const struct user_regset *regset,
432 unsigned int pos, unsigned int count,
433 const void *kbuf, const void __user *ubuf)
434{
435 int ret;
436
437 flush_altivec_to_thread(target);
438
439 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
440 offsetof(struct thread_struct, vr[32]));
441
442 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
443 &target->thread.vr, 0, 33 * sizeof(vector128));
444 if (!ret && count > 0) {
445 /*
446 * We use only the first word of vrsave.
447 */
448 union {
449 elf_vrreg_t reg;
450 u32 word;
451 } vrsave;
452 memset(&vrsave, 0, sizeof(vrsave));
453 vrsave.word = target->thread.vrsave;
454 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
455 33 * sizeof(vector128), -1);
456 if (!ret)
457 target->thread.vrsave = vrsave.word;
458 }
459
460 return ret;
461}
865418d8
BH		 462#endif /* CONFIG_ALTIVEC */
463
ce48b210
MN		 464#ifdef CONFIG_VSX
465/*
466 * Currently to set and and get all the vsx state, you need to call
25985edc 467 * the fp and VMX calls as well. This only get/sets the lower 32
ce48b210
MN		 468 * 128bit VSX registers.
469 */
470
471static int vsr_active(struct task_struct *target,
472 const struct user_regset *regset)
473{
474 flush_vsx_to_thread(target);
475 return target->thread.used_vsr ? regset->n : 0;
476}
477
478static int vsr_get(struct task_struct *target, const struct user_regset *regset,
479 unsigned int pos, unsigned int count,
480 void *kbuf, void __user *ubuf)
481{
f3e909c2
MN		 482 double buf[32];
483 int ret, i;
ce48b210
MN		 484
485 flush_vsx_to_thread(target);
486
f3e909c2 487 for (i = 0; i < 32 ; i++)
7d2a175b 488 buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET];
ce48b210 489 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
f3e909c2 490 buf, 0, 32 * sizeof(double));
ce48b210
MN		 491
492 return ret;
493}
494
495static int vsr_set(struct task_struct *target, const struct user_regset *regset,
496 unsigned int pos, unsigned int count,
497 const void *kbuf, const void __user *ubuf)
498{
f3e909c2
MN		 499 double buf[32];
500 int ret,i;
ce48b210
MN		 501
502 flush_vsx_to_thread(target);
503
504 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
f3e909c2
MN		 505 buf, 0, 32 * sizeof(double));
506 for (i = 0; i < 32 ; i++)
7d2a175b 507 target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
f3e909c2 508
ce48b210
MN		 509
510 return ret;
511}
512#endif /* CONFIG_VSX */
513
865418d8
BH		 514#ifdef CONFIG_SPE
515
516/*
517 * For get_evrregs/set_evrregs functions 'data' has the following layout:
518 *
519 * struct {
520 * u32 evr[32];
521 * u64 acc;
522 * u32 spefscr;
523 * }
524 */
525
a4e4b175
RM		 526static int evr_active(struct task_struct *target,
527 const struct user_regset *regset)
865418d8 528{
a4e4b175
RM		 529 flush_spe_to_thread(target);
530 return target->thread.used_spe ? regset->n : 0;
531}
865418d8 532
a4e4b175
RM		 533static int evr_get(struct task_struct *target, const struct user_regset *regset,
534 unsigned int pos, unsigned int count,
535 void *kbuf, void __user *ubuf)
536{
537 int ret;
865418d8 538
a4e4b175 539 flush_spe_to_thread(target);
865418d8 540
a4e4b175
RM		 541 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
542 &target->thread.evr,
543 0, sizeof(target->thread.evr));
865418d8 544
a4e4b175
RM		 545 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
546 offsetof(struct thread_struct, spefscr));
547
548 if (!ret)
549 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
550 &target->thread.acc,
551 sizeof(target->thread.evr), -1);
552
553 return ret;
554}
555
556static int evr_set(struct task_struct *target, const struct user_regset *regset,
557 unsigned int pos, unsigned int count,
558 const void *kbuf, const void __user *ubuf)
559{
560 int ret;
561
562 flush_spe_to_thread(target);
563
564 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
565 &target->thread.evr,
566 0, sizeof(target->thread.evr));
865418d8 567
a4e4b175
RM		 568 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
569 offsetof(struct thread_struct, spefscr));
570
571 if (!ret)
572 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
573 &target->thread.acc,
574 sizeof(target->thread.evr), -1);
575
576 return ret;
865418d8 577}
865418d8
BH		 578#endif /* CONFIG_SPE */
579
580
80fdf470
RM		 581/*
582 * These are our native regset flavors.
583 */
584enum powerpc_regset {
585 REGSET_GPR,
586 REGSET_FPR,
587#ifdef CONFIG_ALTIVEC
588 REGSET_VMX,
589#endif
ce48b210
MN		 590#ifdef CONFIG_VSX
591 REGSET_VSX,
592#endif
80fdf470
RM		 593#ifdef CONFIG_SPE
594 REGSET_SPE,
595#endif
596};
597
598static const struct user_regset native_regsets[] = {
599 [REGSET_GPR] = {
600 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
601 .size = sizeof(long), .align = sizeof(long),
602 .get = gpr_get, .set = gpr_set
603 },
604 [REGSET_FPR] = {
605 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
606 .size = sizeof(double), .align = sizeof(double),
607 .get = fpr_get, .set = fpr_set
608 },
609#ifdef CONFIG_ALTIVEC
610 [REGSET_VMX] = {
611 .core_note_type = NT_PPC_VMX, .n = 34,
612 .size = sizeof(vector128), .align = sizeof(vector128),
613 .active = vr_active, .get = vr_get, .set = vr_set
614 },
615#endif
ce48b210
MN		 616#ifdef CONFIG_VSX
617 [REGSET_VSX] = {
f3e909c2
MN		 618 .core_note_type = NT_PPC_VSX, .n = 32,
619 .size = sizeof(double), .align = sizeof(double),
ce48b210
MN		 620 .active = vsr_active, .get = vsr_get, .set = vsr_set
621 },
622#endif
80fdf470
RM		 623#ifdef CONFIG_SPE
624 [REGSET_SPE] = {
625 .n = 35,
626 .size = sizeof(u32), .align = sizeof(u32),
627 .active = evr_active, .get = evr_get, .set = evr_set
628 },
629#endif
630};
631
632static const struct user_regset_view user_ppc_native_view = {
633 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
634 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
635};
636
fa8f5cb0
RM		 637#ifdef CONFIG_PPC64
638#include <linux/compat.h>
639
640static int gpr32_get(struct task_struct *target,
641 const struct user_regset *regset,
642 unsigned int pos, unsigned int count,
643 void *kbuf, void __user *ubuf)
644{
645 const unsigned long *regs = &target->thread.regs->gpr[0];
646 compat_ulong_t *k = kbuf;
647 compat_ulong_t __user *u = ubuf;
648 compat_ulong_t reg;
a71f5d5d 649 int i;
fa8f5cb0
RM		 650
651 if (target->thread.regs == NULL)
652 return -EIO;
653
a71f5d5d
MW		 654 if (!FULL_REGS(target->thread.regs)) {
655 /* We have a partial register set. Fill 14-31 with bogus values */
656 for (i = 14; i < 32; i++)
657 target->thread.regs->gpr[i] = NV_REG_POISON;
658 }
fa8f5cb0
RM		 659
660 pos /= sizeof(reg);
661 count /= sizeof(reg);
662
663 if (kbuf)
664 for (; count > 0 && pos < PT_MSR; --count)
665 *k++ = regs[pos++];
666 else
667 for (; count > 0 && pos < PT_MSR; --count)
668 if (__put_user((compat_ulong_t) regs[pos++], u++))
669 return -EFAULT;
670
671 if (count > 0 && pos == PT_MSR) {
672 reg = get_user_msr(target);
673 if (kbuf)
674 *k++ = reg;
675 else if (__put_user(reg, u++))
676 return -EFAULT;
677 ++pos;
678 --count;
679 }
680
681 if (kbuf)
682 for (; count > 0 && pos < PT_REGS_COUNT; --count)
683 *k++ = regs[pos++];
684 else
685 for (; count > 0 && pos < PT_REGS_COUNT; --count)
686 if (__put_user((compat_ulong_t) regs[pos++], u++))
687 return -EFAULT;
688
689 kbuf = k;
690 ubuf = u;
691 pos *= sizeof(reg);
692 count *= sizeof(reg);
693 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
694 PT_REGS_COUNT * sizeof(reg), -1);
695}
696
697static int gpr32_set(struct task_struct *target,
698 const struct user_regset *regset,
699 unsigned int pos, unsigned int count,
700 const void *kbuf, const void __user *ubuf)
701{
702 unsigned long *regs = &target->thread.regs->gpr[0];
703 const compat_ulong_t *k = kbuf;
704 const compat_ulong_t __user *u = ubuf;
705 compat_ulong_t reg;
706
707 if (target->thread.regs == NULL)
708 return -EIO;
709
710 CHECK_FULL_REGS(target->thread.regs);
711
712 pos /= sizeof(reg);
713 count /= sizeof(reg);
714
715 if (kbuf)
716 for (; count > 0 && pos < PT_MSR; --count)
717 regs[pos++] = *k++;
718 else
719 for (; count > 0 && pos < PT_MSR; --count) {
720 if (__get_user(reg, u++))
721 return -EFAULT;
722 regs[pos++] = reg;
723 }
724
725
726 if (count > 0 && pos == PT_MSR) {
727 if (kbuf)
728 reg = *k++;
729 else if (__get_user(reg, u++))
730 return -EFAULT;
731 set_user_msr(target, reg);
732 ++pos;
733 --count;
734 }
735
c2372eb9 736 if (kbuf) {
fa8f5cb0
RM		 737 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
738 regs[pos++] = *k++;
c2372eb9
RM		 739 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
740 ++k;
741 } else {
fa8f5cb0
RM		 742 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
743 if (__get_user(reg, u++))
744 return -EFAULT;
745 regs[pos++] = reg;
746 }
c2372eb9
RM		 747 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
748 if (__get_user(reg, u++))
749 return -EFAULT;
750 }
fa8f5cb0
RM		 751
752 if (count > 0 && pos == PT_TRAP) {
753 if (kbuf)
754 reg = *k++;
755 else if (__get_user(reg, u++))
756 return -EFAULT;
757 set_user_trap(target, reg);
758 ++pos;
759 --count;
760 }
761
762 kbuf = k;
763 ubuf = u;
764 pos *= sizeof(reg);
765 count *= sizeof(reg);
766 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
767 (PT_TRAP + 1) * sizeof(reg), -1);
768}
769
770/*
771 * These are the regset flavors matching the CONFIG_PPC32 native set.
772 */
773static const struct user_regset compat_regsets[] = {
774 [REGSET_GPR] = {
775 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
776 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
777 .get = gpr32_get, .set = gpr32_set
778 },
779 [REGSET_FPR] = {
780 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
781 .size = sizeof(double), .align = sizeof(double),
782 .get = fpr_get, .set = fpr_set
783 },
784#ifdef CONFIG_ALTIVEC
785 [REGSET_VMX] = {
786 .core_note_type = NT_PPC_VMX, .n = 34,
787 .size = sizeof(vector128), .align = sizeof(vector128),
788 .active = vr_active, .get = vr_get, .set = vr_set
789 },
790#endif
791#ifdef CONFIG_SPE
792 [REGSET_SPE] = {
24f1a849 793 .core_note_type = NT_PPC_SPE, .n = 35,
fa8f5cb0
RM		 794 .size = sizeof(u32), .align = sizeof(u32),
795 .active = evr_active, .get = evr_get, .set = evr_set
796 },
797#endif
798};
799
800static const struct user_regset_view user_ppc_compat_view = {
801 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
802 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
803};
804#endif /* CONFIG_PPC64 */
805
80fdf470
RM		 806const struct user_regset_view *task_user_regset_view(struct task_struct *task)
807{
fa8f5cb0
RM		 808#ifdef CONFIG_PPC64
809 if (test_tsk_thread_flag(task, TIF_32BIT))
810 return &user_ppc_compat_view;
811#endif
80fdf470
RM		 812 return &user_ppc_native_view;
813}
814
815
2a84b0d7 816void user_enable_single_step(struct task_struct *task)
865418d8
BH		 817{
818 struct pt_regs *regs = task->thread.regs;
819
820 if (regs != NULL) {
172ae2e7 821#ifdef CONFIG_PPC_ADV_DEBUG_REGS
ec097c84 822 task->thread.dbcr0 &= ~DBCR0_BT;
d6a61bfc 823 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
865418d8
BH		 824 regs->msr |= MSR_DE;
825#else
ec097c84 826 regs->msr &= ~MSR_BE;
865418d8
BH		 827 regs->msr |= MSR_SE;
828#endif
829 }
830 set_tsk_thread_flag(task, TIF_SINGLESTEP);
831}
832
ec097c84
RM		 833void user_enable_block_step(struct task_struct *task)
834{
835 struct pt_regs *regs = task->thread.regs;
836
837 if (regs != NULL) {
172ae2e7 838#ifdef CONFIG_PPC_ADV_DEBUG_REGS
ec097c84
RM		 839 task->thread.dbcr0 &= ~DBCR0_IC;
840 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
841 regs->msr |= MSR_DE;
842#else
843 regs->msr &= ~MSR_SE;
844 regs->msr |= MSR_BE;
845#endif
846 }
847 set_tsk_thread_flag(task, TIF_SINGLESTEP);
848}
849
2a84b0d7 850void user_disable_single_step(struct task_struct *task)
865418d8
BH		 851{
852 struct pt_regs *regs = task->thread.regs;
853
854 if (regs != NULL) {
172ae2e7 855#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3bffb652
DK		 856 /*
857 * The logic to disable single stepping should be as
858 * simple as turning off the Instruction Complete flag.
859 * And, after doing so, if all debug flags are off, turn
860 * off DBCR0(IDM) and MSR(DE) .... Torez
861 */
862 task->thread.dbcr0 &= ~DBCR0_IC;
863 /*
864 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
865 */
866 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
867 task->thread.dbcr1)) {
868 /*
869 * All debug events were off.....
870 */
871 task->thread.dbcr0 &= ~DBCR0_IDM;
28477fb1
DK		 872 regs->msr &= ~MSR_DE;
873 }
865418d8 874#else
ec097c84 875 regs->msr &= ~(MSR_SE | MSR_BE);
865418d8
BH		 876#endif
877 }
878 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
879}
880
5aae8a53 881#ifdef CONFIG_HAVE_HW_BREAKPOINT
a8b0ca17 882void ptrace_triggered(struct perf_event *bp,
5aae8a53
P		 883 struct perf_sample_data *data, struct pt_regs *regs)
884{
885 struct perf_event_attr attr;
886
887 /*
888 * Disable the breakpoint request here since ptrace has defined a
889 * one-shot behaviour for breakpoint exceptions in PPC64.
890 * The SIGTRAP signal is generated automatically for us in do_dabr().
891 * We don't have to do anything about that here
892 */
893 attr = bp->attr;
894 attr.disabled = true;
895 modify_user_hw_breakpoint(bp, &attr);
896}
897#endif /* CONFIG_HAVE_HW_BREAKPOINT */
898
d6a61bfc 899int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
abd06505
BH		 900 unsigned long data)
901{
5aae8a53
P		 902#ifdef CONFIG_HAVE_HW_BREAKPOINT
903 int ret;
904 struct thread_struct *thread = &(task->thread);
905 struct perf_event *bp;
906 struct perf_event_attr attr;
907#endif /* CONFIG_HAVE_HW_BREAKPOINT */
908
d6a61bfc
LM		 909 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
910 * For embedded processors we support one DAC and no IAC's at the
911 * moment.
912 */
abd06505
BH		 913 if (addr > 0)
914 return -EINVAL;
915
2325f0a0 916 /* The bottom 3 bits in dabr are flags */
abd06505
BH		 917 if ((data & ~0x7UL) >= TASK_SIZE)
918 return -EIO;
919
172ae2e7 920#ifndef CONFIG_PPC_ADV_DEBUG_REGS
d6a61bfc
LM		 921 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
922 * It was assumed, on previous implementations, that 3 bits were
923 * passed together with the data address, fitting the design of the
924 * DABR register, as follows:
925 *
926 * bit 0: Read flag
927 * bit 1: Write flag
928 * bit 2: Breakpoint translation
929 *
930 * Thus, we use them here as so.
931 */
932
933 /* Ensure breakpoint translation bit is set */
abd06505
BH		 934 if (data && !(data & DABR_TRANSLATION))
935 return -EIO;
5aae8a53 936#ifdef CONFIG_HAVE_HW_BREAKPOINT
925f83c0
FW		 937 if (ptrace_get_breakpoints(task) < 0)
938 return -ESRCH;
939
5aae8a53
P		 940 bp = thread->ptrace_bps[0];
941 if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
942 if (bp) {
943 unregister_hw_breakpoint(bp);
944 thread->ptrace_bps[0] = NULL;
945 }
925f83c0 946 ptrace_put_breakpoints(task);
5aae8a53
P		 947 return 0;
948 }
949 if (bp) {
950 attr = bp->attr;
951 attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
952 arch_bp_generic_fields(data &
953 (DABR_DATA_WRITE | DABR_DATA_READ),
954 &attr.bp_type);
a53fd61a
AP		 955
956 /* Enable breakpoint */
957 attr.disabled = false;
958
5aae8a53 959 ret = modify_user_hw_breakpoint(bp, &attr);
925f83c0
FW		 960 if (ret) {
961 ptrace_put_breakpoints(task);
5aae8a53 962 return ret;
925f83c0 963 }
5aae8a53 964 thread->ptrace_bps[0] = bp;
925f83c0 965 ptrace_put_breakpoints(task);
5aae8a53 966 thread->dabr = data;
4474ef05 967 thread->dabrx = DABRX_ALL;
5aae8a53
P		 968 return 0;
969 }
970
971 /* Create a new breakpoint request if one doesn't exist already */
972 hw_breakpoint_init(&attr);
973 attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
974 arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
975 &attr.bp_type);
976
977 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
4dc0da86 978 ptrace_triggered, NULL, task);
5aae8a53
P		 979 if (IS_ERR(bp)) {
980 thread->ptrace_bps[0] = NULL;
925f83c0 981 ptrace_put_breakpoints(task);
5aae8a53
P		 982 return PTR_ERR(bp);
983 }
984
925f83c0
FW		 985 ptrace_put_breakpoints(task);
986
5aae8a53 987#endif /* CONFIG_HAVE_HW_BREAKPOINT */
abd06505 988
d6a61bfc 989 /* Move contents to the DABR register */
abd06505 990 task->thread.dabr = data;
4474ef05 991 task->thread.dabrx = DABRX_ALL;
172ae2e7 992#else /* CONFIG_PPC_ADV_DEBUG_REGS */
d6a61bfc
LM		 993 /* As described above, it was assumed 3 bits were passed with the data
994 * address, but we will assume only the mode bits will be passed
995 * as to not cause alignment restrictions for DAC-based processors.
996 */
997
998 /* DAC's hold the whole address without any mode flags */
3bffb652
DK		 999 task->thread.dac1 = data & ~0x3UL;
1000
1001 if (task->thread.dac1 == 0) {
1002 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1003 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
1004 task->thread.dbcr1)) {
1005 task->thread.regs->msr &= ~MSR_DE;
1006 task->thread.dbcr0 &= ~DBCR0_IDM;
1007 }
d6a61bfc
LM		 1008 return 0;
1009 }
1010
1011 /* Read or Write bits must be set */
1012
1013 if (!(data & 0x3UL))
1014 return -EINVAL;
1015
1016 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
1017 register */
3bffb652 1018 task->thread.dbcr0 |= DBCR0_IDM;
d6a61bfc
LM		 1019
1020 /* Check for write and read flags and set DBCR0
1021 accordingly */
3bffb652 1022 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
d6a61bfc 1023 if (data & 0x1UL)
3bffb652 1024 dbcr_dac(task) |= DBCR_DAC1R;
d6a61bfc 1025 if (data & 0x2UL)
3bffb652 1026 dbcr_dac(task) |= DBCR_DAC1W;
d6a61bfc 1027 task->thread.regs->msr |= MSR_DE;
172ae2e7 1028#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
abd06505
BH		 1029 return 0;
1030}
abd06505 1031
1da177e4
LT		 1032/*
1033 * Called by kernel/ptrace.c when detaching..
1034 *
1035 * Make sure single step bits etc are not set.
1036 */
1037void ptrace_disable(struct task_struct *child)
1038{
1039 /* make sure the single step bit is not set. */
2a84b0d7 1040 user_disable_single_step(child);
1da177e4
LT		 1041}
1042
3bffb652 1043#ifdef CONFIG_PPC_ADV_DEBUG_REGS
84295dfc 1044static long set_instruction_bp(struct task_struct *child,
3bffb652
DK		 1045 struct ppc_hw_breakpoint *bp_info)
1046{
1047 int slot;
1048 int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
1049 int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
1050 int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
1051 int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
1052
1053 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1054 slot2_in_use = 1;
1055 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1056 slot4_in_use = 1;
1057
1058 if (bp_info->addr >= TASK_SIZE)
1059 return -EIO;
1060
1061 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1062
1063 /* Make sure range is valid. */
1064 if (bp_info->addr2 >= TASK_SIZE)
1065 return -EIO;
1066
1067 /* We need a pair of IAC regsisters */
1068 if ((!slot1_in_use) && (!slot2_in_use)) {
1069 slot = 1;
1070 child->thread.iac1 = bp_info->addr;
1071 child->thread.iac2 = bp_info->addr2;
1072 child->thread.dbcr0 |= DBCR0_IAC1;
1073 if (bp_info->addr_mode ==
1074 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1075 dbcr_iac_range(child) |= DBCR_IAC12X;
1076 else
1077 dbcr_iac_range(child) |= DBCR_IAC12I;
1078#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1079 } else if ((!slot3_in_use) && (!slot4_in_use)) {
1080 slot = 3;
1081 child->thread.iac3 = bp_info->addr;
1082 child->thread.iac4 = bp_info->addr2;
1083 child->thread.dbcr0 |= DBCR0_IAC3;
1084 if (bp_info->addr_mode ==
1085 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1086 dbcr_iac_range(child) |= DBCR_IAC34X;
1087 else
1088 dbcr_iac_range(child) |= DBCR_IAC34I;
1089#endif
1090 } else
1091 return -ENOSPC;
1092 } else {
1093 /* We only need one. If possible leave a pair free in
1094 * case a range is needed later
1095 */
1096 if (!slot1_in_use) {
1097 /*
1098 * Don't use iac1 if iac1-iac2 are free and either
1099 * iac3 or iac4 (but not both) are free
1100 */
1101 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
1102 slot = 1;
1103 child->thread.iac1 = bp_info->addr;
1104 child->thread.dbcr0 |= DBCR0_IAC1;
1105 goto out;
1106 }
1107 }
1108 if (!slot2_in_use) {
1109 slot = 2;
1110 child->thread.iac2 = bp_info->addr;
1111 child->thread.dbcr0 |= DBCR0_IAC2;
1112#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1113 } else if (!slot3_in_use) {
1114 slot = 3;
1115 child->thread.iac3 = bp_info->addr;
1116 child->thread.dbcr0 |= DBCR0_IAC3;
1117 } else if (!slot4_in_use) {
1118 slot = 4;
1119 child->thread.iac4 = bp_info->addr;
1120 child->thread.dbcr0 |= DBCR0_IAC4;
1121#endif
1122 } else
1123 return -ENOSPC;
1124 }
1125out:
1126 child->thread.dbcr0 |= DBCR0_IDM;
1127 child->thread.regs->msr |= MSR_DE;
1128
1129 return slot;
1130}
1131
1132static int del_instruction_bp(struct task_struct *child, int slot)
1133{
1134 switch (slot) {
1135 case 1:
30124d11 1136 if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
3bffb652
DK		 1137 return -ENOENT;
1138
1139 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
1140 /* address range - clear slots 1 & 2 */
1141 child->thread.iac2 = 0;
1142 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
1143 }
1144 child->thread.iac1 = 0;
1145 child->thread.dbcr0 &= ~DBCR0_IAC1;
1146 break;
1147 case 2:
30124d11 1148 if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
3bffb652
DK		 1149 return -ENOENT;
1150
1151 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1152 /* used in a range */
1153 return -EINVAL;
1154 child->thread.iac2 = 0;
1155 child->thread.dbcr0 &= ~DBCR0_IAC2;
1156 break;
1157#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1158 case 3:
30124d11 1159 if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
3bffb652
DK		 1160 return -ENOENT;
1161
1162 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
1163 /* address range - clear slots 3 & 4 */
1164 child->thread.iac4 = 0;
1165 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
1166 }
1167 child->thread.iac3 = 0;
1168 child->thread.dbcr0 &= ~DBCR0_IAC3;
1169 break;
1170 case 4:
30124d11 1171 if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
3bffb652
DK		 1172 return -ENOENT;
1173
1174 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1175 /* Used in a range */
1176 return -EINVAL;
1177 child->thread.iac4 = 0;
1178 child->thread.dbcr0 &= ~DBCR0_IAC4;
1179 break;
1180#endif
1181 default:
1182 return -EINVAL;
1183 }
1184 return 0;
1185}
1186
1187static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1188{
1189 int byte_enable =
1190 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
1191 & 0xf;
1192 int condition_mode =
1193 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
1194 int slot;
1195
1196 if (byte_enable && (condition_mode == 0))
1197 return -EINVAL;
1198
1199 if (bp_info->addr >= TASK_SIZE)
1200 return -EIO;
1201
1202 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
1203 slot = 1;
1204 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1205 dbcr_dac(child) |= DBCR_DAC1R;
1206 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1207 dbcr_dac(child) |= DBCR_DAC1W;
1208 child->thread.dac1 = (unsigned long)bp_info->addr;
1209#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1210 if (byte_enable) {
1211 child->thread.dvc1 =
1212 (unsigned long)bp_info->condition_value;
1213 child->thread.dbcr2 |=
1214 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
1215 (condition_mode << DBCR2_DVC1M_SHIFT));
1216 }
1217#endif
1218#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1219 } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1220 /* Both dac1 and dac2 are part of a range */
1221 return -ENOSPC;
1222#endif
1223 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
1224 slot = 2;
1225 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1226 dbcr_dac(child) |= DBCR_DAC2R;
1227 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1228 dbcr_dac(child) |= DBCR_DAC2W;
1229 child->thread.dac2 = (unsigned long)bp_info->addr;
1230#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1231 if (byte_enable) {
1232 child->thread.dvc2 =
1233 (unsigned long)bp_info->condition_value;
1234 child->thread.dbcr2 |=
1235 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
1236 (condition_mode << DBCR2_DVC2M_SHIFT));
1237 }
1238#endif
1239 } else
1240 return -ENOSPC;
1241 child->thread.dbcr0 |= DBCR0_IDM;
1242 child->thread.regs->msr |= MSR_DE;
1243
1244 return slot + 4;
1245}
1246
1247static int del_dac(struct task_struct *child, int slot)
1248{
1249 if (slot == 1) {
30124d11 1250 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
3bffb652
DK		 1251 return -ENOENT;
1252
1253 child->thread.dac1 = 0;
1254 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1255#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1256 if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1257 child->thread.dac2 = 0;
1258 child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1259 }
1260 child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
1261#endif
1262#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1263 child->thread.dvc1 = 0;
1264#endif
1265 } else if (slot == 2) {
30124d11 1266 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
3bffb652
DK		 1267 return -ENOENT;
1268
1269#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1270 if (child->thread.dbcr2 & DBCR2_DAC12MODE)
1271 /* Part of a range */
1272 return -EINVAL;
1273 child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
1274#endif
1275#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1276 child->thread.dvc2 = 0;
1277#endif
1278 child->thread.dac2 = 0;
1279 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1280 } else
1281 return -EINVAL;
1282
1283 return 0;
1284}
1285#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1286
1287#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1288static int set_dac_range(struct task_struct *child,
1289 struct ppc_hw_breakpoint *bp_info)
1290{
1291 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
1292
1293 /* We don't allow range watchpoints to be used with DVC */
1294 if (bp_info->condition_mode)
1295 return -EINVAL;
1296
1297 /*
1298 * Best effort to verify the address range. The user/supervisor bits
1299 * prevent trapping in kernel space, but let's fail on an obvious bad
1300 * range. The simple test on the mask is not fool-proof, and any
1301 * exclusive range will spill over into kernel space.
1302 */
1303 if (bp_info->addr >= TASK_SIZE)
1304 return -EIO;
1305 if (mode == PPC_BREAKPOINT_MODE_MASK) {
1306 /*
1307 * dac2 is a bitmask. Don't allow a mask that makes a
1308 * kernel space address from a valid dac1 value
1309 */
1310 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
1311 return -EIO;
1312 } else {
1313 /*
1314 * For range breakpoints, addr2 must also be a valid address
1315 */
1316 if (bp_info->addr2 >= TASK_SIZE)
1317 return -EIO;
1318 }
1319
1320 if (child->thread.dbcr0 &
1321 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
1322 return -ENOSPC;
1323
1324 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1325 child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
1326 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1327 child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
1328 child->thread.dac1 = bp_info->addr;
1329 child->thread.dac2 = bp_info->addr2;
1330 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
1331 child->thread.dbcr2 |= DBCR2_DAC12M;
1332 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1333 child->thread.dbcr2 |= DBCR2_DAC12MX;
1334 else /* PPC_BREAKPOINT_MODE_MASK */
1335 child->thread.dbcr2 |= DBCR2_DAC12MM;
1336 child->thread.regs->msr |= MSR_DE;
1337
1338 return 5;
1339}
1340#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
1341
3162d92d
DK		 1342static long ppc_set_hwdebug(struct task_struct *child,
1343 struct ppc_hw_breakpoint *bp_info)
1344{
6c7a2856
P		 1345#ifdef CONFIG_HAVE_HW_BREAKPOINT
1346 int len = 0;
1347 struct thread_struct *thread = &(child->thread);
1348 struct perf_event *bp;
1349 struct perf_event_attr attr;
1350#endif /* CONFIG_HAVE_HW_BREAKPOINT */
4dfbf290
AS		 1351#ifndef CONFIG_PPC_ADV_DEBUG_REGS
1352 unsigned long dabr;
1353#endif
1354
3bffb652
DK		 1355 if (bp_info->version != 1)
1356 return -ENOTSUPP;
1357#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1358 /*
1359 * Check for invalid flags and combinations
1360 */
1361 if ((bp_info->trigger_type == 0) ||
1362 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
1363 PPC_BREAKPOINT_TRIGGER_RW)) ||
1364 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
1365 (bp_info->condition_mode &
1366 ~(PPC_BREAKPOINT_CONDITION_MODE |
1367 PPC_BREAKPOINT_CONDITION_BE_ALL)))
1368 return -EINVAL;
1369#if CONFIG_PPC_ADV_DEBUG_DVCS == 0
1370 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1371 return -EINVAL;
1372#endif
1373
1374 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
1375 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
1376 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
1377 return -EINVAL;
84295dfc 1378 return set_instruction_bp(child, bp_info);
3bffb652
DK		 1379 }
1380 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
1381 return set_dac(child, bp_info);
1382
1383#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1384 return set_dac_range(child, bp_info);
1385#else
1386 return -EINVAL;
1387#endif
1388#else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
3162d92d 1389 /*
3bffb652 1390 * We only support one data breakpoint
3162d92d 1391 */
4dfbf290
AS		 1392 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
1393 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
4dfbf290 1394 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
3162d92d
DK		 1395 return -EINVAL;
1396
3162d92d
DK		 1397 if ((unsigned long)bp_info->addr >= TASK_SIZE)
1398 return -EIO;
1399
4dfbf290
AS		 1400 dabr = (unsigned long)bp_info->addr & ~7UL;
1401 dabr |= DABR_TRANSLATION;
1402 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1403 dabr |= DABR_DATA_READ;
1404 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1405 dabr |= DABR_DATA_WRITE;
6c7a2856
P		 1406#ifdef CONFIG_HAVE_HW_BREAKPOINT
1407 if (ptrace_get_breakpoints(child) < 0)
1408 return -ESRCH;
1409
1410 /*
1411 * Check if the request is for 'range' breakpoints. We can
1412 * support it if range < 8 bytes.
1413 */
1414 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) {
1415 len = bp_info->addr2 - bp_info->addr;
1416 } else if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1417 ptrace_put_breakpoints(child);
1418 return -EINVAL;
1419 }
1420 bp = thread->ptrace_bps[0];
1421 if (bp) {
1422 ptrace_put_breakpoints(child);
1423 return -ENOSPC;
1424 }
1425
1426 /* Create a new breakpoint request if one doesn't exist already */
1427 hw_breakpoint_init(&attr);
1428 attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
1429 attr.bp_len = len;
1430 arch_bp_generic_fields(dabr & (DABR_DATA_WRITE | DABR_DATA_READ),
1431 &attr.bp_type);
1432
1433 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
1434 ptrace_triggered, NULL, child);
1435 if (IS_ERR(bp)) {
1436 thread->ptrace_bps[0] = NULL;
1437 ptrace_put_breakpoints(child);
1438 return PTR_ERR(bp);
1439 }
1440
1441 ptrace_put_breakpoints(child);
1442 return 1;
1443#endif /* CONFIG_HAVE_HW_BREAKPOINT */
1444
1445 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
1446 return -EINVAL;
1447
1448 if (child->thread.dabr)
1449 return -ENOSPC;
4dfbf290
AS		 1450
1451 child->thread.dabr = dabr;
4474ef05 1452 child->thread.dabrx = DABRX_ALL;
3bffb652 1453
3162d92d 1454 return 1;
3bffb652 1455#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
3162d92d
DK		 1456}
1457
ec1b33dc 1458static long ppc_del_hwdebug(struct task_struct *child, long data)
3162d92d 1459{
6c7a2856
P		 1460#ifdef CONFIG_HAVE_HW_BREAKPOINT
1461 int ret = 0;
1462 struct thread_struct *thread = &(child->thread);
1463 struct perf_event *bp;
1464#endif /* CONFIG_HAVE_HW_BREAKPOINT */
3bffb652
DK		 1465#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1466 int rc;
1467
1468 if (data <= 4)
1469 rc = del_instruction_bp(child, (int)data);
1470 else
1471 rc = del_dac(child, (int)data - 4);
1472
1473 if (!rc) {
1474 if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
1475 child->thread.dbcr1)) {
1476 child->thread.dbcr0 &= ~DBCR0_IDM;
1477 child->thread.regs->msr &= ~MSR_DE;
1478 }
1479 }
1480 return rc;
1481#else
3162d92d
DK		 1482 if (data != 1)
1483 return -EINVAL;
6c7a2856
P		 1484
1485#ifdef CONFIG_HAVE_HW_BREAKPOINT
1486 if (ptrace_get_breakpoints(child) < 0)
1487 return -ESRCH;
1488
1489 bp = thread->ptrace_bps[0];
1490 if (bp) {
1491 unregister_hw_breakpoint(bp);
1492 thread->ptrace_bps[0] = NULL;
1493 } else
1494 ret = -ENOENT;
1495 ptrace_put_breakpoints(child);
1496 return ret;
1497#else /* CONFIG_HAVE_HW_BREAKPOINT */
3162d92d
DK		 1498 if (child->thread.dabr == 0)
1499 return -ENOENT;
1500
1501 child->thread.dabr = 0;
6c7a2856 1502#endif /* CONFIG_HAVE_HW_BREAKPOINT */
3bffb652 1503
3162d92d 1504 return 0;
3bffb652 1505#endif
3162d92d
DK		 1506}
1507
9b05a69e
NK		 1508long arch_ptrace(struct task_struct *child, long request,
1509 unsigned long addr, unsigned long data)
1da177e4 1510{
1da177e4 1511 int ret = -EPERM;
f68d2048
NK		 1512 void __user *datavp = (void __user *) data;
1513 unsigned long __user *datalp = datavp;
1da177e4 1514
1da177e4 1515 switch (request) {
1da177e4 1516 /* read the word at location addr in the USER area. */
1da177e4
LT		 1517 case PTRACE_PEEKUSR: {
1518 unsigned long index, tmp;
1519
1520 ret = -EIO;
1521 /* convert to index and check */
e8a30302 1522#ifdef CONFIG_PPC32
9b05a69e 1523 index = addr >> 2;
e8a30302
SR		 1524 if ((addr & 3) || (index > PT_FPSCR)
1525 || (child->thread.regs == NULL))
1526#else
9b05a69e 1527 index = addr >> 3;
e8a30302
SR		 1528 if ((addr & 7) || (index > PT_FPSCR))
1529#endif
1da177e4
LT		 1530 break;
1531
1532 CHECK_FULL_REGS(child->thread.regs);
1533 if (index < PT_FPR0) {
865418d8 1534 tmp = ptrace_get_reg(child, (int) index);
1da177e4 1535 } else {
e69b742a
BH		 1536 unsigned int fpidx = index - PT_FPR0;
1537
e8a30302 1538 flush_fp_to_thread(child);
e69b742a
BH		 1539 if (fpidx < (PT_FPSCR - PT_FPR0))
1540 tmp = ((unsigned long *)child->thread.fpr)
1541 [fpidx * TS_FPRWIDTH];
1542 else
1543 tmp = child->thread.fpscr.val;
1da177e4 1544 }
f68d2048 1545 ret = put_user(tmp, datalp);
1da177e4
LT		 1546 break;
1547 }
1548
1da177e4
LT		 1549 /* write the word at location addr in the USER area */
1550 case PTRACE_POKEUSR: {
1551 unsigned long index;
1552
1553 ret = -EIO;
1554 /* convert to index and check */
e8a30302 1555#ifdef CONFIG_PPC32
9b05a69e 1556 index = addr >> 2;
e8a30302
SR		 1557 if ((addr & 3) || (index > PT_FPSCR)
1558 || (child->thread.regs == NULL))
1559#else
9b05a69e 1560 index = addr >> 3;
e8a30302
SR		 1561 if ((addr & 7) || (index > PT_FPSCR))
1562#endif
1da177e4
LT		 1563 break;
1564
1565 CHECK_FULL_REGS(child->thread.regs);
1da177e4 1566 if (index < PT_FPR0) {
865418d8 1567 ret = ptrace_put_reg(child, index, data);
1da177e4 1568 } else {
e69b742a
BH		 1569 unsigned int fpidx = index - PT_FPR0;
1570
e8a30302 1571 flush_fp_to_thread(child);
e69b742a
BH		 1572 if (fpidx < (PT_FPSCR - PT_FPR0))
1573 ((unsigned long *)child->thread.fpr)
1574 [fpidx * TS_FPRWIDTH] = data;
1575 else
1576 child->thread.fpscr.val = data;
1da177e4
LT		 1577 ret = 0;
1578 }
1579 break;
1580 }
1581
3162d92d
DK		 1582 case PPC_PTRACE_GETHWDBGINFO: {
1583 struct ppc_debug_info dbginfo;
1584
1585 dbginfo.version = 1;
3bffb652
DK		 1586#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1587 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
1588 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
1589 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
1590 dbginfo.data_bp_alignment = 4;
1591 dbginfo.sizeof_condition = 4;
1592 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
1593 PPC_DEBUG_FEATURE_INSN_BP_MASK;
1594#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1595 dbginfo.features |=
1596 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
1597 PPC_DEBUG_FEATURE_DATA_BP_MASK;
1598#endif
1599#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
3162d92d
DK		 1600 dbginfo.num_instruction_bps = 0;
1601 dbginfo.num_data_bps = 1;
1602 dbginfo.num_condition_regs = 0;
1603#ifdef CONFIG_PPC64
1604 dbginfo.data_bp_alignment = 8;
1605#else
1606 dbginfo.data_bp_alignment = 4;
1607#endif
1608 dbginfo.sizeof_condition = 0;
6c7a2856
P		 1609#ifdef CONFIG_HAVE_HW_BREAKPOINT
1610 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
1611#else
3162d92d 1612 dbginfo.features = 0;
6c7a2856 1613#endif /* CONFIG_HAVE_HW_BREAKPOINT */
3bffb652 1614#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
3162d92d 1615
f68d2048 1616 if (!access_ok(VERIFY_WRITE, datavp,
3162d92d
DK		 1617 sizeof(struct ppc_debug_info)))
1618 return -EFAULT;
f68d2048
NK		 1619 ret = __copy_to_user(datavp, &dbginfo,
1620 sizeof(struct ppc_debug_info)) ?
3162d92d
DK		 1621 -EFAULT : 0;
1622 break;
1623 }
1624
1625 case PPC_PTRACE_SETHWDEBUG: {
1626 struct ppc_hw_breakpoint bp_info;
1627
f68d2048 1628 if (!access_ok(VERIFY_READ, datavp,
3162d92d
DK		 1629 sizeof(struct ppc_hw_breakpoint)))
1630 return -EFAULT;
f68d2048 1631 ret = __copy_from_user(&bp_info, datavp,
3162d92d
DK		 1632 sizeof(struct ppc_hw_breakpoint)) ?
1633 -EFAULT : 0;
1634 if (!ret)
1635 ret = ppc_set_hwdebug(child, &bp_info);
1636 break;
1637 }
1638
1639 case PPC_PTRACE_DELHWDEBUG: {
ec1b33dc 1640 ret = ppc_del_hwdebug(child, data);
3162d92d
DK		 1641 break;
1642 }
1643
e8a30302
SR		 1644 case PTRACE_GET_DEBUGREG: {
1645 ret = -EINVAL;
1646 /* We only support one DABR and no IABRS at the moment */
1647 if (addr > 0)
1648 break;
3bffb652 1649#ifdef CONFIG_PPC_ADV_DEBUG_REGS
f68d2048 1650 ret = put_user(child->thread.dac1, datalp);
3bffb652 1651#else
f68d2048 1652 ret = put_user(child->thread.dabr, datalp);
3bffb652 1653#endif
e8a30302
SR		 1654 break;
1655 }
1656
1657 case PTRACE_SET_DEBUGREG:
1658 ret = ptrace_set_debugreg(child, addr, data);
1659 break;
e8a30302 1660
e17666ba
BH		 1661#ifdef CONFIG_PPC64
1662 case PTRACE_GETREGS64:
1663#endif
c391cd00
RM		 1664 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
1665 return copy_regset_to_user(child, &user_ppc_native_view,
1666 REGSET_GPR,
1667 0, sizeof(struct pt_regs),
f68d2048 1668 datavp);
e8a30302 1669
e17666ba
BH		 1670#ifdef CONFIG_PPC64
1671 case PTRACE_SETREGS64:
1672#endif
c391cd00
RM		 1673 case PTRACE_SETREGS: /* Set all gp regs in the child. */
1674 return copy_regset_from_user(child, &user_ppc_native_view,
1675 REGSET_GPR,
1676 0, sizeof(struct pt_regs),
f68d2048 1677 datavp);
c391cd00
RM		 1678
1679 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
1680 return copy_regset_to_user(child, &user_ppc_native_view,
1681 REGSET_FPR,
1682 0, sizeof(elf_fpregset_t),
f68d2048 1683 datavp);
c391cd00
RM		 1684
1685 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
1686 return copy_regset_from_user(child, &user_ppc_native_view,
1687 REGSET_FPR,
1688 0, sizeof(elf_fpregset_t),
f68d2048 1689 datavp);
e8a30302 1690
1da177e4
LT		 1691#ifdef CONFIG_ALTIVEC
1692 case PTRACE_GETVRREGS:
c391cd00
RM		 1693 return copy_regset_to_user(child, &user_ppc_native_view,
1694 REGSET_VMX,
1695 0, (33 * sizeof(vector128) +
1696 sizeof(u32)),
f68d2048 1697 datavp);
1da177e4
LT		 1698
1699 case PTRACE_SETVRREGS:
c391cd00
RM		 1700 return copy_regset_from_user(child, &user_ppc_native_view,
1701 REGSET_VMX,
1702 0, (33 * sizeof(vector128) +
1703 sizeof(u32)),
f68d2048 1704 datavp);
1da177e4 1705#endif
ce48b210
MN		 1706#ifdef CONFIG_VSX
1707 case PTRACE_GETVSRREGS:
1708 return copy_regset_to_user(child, &user_ppc_native_view,
1709 REGSET_VSX,
1ac42ef8 1710 0, 32 * sizeof(double),
f68d2048 1711 datavp);
ce48b210
MN		 1712
1713 case PTRACE_SETVSRREGS:
1714 return copy_regset_from_user(child, &user_ppc_native_view,
1715 REGSET_VSX,
1ac42ef8 1716 0, 32 * sizeof(double),
f68d2048 1717 datavp);
ce48b210 1718#endif
1da177e4
LT		 1719#ifdef CONFIG_SPE
1720 case PTRACE_GETEVRREGS:
1721 /* Get the child spe register state. */
c391cd00
RM		 1722 return copy_regset_to_user(child, &user_ppc_native_view,
1723 REGSET_SPE, 0, 35 * sizeof(u32),
f68d2048 1724 datavp);
1da177e4
LT		 1725
1726 case PTRACE_SETEVRREGS:
1727 /* Set the child spe register state. */
c391cd00
RM		 1728 return copy_regset_from_user(child, &user_ppc_native_view,
1729 REGSET_SPE, 0, 35 * sizeof(u32),
f68d2048 1730 datavp);
1da177e4
LT		 1731#endif
1732
1733 default:
1734 ret = ptrace_request(child, request, addr, data);
1735 break;
1736 }
1da177e4
LT		 1737 return ret;
1738}
1739
4f72c427
RM		 1740/*
1741 * We must return the syscall number to actually look up in the table.
1742 * This can be -1L to skip running any syscall at all.
1743 */
1744long do_syscall_trace_enter(struct pt_regs *regs)
1da177e4 1745{
4f72c427 1746 long ret = 0;
ea9c102c 1747
e4da89d0 1748 secure_computing_strict(regs->gpr[0]);
e8a30302 1749
4f72c427
RM		 1750 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
1751 tracehook_report_syscall_entry(regs))
1752 /*
1753 * Tracing decided this syscall should not happen.
1754 * We'll return a bogus call number to get an ENOSYS
1755 * error, but leave the original number in regs->gpr[0].
1756 */
1757 ret = -1L;
ea9c102c 1758
02424d89
IM		 1759 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1760 trace_sys_enter(regs, regs->gpr[0]);
1761
cfcd1705 1762#ifdef CONFIG_PPC64
b05d8447
EP		 1763 if (!is_32bit_task())
1764 audit_syscall_entry(AUDIT_ARCH_PPC64,
1765 regs->gpr[0],
1766 regs->gpr[3], regs->gpr[4],
1767 regs->gpr[5], regs->gpr[6]);
1768 else
e8a30302 1769#endif
b05d8447
EP		 1770 audit_syscall_entry(AUDIT_ARCH_PPC,
1771 regs->gpr[0],
1772 regs->gpr[3] & 0xffffffff,
1773 regs->gpr[4] & 0xffffffff,
1774 regs->gpr[5] & 0xffffffff,
1775 regs->gpr[6] & 0xffffffff);
4f72c427
RM		 1776
1777 return ret ?: regs->gpr[0];
ea9c102c
DW		 1778}
1779
1780void do_syscall_trace_leave(struct pt_regs *regs)
1781{
4f72c427
RM		 1782 int step;
1783
d7e7528b 1784 audit_syscall_exit(regs);
ea9c102c 1785
02424d89
IM		 1786 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1787 trace_sys_exit(regs, regs->result);
1788
4f72c427
RM		 1789 step = test_thread_flag(TIF_SINGLESTEP);
1790 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
1791 tracehook_report_syscall_exit(regs, step);
ea9c102c 1792}
Linux kernel - Deliverables
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