Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ptrace.h> | |
f65255e8 | 24 | #include <linux/regset.h> |
4f72c427 | 25 | #include <linux/tracehook.h> |
3caf06c6 | 26 | #include <linux/elf.h> |
1da177e4 LT |
27 | #include <linux/user.h> |
28 | #include <linux/security.h> | |
7ed20e1a | 29 | #include <linux/signal.h> |
ea9c102c DW |
30 | #include <linux/seccomp.h> |
31 | #include <linux/audit.h> | |
02424d89 | 32 | #include <trace/syscall.h> |
5aae8a53 P |
33 | #include <linux/hw_breakpoint.h> |
34 | #include <linux/perf_event.h> | |
22ecbe8d | 35 | #include <linux/context_tracking.h> |
1da177e4 LT |
36 | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/pgtable.h> | |
ae3a197e | 40 | #include <asm/switch_to.h> |
21a62902 | 41 | |
02424d89 IM |
42 | #define CREATE_TRACE_POINTS |
43 | #include <trace/events/syscalls.h> | |
44 | ||
359e4284 MS |
45 | /* |
46 | * The parameter save area on the stack is used to store arguments being passed | |
47 | * to callee function and is located at fixed offset from stack pointer. | |
48 | */ | |
49 | #ifdef CONFIG_PPC32 | |
50 | #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */ | |
51 | #else /* CONFIG_PPC32 */ | |
52 | #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */ | |
53 | #endif | |
54 | ||
55 | struct pt_regs_offset { | |
56 | const char *name; | |
57 | int offset; | |
58 | }; | |
59 | ||
60 | #define STR(s) #s /* convert to string */ | |
61 | #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} | |
62 | #define GPR_OFFSET_NAME(num) \ | |
343c3327 | 63 | {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \ |
359e4284 MS |
64 | {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])} |
65 | #define REG_OFFSET_END {.name = NULL, .offset = 0} | |
66 | ||
67 | static const struct pt_regs_offset regoffset_table[] = { | |
68 | GPR_OFFSET_NAME(0), | |
69 | GPR_OFFSET_NAME(1), | |
70 | GPR_OFFSET_NAME(2), | |
71 | GPR_OFFSET_NAME(3), | |
72 | GPR_OFFSET_NAME(4), | |
73 | GPR_OFFSET_NAME(5), | |
74 | GPR_OFFSET_NAME(6), | |
75 | GPR_OFFSET_NAME(7), | |
76 | GPR_OFFSET_NAME(8), | |
77 | GPR_OFFSET_NAME(9), | |
78 | GPR_OFFSET_NAME(10), | |
79 | GPR_OFFSET_NAME(11), | |
80 | GPR_OFFSET_NAME(12), | |
81 | GPR_OFFSET_NAME(13), | |
82 | GPR_OFFSET_NAME(14), | |
83 | GPR_OFFSET_NAME(15), | |
84 | GPR_OFFSET_NAME(16), | |
85 | GPR_OFFSET_NAME(17), | |
86 | GPR_OFFSET_NAME(18), | |
87 | GPR_OFFSET_NAME(19), | |
88 | GPR_OFFSET_NAME(20), | |
89 | GPR_OFFSET_NAME(21), | |
90 | GPR_OFFSET_NAME(22), | |
91 | GPR_OFFSET_NAME(23), | |
92 | GPR_OFFSET_NAME(24), | |
93 | GPR_OFFSET_NAME(25), | |
94 | GPR_OFFSET_NAME(26), | |
95 | GPR_OFFSET_NAME(27), | |
96 | GPR_OFFSET_NAME(28), | |
97 | GPR_OFFSET_NAME(29), | |
98 | GPR_OFFSET_NAME(30), | |
99 | GPR_OFFSET_NAME(31), | |
100 | REG_OFFSET_NAME(nip), | |
101 | REG_OFFSET_NAME(msr), | |
102 | REG_OFFSET_NAME(ctr), | |
103 | REG_OFFSET_NAME(link), | |
104 | REG_OFFSET_NAME(xer), | |
105 | REG_OFFSET_NAME(ccr), | |
106 | #ifdef CONFIG_PPC64 | |
107 | REG_OFFSET_NAME(softe), | |
108 | #else | |
109 | REG_OFFSET_NAME(mq), | |
110 | #endif | |
111 | REG_OFFSET_NAME(trap), | |
112 | REG_OFFSET_NAME(dar), | |
113 | REG_OFFSET_NAME(dsisr), | |
114 | REG_OFFSET_END, | |
115 | }; | |
116 | ||
117 | /** | |
118 | * regs_query_register_offset() - query register offset from its name | |
119 | * @name: the name of a register | |
120 | * | |
121 | * regs_query_register_offset() returns the offset of a register in struct | |
122 | * pt_regs from its name. If the name is invalid, this returns -EINVAL; | |
123 | */ | |
124 | int regs_query_register_offset(const char *name) | |
125 | { | |
126 | const struct pt_regs_offset *roff; | |
127 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
128 | if (!strcmp(roff->name, name)) | |
129 | return roff->offset; | |
130 | return -EINVAL; | |
131 | } | |
132 | ||
133 | /** | |
134 | * regs_query_register_name() - query register name from its offset | |
135 | * @offset: the offset of a register in struct pt_regs. | |
136 | * | |
137 | * regs_query_register_name() returns the name of a register from its | |
138 | * offset in struct pt_regs. If the @offset is invalid, this returns NULL; | |
139 | */ | |
140 | const char *regs_query_register_name(unsigned int offset) | |
141 | { | |
142 | const struct pt_regs_offset *roff; | |
143 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
144 | if (roff->offset == offset) | |
145 | return roff->name; | |
146 | return NULL; | |
147 | } | |
148 | ||
abd06505 BH |
149 | /* |
150 | * does not yet catch signals sent when the child dies. | |
151 | * in exit.c or in signal.c. | |
152 | */ | |
153 | ||
154 | /* | |
155 | * Set of msr bits that gdb can change on behalf of a process. | |
156 | */ | |
172ae2e7 | 157 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
abd06505 | 158 | #define MSR_DEBUGCHANGE 0 |
1da177e4 | 159 | #else |
abd06505 | 160 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) |
1da177e4 | 161 | #endif |
acd89828 | 162 | |
1da177e4 | 163 | /* |
abd06505 | 164 | * Max register writeable via put_reg |
1da177e4 | 165 | */ |
abd06505 BH |
166 | #ifdef CONFIG_PPC32 |
167 | #define PT_MAX_PUT_REG PT_MQ | |
168 | #else | |
169 | #define PT_MAX_PUT_REG PT_CCR | |
170 | #endif | |
1da177e4 | 171 | |
26f77130 RM |
172 | static unsigned long get_user_msr(struct task_struct *task) |
173 | { | |
174 | return task->thread.regs->msr | task->thread.fpexc_mode; | |
175 | } | |
176 | ||
177 | static int set_user_msr(struct task_struct *task, unsigned long msr) | |
178 | { | |
179 | task->thread.regs->msr &= ~MSR_DEBUGCHANGE; | |
180 | task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; | |
181 | return 0; | |
182 | } | |
183 | ||
25847fb1 AK |
184 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
185 | static unsigned long get_user_ckpt_msr(struct task_struct *task) | |
186 | { | |
187 | return task->thread.ckpt_regs.msr | task->thread.fpexc_mode; | |
188 | } | |
189 | ||
190 | static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr) | |
191 | { | |
192 | task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE; | |
193 | task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE; | |
194 | return 0; | |
195 | } | |
196 | ||
197 | static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap) | |
198 | { | |
199 | task->thread.ckpt_regs.trap = trap & 0xfff0; | |
200 | return 0; | |
201 | } | |
202 | #endif | |
203 | ||
1715a826 | 204 | #ifdef CONFIG_PPC64 |
ee4a3916 | 205 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 | 206 | { |
ee4a3916 AK |
207 | *data = task->thread.dscr; |
208 | return 0; | |
1715a826 AK |
209 | } |
210 | ||
211 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
212 | { | |
213 | task->thread.dscr = dscr; | |
214 | task->thread.dscr_inherit = 1; | |
215 | return 0; | |
216 | } | |
217 | #else | |
ee4a3916 | 218 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 AK |
219 | { |
220 | return -EIO; | |
221 | } | |
222 | ||
223 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
224 | { | |
225 | return -EIO; | |
226 | } | |
227 | #endif | |
228 | ||
26f77130 RM |
229 | /* |
230 | * We prevent mucking around with the reserved area of trap | |
231 | * which are used internally by the kernel. | |
232 | */ | |
233 | static int set_user_trap(struct task_struct *task, unsigned long trap) | |
234 | { | |
235 | task->thread.regs->trap = trap & 0xfff0; | |
236 | return 0; | |
237 | } | |
238 | ||
865418d8 BH |
239 | /* |
240 | * Get contents of register REGNO in task TASK. | |
241 | */ | |
ee4a3916 | 242 | int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data) |
865418d8 | 243 | { |
ee4a3916 | 244 | if ((task->thread.regs == NULL) || !data) |
865418d8 BH |
245 | return -EIO; |
246 | ||
ee4a3916 AK |
247 | if (regno == PT_MSR) { |
248 | *data = get_user_msr(task); | |
249 | return 0; | |
250 | } | |
865418d8 | 251 | |
1715a826 | 252 | if (regno == PT_DSCR) |
ee4a3916 | 253 | return get_user_dscr(task, data); |
1715a826 | 254 | |
ee4a3916 AK |
255 | if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) { |
256 | *data = ((unsigned long *)task->thread.regs)[regno]; | |
257 | return 0; | |
258 | } | |
865418d8 BH |
259 | |
260 | return -EIO; | |
261 | } | |
262 | ||
263 | /* | |
264 | * Write contents of register REGNO in task TASK. | |
265 | */ | |
266 | int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) | |
267 | { | |
268 | if (task->thread.regs == NULL) | |
269 | return -EIO; | |
270 | ||
26f77130 RM |
271 | if (regno == PT_MSR) |
272 | return set_user_msr(task, data); | |
273 | if (regno == PT_TRAP) | |
274 | return set_user_trap(task, data); | |
1715a826 AK |
275 | if (regno == PT_DSCR) |
276 | return set_user_dscr(task, data); | |
26f77130 RM |
277 | |
278 | if (regno <= PT_MAX_PUT_REG) { | |
865418d8 BH |
279 | ((unsigned long *)task->thread.regs)[regno] = data; |
280 | return 0; | |
281 | } | |
282 | return -EIO; | |
283 | } | |
284 | ||
44dd3f50 RM |
285 | static int gpr_get(struct task_struct *target, const struct user_regset *regset, |
286 | unsigned int pos, unsigned int count, | |
287 | void *kbuf, void __user *ubuf) | |
288 | { | |
a71f5d5d | 289 | int i, ret; |
44dd3f50 RM |
290 | |
291 | if (target->thread.regs == NULL) | |
292 | return -EIO; | |
293 | ||
a71f5d5d MW |
294 | if (!FULL_REGS(target->thread.regs)) { |
295 | /* We have a partial register set. Fill 14-31 with bogus values */ | |
296 | for (i = 14; i < 32; i++) | |
297 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
298 | } | |
44dd3f50 RM |
299 | |
300 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
301 | target->thread.regs, | |
302 | 0, offsetof(struct pt_regs, msr)); | |
303 | if (!ret) { | |
304 | unsigned long msr = get_user_msr(target); | |
305 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
306 | offsetof(struct pt_regs, msr), | |
307 | offsetof(struct pt_regs, msr) + | |
308 | sizeof(msr)); | |
309 | } | |
310 | ||
311 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
312 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
313 | ||
314 | if (!ret) | |
315 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
316 | &target->thread.regs->orig_gpr3, | |
317 | offsetof(struct pt_regs, orig_gpr3), | |
318 | sizeof(struct pt_regs)); | |
319 | if (!ret) | |
320 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
321 | sizeof(struct pt_regs), -1); | |
322 | ||
323 | return ret; | |
324 | } | |
325 | ||
326 | static int gpr_set(struct task_struct *target, const struct user_regset *regset, | |
327 | unsigned int pos, unsigned int count, | |
328 | const void *kbuf, const void __user *ubuf) | |
329 | { | |
330 | unsigned long reg; | |
331 | int ret; | |
332 | ||
333 | if (target->thread.regs == NULL) | |
334 | return -EIO; | |
335 | ||
336 | CHECK_FULL_REGS(target->thread.regs); | |
337 | ||
338 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
339 | target->thread.regs, | |
340 | 0, PT_MSR * sizeof(reg)); | |
341 | ||
342 | if (!ret && count > 0) { | |
343 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
344 | PT_MSR * sizeof(reg), | |
345 | (PT_MSR + 1) * sizeof(reg)); | |
346 | if (!ret) | |
347 | ret = set_user_msr(target, reg); | |
348 | } | |
349 | ||
350 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
351 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
352 | ||
353 | if (!ret) | |
354 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
355 | &target->thread.regs->orig_gpr3, | |
356 | PT_ORIG_R3 * sizeof(reg), | |
357 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
358 | ||
359 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
360 | ret = user_regset_copyin_ignore( | |
361 | &pos, &count, &kbuf, &ubuf, | |
362 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
363 | PT_TRAP * sizeof(reg)); | |
364 | ||
365 | if (!ret && count > 0) { | |
366 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
367 | PT_TRAP * sizeof(reg), | |
368 | (PT_TRAP + 1) * sizeof(reg)); | |
369 | if (!ret) | |
370 | ret = set_user_trap(target, reg); | |
371 | } | |
372 | ||
373 | if (!ret) | |
374 | ret = user_regset_copyin_ignore( | |
375 | &pos, &count, &kbuf, &ubuf, | |
376 | (PT_TRAP + 1) * sizeof(reg), -1); | |
377 | ||
378 | return ret; | |
379 | } | |
865418d8 | 380 | |
1ec8549d AK |
381 | /* |
382 | * When the transaction is active, 'transact_fp' holds the current running | |
383 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
384 | * value of all FPR registers for the current transaction. When transaction | |
385 | * is not active 'fp_state' holds the current running state of all the FPR | |
386 | * registers. So this function which returns the current running values of | |
387 | * all the FPR registers, needs to know whether any transaction is active | |
388 | * or not. | |
389 | * | |
390 | * Userspace interface buffer layout: | |
391 | * | |
392 | * struct data { | |
393 | * u64 fpr[32]; | |
394 | * u64 fpscr; | |
395 | * }; | |
396 | * | |
397 | * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM | |
398 | * which determines the final code in this function. All the combinations of | |
399 | * these two config options are possible except the one below as transactional | |
400 | * memory config pulls in CONFIG_VSX automatically. | |
401 | * | |
402 | * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
403 | */ | |
f65255e8 RM |
404 | static int fpr_get(struct task_struct *target, const struct user_regset *regset, |
405 | unsigned int pos, unsigned int count, | |
406 | void *kbuf, void __user *ubuf) | |
407 | { | |
c6e6771b | 408 | #ifdef CONFIG_VSX |
de79f7b9 | 409 | u64 buf[33]; |
c6e6771b MN |
410 | int i; |
411 | #endif | |
f65255e8 RM |
412 | flush_fp_to_thread(target); |
413 | ||
1ec8549d AK |
414 | #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
415 | /* copy to local buffer then write that out */ | |
416 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
417 | flush_altivec_to_thread(target); | |
418 | flush_tmregs_to_thread(target); | |
419 | for (i = 0; i < 32 ; i++) | |
420 | buf[i] = target->thread.TS_TRANS_FPR(i); | |
421 | buf[32] = target->thread.transact_fp.fpscr; | |
422 | } else { | |
423 | for (i = 0; i < 32 ; i++) | |
424 | buf[i] = target->thread.TS_FPR(i); | |
425 | buf[32] = target->thread.fp_state.fpscr; | |
426 | } | |
427 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
428 | #endif | |
429 | ||
430 | #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
c6e6771b MN |
431 | /* copy to local buffer then write that out */ |
432 | for (i = 0; i < 32 ; i++) | |
433 | buf[i] = target->thread.TS_FPR(i); | |
de79f7b9 | 434 | buf[32] = target->thread.fp_state.fpscr; |
c6e6771b | 435 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); |
1ec8549d | 436 | #endif |
c6e6771b | 437 | |
1ec8549d | 438 | #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
de79f7b9 | 439 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 440 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
441 | |
442 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 443 | &target->thread.fp_state, 0, -1); |
c6e6771b | 444 | #endif |
f65255e8 RM |
445 | } |
446 | ||
1ec8549d AK |
447 | /* |
448 | * When the transaction is active, 'transact_fp' holds the current running | |
449 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
450 | * value of all FPR registers for the current transaction. When transaction | |
451 | * is not active 'fp_state' holds the current running state of all the FPR | |
452 | * registers. So this function which setss the current running values of | |
453 | * all the FPR registers, needs to know whether any transaction is active | |
454 | * or not. | |
455 | * | |
456 | * Userspace interface buffer layout: | |
457 | * | |
458 | * struct data { | |
459 | * u64 fpr[32]; | |
460 | * u64 fpscr; | |
461 | * }; | |
462 | * | |
463 | * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM | |
464 | * which determines the final code in this function. All the combinations of | |
465 | * these two config options are possible except the one below as transactional | |
466 | * memory config pulls in CONFIG_VSX automatically. | |
467 | * | |
468 | * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
469 | */ | |
f65255e8 RM |
470 | static int fpr_set(struct task_struct *target, const struct user_regset *regset, |
471 | unsigned int pos, unsigned int count, | |
472 | const void *kbuf, const void __user *ubuf) | |
473 | { | |
c6e6771b | 474 | #ifdef CONFIG_VSX |
de79f7b9 | 475 | u64 buf[33]; |
c6e6771b MN |
476 | int i; |
477 | #endif | |
f65255e8 RM |
478 | flush_fp_to_thread(target); |
479 | ||
1ec8549d AK |
480 | #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
481 | /* copy to local buffer then write that out */ | |
482 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
483 | if (i) | |
484 | return i; | |
485 | ||
486 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
487 | flush_altivec_to_thread(target); | |
488 | flush_tmregs_to_thread(target); | |
489 | for (i = 0; i < 32 ; i++) | |
490 | target->thread.TS_TRANS_FPR(i) = buf[i]; | |
491 | target->thread.transact_fp.fpscr = buf[32]; | |
492 | } else { | |
493 | for (i = 0; i < 32 ; i++) | |
494 | target->thread.TS_FPR(i) = buf[i]; | |
495 | target->thread.fp_state.fpscr = buf[32]; | |
496 | } | |
497 | return 0; | |
498 | #endif | |
499 | ||
500 | #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
c6e6771b MN |
501 | /* copy to local buffer then write that out */ |
502 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
503 | if (i) | |
504 | return i; | |
505 | for (i = 0; i < 32 ; i++) | |
506 | target->thread.TS_FPR(i) = buf[i]; | |
de79f7b9 | 507 | target->thread.fp_state.fpscr = buf[32]; |
c6e6771b | 508 | return 0; |
1ec8549d AK |
509 | #endif |
510 | ||
511 | #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
de79f7b9 | 512 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 513 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
514 | |
515 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 516 | &target->thread.fp_state, 0, -1); |
c6e6771b | 517 | #endif |
f65255e8 RM |
518 | } |
519 | ||
865418d8 BH |
520 | #ifdef CONFIG_ALTIVEC |
521 | /* | |
522 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. | |
523 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
524 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
525 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
526 | * vrsave as the first word (offset 0) within the quadword. | |
527 | * | |
528 | * This definition of the VMX state is compatible with the current PPC32 | |
529 | * ptrace interface. This allows signal handling and ptrace to use the | |
530 | * same structures. This also simplifies the implementation of a bi-arch | |
531 | * (combined (32- and 64-bit) gdb. | |
532 | */ | |
533 | ||
3caf06c6 RM |
534 | static int vr_active(struct task_struct *target, |
535 | const struct user_regset *regset) | |
536 | { | |
537 | flush_altivec_to_thread(target); | |
538 | return target->thread.used_vr ? regset->n : 0; | |
539 | } | |
540 | ||
d844e279 AK |
541 | /* |
542 | * When the transaction is active, 'transact_vr' holds the current running | |
543 | * value of all the VMX registers and 'vr_state' holds the last checkpointed | |
544 | * value of all the VMX registers for the current transaction to fall back | |
545 | * on in case it aborts. When transaction is not active 'vr_state' holds | |
546 | * the current running state of all the VMX registers. So this function which | |
547 | * gets the current running values of all the VMX registers, needs to know | |
548 | * whether any transaction is active or not. | |
549 | * | |
550 | * Userspace interface buffer layout: | |
551 | * | |
552 | * struct data { | |
553 | * vector128 vr[32]; | |
554 | * vector128 vscr; | |
555 | * vector128 vrsave; | |
556 | * }; | |
557 | */ | |
3caf06c6 RM |
558 | static int vr_get(struct task_struct *target, const struct user_regset *regset, |
559 | unsigned int pos, unsigned int count, | |
560 | void *kbuf, void __user *ubuf) | |
561 | { | |
d844e279 | 562 | struct thread_vr_state *addr; |
3caf06c6 RM |
563 | int ret; |
564 | ||
565 | flush_altivec_to_thread(target); | |
566 | ||
de79f7b9 PM |
567 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
568 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 | 569 | |
d844e279 AK |
570 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
571 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
572 | flush_fp_to_thread(target); | |
573 | flush_tmregs_to_thread(target); | |
574 | addr = &target->thread.transact_vr; | |
575 | } else { | |
576 | addr = &target->thread.vr_state; | |
577 | } | |
578 | #else | |
579 | addr = &target->thread.vr_state; | |
580 | #endif | |
3caf06c6 | 581 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
d844e279 | 582 | addr, 0, |
3caf06c6 RM |
583 | 33 * sizeof(vector128)); |
584 | if (!ret) { | |
585 | /* | |
586 | * Copy out only the low-order word of vrsave. | |
587 | */ | |
588 | union { | |
589 | elf_vrreg_t reg; | |
590 | u32 word; | |
591 | } vrsave; | |
592 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 AK |
593 | |
594 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
595 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
596 | vrsave.word = target->thread.transact_vrsave; | |
597 | else | |
598 | vrsave.word = target->thread.vrsave; | |
599 | #else | |
3caf06c6 | 600 | vrsave.word = target->thread.vrsave; |
d844e279 AK |
601 | #endif |
602 | ||
3caf06c6 RM |
603 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, |
604 | 33 * sizeof(vector128), -1); | |
605 | } | |
606 | ||
607 | return ret; | |
608 | } | |
609 | ||
d844e279 AK |
610 | /* |
611 | * When the transaction is active, 'transact_vr' holds the current running | |
612 | * value of all the VMX registers and 'vr_state' holds the last checkpointed | |
613 | * value of all the VMX registers for the current transaction to fall back | |
614 | * on in case it aborts. When transaction is not active 'vr_state' holds | |
615 | * the current running state of all the VMX registers. So this function which | |
616 | * sets the current running values of all the VMX registers, needs to know | |
617 | * whether any transaction is active or not. | |
618 | * | |
619 | * Userspace interface buffer layout: | |
620 | * | |
621 | * struct data { | |
622 | * vector128 vr[32]; | |
623 | * vector128 vscr; | |
624 | * vector128 vrsave; | |
625 | * }; | |
626 | */ | |
3caf06c6 RM |
627 | static int vr_set(struct task_struct *target, const struct user_regset *regset, |
628 | unsigned int pos, unsigned int count, | |
629 | const void *kbuf, const void __user *ubuf) | |
630 | { | |
d844e279 | 631 | struct thread_vr_state *addr; |
3caf06c6 RM |
632 | int ret; |
633 | ||
634 | flush_altivec_to_thread(target); | |
635 | ||
de79f7b9 PM |
636 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
637 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 | 638 | |
d844e279 AK |
639 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
640 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
641 | flush_fp_to_thread(target); | |
642 | flush_tmregs_to_thread(target); | |
643 | addr = &target->thread.transact_vr; | |
644 | } else { | |
645 | addr = &target->thread.vr_state; | |
646 | } | |
647 | #else | |
648 | addr = &target->thread.vr_state; | |
649 | #endif | |
3caf06c6 | 650 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
d844e279 | 651 | addr, 0, |
de79f7b9 | 652 | 33 * sizeof(vector128)); |
3caf06c6 RM |
653 | if (!ret && count > 0) { |
654 | /* | |
655 | * We use only the first word of vrsave. | |
656 | */ | |
657 | union { | |
658 | elf_vrreg_t reg; | |
659 | u32 word; | |
660 | } vrsave; | |
661 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 AK |
662 | |
663 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
664 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
665 | vrsave.word = target->thread.transact_vrsave; | |
666 | else | |
667 | vrsave.word = target->thread.vrsave; | |
668 | #else | |
3caf06c6 | 669 | vrsave.word = target->thread.vrsave; |
d844e279 | 670 | #endif |
3caf06c6 RM |
671 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, |
672 | 33 * sizeof(vector128), -1); | |
d844e279 AK |
673 | if (!ret) { |
674 | ||
675 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
676 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
677 | target->thread.transact_vrsave = vrsave.word; | |
678 | else | |
679 | target->thread.vrsave = vrsave.word; | |
680 | #else | |
3caf06c6 | 681 | target->thread.vrsave = vrsave.word; |
d844e279 AK |
682 | #endif |
683 | } | |
3caf06c6 RM |
684 | } |
685 | ||
686 | return ret; | |
687 | } | |
865418d8 BH |
688 | #endif /* CONFIG_ALTIVEC */ |
689 | ||
ce48b210 MN |
690 | #ifdef CONFIG_VSX |
691 | /* | |
692 | * Currently to set and and get all the vsx state, you need to call | |
25985edc | 693 | * the fp and VMX calls as well. This only get/sets the lower 32 |
ce48b210 MN |
694 | * 128bit VSX registers. |
695 | */ | |
696 | ||
697 | static int vsr_active(struct task_struct *target, | |
698 | const struct user_regset *regset) | |
699 | { | |
700 | flush_vsx_to_thread(target); | |
701 | return target->thread.used_vsr ? regset->n : 0; | |
702 | } | |
703 | ||
94b7d361 AK |
704 | /* |
705 | * When the transaction is active, 'transact_fp' holds the current running | |
706 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
707 | * value of all FPR registers for the current transaction. When transaction | |
708 | * is not active 'fp_state' holds the current running state of all the FPR | |
709 | * registers. So this function which returns the current running values of | |
710 | * all the FPR registers, needs to know whether any transaction is active | |
711 | * or not. | |
712 | * | |
713 | * Userspace interface buffer layout: | |
714 | * | |
715 | * struct data { | |
716 | * u64 vsx[32]; | |
717 | * }; | |
718 | */ | |
ce48b210 MN |
719 | static int vsr_get(struct task_struct *target, const struct user_regset *regset, |
720 | unsigned int pos, unsigned int count, | |
721 | void *kbuf, void __user *ubuf) | |
722 | { | |
de79f7b9 | 723 | u64 buf[32]; |
f3e909c2 | 724 | int ret, i; |
ce48b210 | 725 | |
94b7d361 AK |
726 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
727 | flush_fp_to_thread(target); | |
728 | flush_altivec_to_thread(target); | |
729 | flush_tmregs_to_thread(target); | |
730 | #endif | |
ce48b210 MN |
731 | flush_vsx_to_thread(target); |
732 | ||
94b7d361 AK |
733 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
734 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
735 | for (i = 0; i < 32 ; i++) | |
736 | buf[i] = target->thread. | |
737 | transact_fp.fpr[i][TS_VSRLOWOFFSET]; | |
738 | } else { | |
739 | for (i = 0; i < 32 ; i++) | |
740 | buf[i] = target->thread. | |
741 | fp_state.fpr[i][TS_VSRLOWOFFSET]; | |
742 | } | |
743 | #else | |
f3e909c2 | 744 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 745 | buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET]; |
94b7d361 | 746 | #endif |
ce48b210 | 747 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
f3e909c2 | 748 | buf, 0, 32 * sizeof(double)); |
ce48b210 MN |
749 | |
750 | return ret; | |
751 | } | |
752 | ||
94b7d361 AK |
753 | /* |
754 | * When the transaction is active, 'transact_fp' holds the current running | |
755 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
756 | * value of all FPR registers for the current transaction. When transaction | |
757 | * is not active 'fp_state' holds the current running state of all the FPR | |
758 | * registers. So this function which sets the current running values of all | |
759 | * the FPR registers, needs to know whether any transaction is active or not. | |
760 | * | |
761 | * Userspace interface buffer layout: | |
762 | * | |
763 | * struct data { | |
764 | * u64 vsx[32]; | |
765 | * }; | |
766 | */ | |
ce48b210 MN |
767 | static int vsr_set(struct task_struct *target, const struct user_regset *regset, |
768 | unsigned int pos, unsigned int count, | |
769 | const void *kbuf, const void __user *ubuf) | |
770 | { | |
de79f7b9 | 771 | u64 buf[32]; |
f3e909c2 | 772 | int ret,i; |
ce48b210 | 773 | |
94b7d361 AK |
774 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
775 | flush_fp_to_thread(target); | |
776 | flush_altivec_to_thread(target); | |
777 | flush_tmregs_to_thread(target); | |
778 | #endif | |
ce48b210 MN |
779 | flush_vsx_to_thread(target); |
780 | ||
781 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
f3e909c2 | 782 | buf, 0, 32 * sizeof(double)); |
94b7d361 AK |
783 | |
784 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
785 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
786 | for (i = 0; i < 32 ; i++) | |
787 | target->thread.transact_fp. | |
788 | fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
789 | } else { | |
790 | for (i = 0; i < 32 ; i++) | |
791 | target->thread.fp_state. | |
792 | fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
793 | } | |
794 | #else | |
f3e909c2 | 795 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 796 | target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; |
94b7d361 | 797 | #endif |
f3e909c2 | 798 | |
ce48b210 MN |
799 | |
800 | return ret; | |
801 | } | |
802 | #endif /* CONFIG_VSX */ | |
803 | ||
865418d8 BH |
804 | #ifdef CONFIG_SPE |
805 | ||
806 | /* | |
807 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
808 | * | |
809 | * struct { | |
810 | * u32 evr[32]; | |
811 | * u64 acc; | |
812 | * u32 spefscr; | |
813 | * } | |
814 | */ | |
815 | ||
a4e4b175 RM |
816 | static int evr_active(struct task_struct *target, |
817 | const struct user_regset *regset) | |
865418d8 | 818 | { |
a4e4b175 RM |
819 | flush_spe_to_thread(target); |
820 | return target->thread.used_spe ? regset->n : 0; | |
821 | } | |
865418d8 | 822 | |
a4e4b175 RM |
823 | static int evr_get(struct task_struct *target, const struct user_regset *regset, |
824 | unsigned int pos, unsigned int count, | |
825 | void *kbuf, void __user *ubuf) | |
826 | { | |
827 | int ret; | |
865418d8 | 828 | |
a4e4b175 | 829 | flush_spe_to_thread(target); |
865418d8 | 830 | |
a4e4b175 RM |
831 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
832 | &target->thread.evr, | |
833 | 0, sizeof(target->thread.evr)); | |
865418d8 | 834 | |
a4e4b175 RM |
835 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
836 | offsetof(struct thread_struct, spefscr)); | |
837 | ||
838 | if (!ret) | |
839 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
840 | &target->thread.acc, | |
841 | sizeof(target->thread.evr), -1); | |
842 | ||
843 | return ret; | |
844 | } | |
845 | ||
846 | static int evr_set(struct task_struct *target, const struct user_regset *regset, | |
847 | unsigned int pos, unsigned int count, | |
848 | const void *kbuf, const void __user *ubuf) | |
849 | { | |
850 | int ret; | |
851 | ||
852 | flush_spe_to_thread(target); | |
853 | ||
854 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
855 | &target->thread.evr, | |
856 | 0, sizeof(target->thread.evr)); | |
865418d8 | 857 | |
a4e4b175 RM |
858 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
859 | offsetof(struct thread_struct, spefscr)); | |
860 | ||
861 | if (!ret) | |
862 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
863 | &target->thread.acc, | |
864 | sizeof(target->thread.evr), -1); | |
865 | ||
866 | return ret; | |
865418d8 | 867 | } |
865418d8 BH |
868 | #endif /* CONFIG_SPE */ |
869 | ||
25847fb1 AK |
870 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
871 | /** | |
872 | * tm_cgpr_active - get active number of registers in CGPR | |
873 | * @target: The target task. | |
874 | * @regset: The user regset structure. | |
875 | * | |
876 | * This function checks for the active number of available | |
877 | * regisers in transaction checkpointed GPR category. | |
878 | */ | |
879 | static int tm_cgpr_active(struct task_struct *target, | |
880 | const struct user_regset *regset) | |
881 | { | |
882 | if (!cpu_has_feature(CPU_FTR_TM)) | |
883 | return -ENODEV; | |
884 | ||
885 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
886 | return 0; | |
887 | ||
888 | return regset->n; | |
889 | } | |
890 | ||
891 | /** | |
892 | * tm_cgpr_get - get CGPR registers | |
893 | * @target: The target task. | |
894 | * @regset: The user regset structure. | |
895 | * @pos: The buffer position. | |
896 | * @count: Number of bytes to copy. | |
897 | * @kbuf: Kernel buffer to copy from. | |
898 | * @ubuf: User buffer to copy into. | |
899 | * | |
900 | * This function gets transaction checkpointed GPR registers. | |
901 | * | |
902 | * When the transaction is active, 'ckpt_regs' holds all the checkpointed | |
903 | * GPR register values for the current transaction to fall back on if it | |
904 | * aborts in between. This function gets those checkpointed GPR registers. | |
905 | * The userspace interface buffer layout is as follows. | |
906 | * | |
907 | * struct data { | |
908 | * struct pt_regs ckpt_regs; | |
909 | * }; | |
910 | */ | |
911 | static int tm_cgpr_get(struct task_struct *target, | |
912 | const struct user_regset *regset, | |
913 | unsigned int pos, unsigned int count, | |
914 | void *kbuf, void __user *ubuf) | |
915 | { | |
916 | int ret; | |
917 | ||
918 | if (!cpu_has_feature(CPU_FTR_TM)) | |
919 | return -ENODEV; | |
920 | ||
921 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
922 | return -ENODATA; | |
923 | ||
924 | flush_fp_to_thread(target); | |
925 | flush_altivec_to_thread(target); | |
926 | flush_tmregs_to_thread(target); | |
927 | ||
928 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
929 | &target->thread.ckpt_regs, | |
930 | 0, offsetof(struct pt_regs, msr)); | |
931 | if (!ret) { | |
932 | unsigned long msr = get_user_ckpt_msr(target); | |
933 | ||
934 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
935 | offsetof(struct pt_regs, msr), | |
936 | offsetof(struct pt_regs, msr) + | |
937 | sizeof(msr)); | |
938 | } | |
939 | ||
940 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
941 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
942 | ||
943 | if (!ret) | |
944 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
945 | &target->thread.ckpt_regs.orig_gpr3, | |
946 | offsetof(struct pt_regs, orig_gpr3), | |
947 | sizeof(struct pt_regs)); | |
948 | if (!ret) | |
949 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
950 | sizeof(struct pt_regs), -1); | |
951 | ||
952 | return ret; | |
953 | } | |
954 | ||
955 | /* | |
956 | * tm_cgpr_set - set the CGPR registers | |
957 | * @target: The target task. | |
958 | * @regset: The user regset structure. | |
959 | * @pos: The buffer position. | |
960 | * @count: Number of bytes to copy. | |
961 | * @kbuf: Kernel buffer to copy into. | |
962 | * @ubuf: User buffer to copy from. | |
963 | * | |
964 | * This function sets in transaction checkpointed GPR registers. | |
965 | * | |
966 | * When the transaction is active, 'ckpt_regs' holds the checkpointed | |
967 | * GPR register values for the current transaction to fall back on if it | |
968 | * aborts in between. This function sets those checkpointed GPR registers. | |
969 | * The userspace interface buffer layout is as follows. | |
970 | * | |
971 | * struct data { | |
972 | * struct pt_regs ckpt_regs; | |
973 | * }; | |
974 | */ | |
975 | static int tm_cgpr_set(struct task_struct *target, | |
976 | const struct user_regset *regset, | |
977 | unsigned int pos, unsigned int count, | |
978 | const void *kbuf, const void __user *ubuf) | |
979 | { | |
980 | unsigned long reg; | |
981 | int ret; | |
982 | ||
983 | if (!cpu_has_feature(CPU_FTR_TM)) | |
984 | return -ENODEV; | |
985 | ||
986 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
987 | return -ENODATA; | |
988 | ||
989 | flush_fp_to_thread(target); | |
990 | flush_altivec_to_thread(target); | |
991 | flush_tmregs_to_thread(target); | |
992 | ||
993 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
994 | &target->thread.ckpt_regs, | |
995 | 0, PT_MSR * sizeof(reg)); | |
996 | ||
997 | if (!ret && count > 0) { | |
998 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
999 | PT_MSR * sizeof(reg), | |
1000 | (PT_MSR + 1) * sizeof(reg)); | |
1001 | if (!ret) | |
1002 | ret = set_user_ckpt_msr(target, reg); | |
1003 | } | |
1004 | ||
1005 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
1006 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
1007 | ||
1008 | if (!ret) | |
1009 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1010 | &target->thread.ckpt_regs.orig_gpr3, | |
1011 | PT_ORIG_R3 * sizeof(reg), | |
1012 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
1013 | ||
1014 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
1015 | ret = user_regset_copyin_ignore( | |
1016 | &pos, &count, &kbuf, &ubuf, | |
1017 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
1018 | PT_TRAP * sizeof(reg)); | |
1019 | ||
1020 | if (!ret && count > 0) { | |
1021 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
1022 | PT_TRAP * sizeof(reg), | |
1023 | (PT_TRAP + 1) * sizeof(reg)); | |
1024 | if (!ret) | |
1025 | ret = set_user_ckpt_trap(target, reg); | |
1026 | } | |
1027 | ||
1028 | if (!ret) | |
1029 | ret = user_regset_copyin_ignore( | |
1030 | &pos, &count, &kbuf, &ubuf, | |
1031 | (PT_TRAP + 1) * sizeof(reg), -1); | |
1032 | ||
1033 | return ret; | |
1034 | } | |
19cbcbf7 AK |
1035 | |
1036 | /** | |
1037 | * tm_cfpr_active - get active number of registers in CFPR | |
1038 | * @target: The target task. | |
1039 | * @regset: The user regset structure. | |
1040 | * | |
1041 | * This function checks for the active number of available | |
1042 | * regisers in transaction checkpointed FPR category. | |
1043 | */ | |
1044 | static int tm_cfpr_active(struct task_struct *target, | |
1045 | const struct user_regset *regset) | |
1046 | { | |
1047 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1048 | return -ENODEV; | |
1049 | ||
1050 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1051 | return 0; | |
1052 | ||
1053 | return regset->n; | |
1054 | } | |
1055 | ||
1056 | /** | |
1057 | * tm_cfpr_get - get CFPR registers | |
1058 | * @target: The target task. | |
1059 | * @regset: The user regset structure. | |
1060 | * @pos: The buffer position. | |
1061 | * @count: Number of bytes to copy. | |
1062 | * @kbuf: Kernel buffer to copy from. | |
1063 | * @ubuf: User buffer to copy into. | |
1064 | * | |
1065 | * This function gets in transaction checkpointed FPR registers. | |
1066 | * | |
1067 | * When the transaction is active 'fp_state' holds the checkpointed | |
1068 | * values for the current transaction to fall back on if it aborts | |
1069 | * in between. This function gets those checkpointed FPR registers. | |
1070 | * The userspace interface buffer layout is as follows. | |
1071 | * | |
1072 | * struct data { | |
1073 | * u64 fpr[32]; | |
1074 | * u64 fpscr; | |
1075 | *}; | |
1076 | */ | |
1077 | static int tm_cfpr_get(struct task_struct *target, | |
1078 | const struct user_regset *regset, | |
1079 | unsigned int pos, unsigned int count, | |
1080 | void *kbuf, void __user *ubuf) | |
1081 | { | |
1082 | u64 buf[33]; | |
1083 | int i; | |
1084 | ||
1085 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1086 | return -ENODEV; | |
1087 | ||
1088 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1089 | return -ENODATA; | |
1090 | ||
1091 | flush_fp_to_thread(target); | |
1092 | flush_altivec_to_thread(target); | |
1093 | flush_tmregs_to_thread(target); | |
1094 | ||
1095 | /* copy to local buffer then write that out */ | |
1096 | for (i = 0; i < 32 ; i++) | |
1097 | buf[i] = target->thread.TS_FPR(i); | |
1098 | buf[32] = target->thread.fp_state.fpscr; | |
1099 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
1100 | } | |
1101 | ||
1102 | /** | |
1103 | * tm_cfpr_set - set CFPR registers | |
1104 | * @target: The target task. | |
1105 | * @regset: The user regset structure. | |
1106 | * @pos: The buffer position. | |
1107 | * @count: Number of bytes to copy. | |
1108 | * @kbuf: Kernel buffer to copy into. | |
1109 | * @ubuf: User buffer to copy from. | |
1110 | * | |
1111 | * This function sets in transaction checkpointed FPR registers. | |
1112 | * | |
1113 | * When the transaction is active 'fp_state' holds the checkpointed | |
1114 | * FPR register values for the current transaction to fall back on | |
1115 | * if it aborts in between. This function sets these checkpointed | |
1116 | * FPR registers. The userspace interface buffer layout is as follows. | |
1117 | * | |
1118 | * struct data { | |
1119 | * u64 fpr[32]; | |
1120 | * u64 fpscr; | |
1121 | *}; | |
1122 | */ | |
1123 | static int tm_cfpr_set(struct task_struct *target, | |
1124 | const struct user_regset *regset, | |
1125 | unsigned int pos, unsigned int count, | |
1126 | const void *kbuf, const void __user *ubuf) | |
1127 | { | |
1128 | u64 buf[33]; | |
1129 | int i; | |
1130 | ||
1131 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1132 | return -ENODEV; | |
1133 | ||
1134 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1135 | return -ENODATA; | |
1136 | ||
1137 | flush_fp_to_thread(target); | |
1138 | flush_altivec_to_thread(target); | |
1139 | flush_tmregs_to_thread(target); | |
1140 | ||
1141 | /* copy to local buffer then write that out */ | |
1142 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
1143 | if (i) | |
1144 | return i; | |
1145 | for (i = 0; i < 32 ; i++) | |
1146 | target->thread.TS_FPR(i) = buf[i]; | |
1147 | target->thread.fp_state.fpscr = buf[32]; | |
1148 | return 0; | |
1149 | } | |
25847fb1 | 1150 | #endif |
865418d8 | 1151 | |
80fdf470 RM |
1152 | /* |
1153 | * These are our native regset flavors. | |
1154 | */ | |
1155 | enum powerpc_regset { | |
1156 | REGSET_GPR, | |
1157 | REGSET_FPR, | |
1158 | #ifdef CONFIG_ALTIVEC | |
1159 | REGSET_VMX, | |
1160 | #endif | |
ce48b210 MN |
1161 | #ifdef CONFIG_VSX |
1162 | REGSET_VSX, | |
1163 | #endif | |
80fdf470 RM |
1164 | #ifdef CONFIG_SPE |
1165 | REGSET_SPE, | |
1166 | #endif | |
25847fb1 AK |
1167 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1168 | REGSET_TM_CGPR, /* TM checkpointed GPR registers */ | |
19cbcbf7 | 1169 | REGSET_TM_CFPR, /* TM checkpointed FPR registers */ |
25847fb1 | 1170 | #endif |
80fdf470 RM |
1171 | }; |
1172 | ||
1173 | static const struct user_regset native_regsets[] = { | |
1174 | [REGSET_GPR] = { | |
1175 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
1176 | .size = sizeof(long), .align = sizeof(long), | |
1177 | .get = gpr_get, .set = gpr_set | |
1178 | }, | |
1179 | [REGSET_FPR] = { | |
1180 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
1181 | .size = sizeof(double), .align = sizeof(double), | |
1182 | .get = fpr_get, .set = fpr_set | |
1183 | }, | |
1184 | #ifdef CONFIG_ALTIVEC | |
1185 | [REGSET_VMX] = { | |
1186 | .core_note_type = NT_PPC_VMX, .n = 34, | |
1187 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1188 | .active = vr_active, .get = vr_get, .set = vr_set | |
1189 | }, | |
1190 | #endif | |
ce48b210 MN |
1191 | #ifdef CONFIG_VSX |
1192 | [REGSET_VSX] = { | |
f3e909c2 MN |
1193 | .core_note_type = NT_PPC_VSX, .n = 32, |
1194 | .size = sizeof(double), .align = sizeof(double), | |
ce48b210 MN |
1195 | .active = vsr_active, .get = vsr_get, .set = vsr_set |
1196 | }, | |
1197 | #endif | |
80fdf470 RM |
1198 | #ifdef CONFIG_SPE |
1199 | [REGSET_SPE] = { | |
a0b38b4e | 1200 | .core_note_type = NT_PPC_SPE, .n = 35, |
80fdf470 RM |
1201 | .size = sizeof(u32), .align = sizeof(u32), |
1202 | .active = evr_active, .get = evr_get, .set = evr_set | |
1203 | }, | |
1204 | #endif | |
25847fb1 AK |
1205 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1206 | [REGSET_TM_CGPR] = { | |
1207 | .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG, | |
1208 | .size = sizeof(long), .align = sizeof(long), | |
1209 | .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set | |
1210 | }, | |
19cbcbf7 AK |
1211 | [REGSET_TM_CFPR] = { |
1212 | .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG, | |
1213 | .size = sizeof(double), .align = sizeof(double), | |
1214 | .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set | |
1215 | }, | |
25847fb1 | 1216 | #endif |
80fdf470 RM |
1217 | }; |
1218 | ||
1219 | static const struct user_regset_view user_ppc_native_view = { | |
1220 | .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, | |
1221 | .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets) | |
1222 | }; | |
1223 | ||
fa8f5cb0 RM |
1224 | #ifdef CONFIG_PPC64 |
1225 | #include <linux/compat.h> | |
1226 | ||
04fcadce | 1227 | static int gpr32_get_common(struct task_struct *target, |
fa8f5cb0 RM |
1228 | const struct user_regset *regset, |
1229 | unsigned int pos, unsigned int count, | |
04fcadce | 1230 | void *kbuf, void __user *ubuf, bool tm_active) |
fa8f5cb0 RM |
1231 | { |
1232 | const unsigned long *regs = &target->thread.regs->gpr[0]; | |
04fcadce | 1233 | const unsigned long *ckpt_regs; |
fa8f5cb0 RM |
1234 | compat_ulong_t *k = kbuf; |
1235 | compat_ulong_t __user *u = ubuf; | |
1236 | compat_ulong_t reg; | |
a71f5d5d | 1237 | int i; |
fa8f5cb0 | 1238 | |
04fcadce AK |
1239 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1240 | ckpt_regs = &target->thread.ckpt_regs.gpr[0]; | |
1241 | #endif | |
1242 | if (tm_active) { | |
1243 | regs = ckpt_regs; | |
1244 | } else { | |
1245 | if (target->thread.regs == NULL) | |
1246 | return -EIO; | |
1247 | ||
1248 | if (!FULL_REGS(target->thread.regs)) { | |
1249 | /* | |
1250 | * We have a partial register set. | |
1251 | * Fill 14-31 with bogus values. | |
1252 | */ | |
1253 | for (i = 14; i < 32; i++) | |
1254 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
1255 | } | |
a71f5d5d | 1256 | } |
fa8f5cb0 RM |
1257 | |
1258 | pos /= sizeof(reg); | |
1259 | count /= sizeof(reg); | |
1260 | ||
1261 | if (kbuf) | |
1262 | for (; count > 0 && pos < PT_MSR; --count) | |
1263 | *k++ = regs[pos++]; | |
1264 | else | |
1265 | for (; count > 0 && pos < PT_MSR; --count) | |
1266 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
1267 | return -EFAULT; | |
1268 | ||
1269 | if (count > 0 && pos == PT_MSR) { | |
1270 | reg = get_user_msr(target); | |
1271 | if (kbuf) | |
1272 | *k++ = reg; | |
1273 | else if (__put_user(reg, u++)) | |
1274 | return -EFAULT; | |
1275 | ++pos; | |
1276 | --count; | |
1277 | } | |
1278 | ||
1279 | if (kbuf) | |
1280 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
1281 | *k++ = regs[pos++]; | |
1282 | else | |
1283 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
1284 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
1285 | return -EFAULT; | |
1286 | ||
1287 | kbuf = k; | |
1288 | ubuf = u; | |
1289 | pos *= sizeof(reg); | |
1290 | count *= sizeof(reg); | |
1291 | return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
1292 | PT_REGS_COUNT * sizeof(reg), -1); | |
1293 | } | |
1294 | ||
04fcadce | 1295 | static int gpr32_set_common(struct task_struct *target, |
fa8f5cb0 RM |
1296 | const struct user_regset *regset, |
1297 | unsigned int pos, unsigned int count, | |
04fcadce | 1298 | const void *kbuf, const void __user *ubuf, bool tm_active) |
fa8f5cb0 RM |
1299 | { |
1300 | unsigned long *regs = &target->thread.regs->gpr[0]; | |
04fcadce | 1301 | unsigned long *ckpt_regs; |
fa8f5cb0 RM |
1302 | const compat_ulong_t *k = kbuf; |
1303 | const compat_ulong_t __user *u = ubuf; | |
1304 | compat_ulong_t reg; | |
1305 | ||
04fcadce AK |
1306 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1307 | ckpt_regs = &target->thread.ckpt_regs.gpr[0]; | |
1308 | #endif | |
fa8f5cb0 | 1309 | |
04fcadce AK |
1310 | if (tm_active) { |
1311 | regs = ckpt_regs; | |
1312 | } else { | |
1313 | regs = &target->thread.regs->gpr[0]; | |
1314 | ||
1315 | if (target->thread.regs == NULL) | |
1316 | return -EIO; | |
1317 | ||
1318 | CHECK_FULL_REGS(target->thread.regs); | |
1319 | } | |
fa8f5cb0 RM |
1320 | |
1321 | pos /= sizeof(reg); | |
1322 | count /= sizeof(reg); | |
1323 | ||
1324 | if (kbuf) | |
1325 | for (; count > 0 && pos < PT_MSR; --count) | |
1326 | regs[pos++] = *k++; | |
1327 | else | |
1328 | for (; count > 0 && pos < PT_MSR; --count) { | |
1329 | if (__get_user(reg, u++)) | |
1330 | return -EFAULT; | |
1331 | regs[pos++] = reg; | |
1332 | } | |
1333 | ||
1334 | ||
1335 | if (count > 0 && pos == PT_MSR) { | |
1336 | if (kbuf) | |
1337 | reg = *k++; | |
1338 | else if (__get_user(reg, u++)) | |
1339 | return -EFAULT; | |
1340 | set_user_msr(target, reg); | |
1341 | ++pos; | |
1342 | --count; | |
1343 | } | |
1344 | ||
c2372eb9 | 1345 | if (kbuf) { |
fa8f5cb0 RM |
1346 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) |
1347 | regs[pos++] = *k++; | |
c2372eb9 RM |
1348 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
1349 | ++k; | |
1350 | } else { | |
fa8f5cb0 RM |
1351 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) { |
1352 | if (__get_user(reg, u++)) | |
1353 | return -EFAULT; | |
1354 | regs[pos++] = reg; | |
1355 | } | |
c2372eb9 RM |
1356 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
1357 | if (__get_user(reg, u++)) | |
1358 | return -EFAULT; | |
1359 | } | |
fa8f5cb0 RM |
1360 | |
1361 | if (count > 0 && pos == PT_TRAP) { | |
1362 | if (kbuf) | |
1363 | reg = *k++; | |
1364 | else if (__get_user(reg, u++)) | |
1365 | return -EFAULT; | |
1366 | set_user_trap(target, reg); | |
1367 | ++pos; | |
1368 | --count; | |
1369 | } | |
1370 | ||
1371 | kbuf = k; | |
1372 | ubuf = u; | |
1373 | pos *= sizeof(reg); | |
1374 | count *= sizeof(reg); | |
1375 | return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, | |
1376 | (PT_TRAP + 1) * sizeof(reg), -1); | |
1377 | } | |
1378 | ||
25847fb1 AK |
1379 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1380 | static int tm_cgpr32_get(struct task_struct *target, | |
1381 | const struct user_regset *regset, | |
1382 | unsigned int pos, unsigned int count, | |
1383 | void *kbuf, void __user *ubuf) | |
1384 | { | |
1385 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 1); | |
1386 | } | |
1387 | ||
1388 | static int tm_cgpr32_set(struct task_struct *target, | |
1389 | const struct user_regset *regset, | |
1390 | unsigned int pos, unsigned int count, | |
1391 | const void *kbuf, const void __user *ubuf) | |
1392 | { | |
1393 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 1); | |
1394 | } | |
1395 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
1396 | ||
04fcadce AK |
1397 | static int gpr32_get(struct task_struct *target, |
1398 | const struct user_regset *regset, | |
1399 | unsigned int pos, unsigned int count, | |
1400 | void *kbuf, void __user *ubuf) | |
1401 | { | |
1402 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 0); | |
1403 | } | |
1404 | ||
1405 | static int gpr32_set(struct task_struct *target, | |
1406 | const struct user_regset *regset, | |
1407 | unsigned int pos, unsigned int count, | |
1408 | const void *kbuf, const void __user *ubuf) | |
1409 | { | |
1410 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 0); | |
1411 | } | |
1412 | ||
fa8f5cb0 RM |
1413 | /* |
1414 | * These are the regset flavors matching the CONFIG_PPC32 native set. | |
1415 | */ | |
1416 | static const struct user_regset compat_regsets[] = { | |
1417 | [REGSET_GPR] = { | |
1418 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
1419 | .size = sizeof(compat_long_t), .align = sizeof(compat_long_t), | |
1420 | .get = gpr32_get, .set = gpr32_set | |
1421 | }, | |
1422 | [REGSET_FPR] = { | |
1423 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
1424 | .size = sizeof(double), .align = sizeof(double), | |
1425 | .get = fpr_get, .set = fpr_set | |
1426 | }, | |
1427 | #ifdef CONFIG_ALTIVEC | |
1428 | [REGSET_VMX] = { | |
1429 | .core_note_type = NT_PPC_VMX, .n = 34, | |
1430 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1431 | .active = vr_active, .get = vr_get, .set = vr_set | |
1432 | }, | |
1433 | #endif | |
1434 | #ifdef CONFIG_SPE | |
1435 | [REGSET_SPE] = { | |
24f1a849 | 1436 | .core_note_type = NT_PPC_SPE, .n = 35, |
fa8f5cb0 RM |
1437 | .size = sizeof(u32), .align = sizeof(u32), |
1438 | .active = evr_active, .get = evr_get, .set = evr_set | |
1439 | }, | |
1440 | #endif | |
25847fb1 AK |
1441 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1442 | [REGSET_TM_CGPR] = { | |
1443 | .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG, | |
1444 | .size = sizeof(long), .align = sizeof(long), | |
1445 | .active = tm_cgpr_active, | |
1446 | .get = tm_cgpr32_get, .set = tm_cgpr32_set | |
1447 | }, | |
19cbcbf7 AK |
1448 | [REGSET_TM_CFPR] = { |
1449 | .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG, | |
1450 | .size = sizeof(double), .align = sizeof(double), | |
1451 | .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set | |
1452 | }, | |
25847fb1 | 1453 | #endif |
fa8f5cb0 RM |
1454 | }; |
1455 | ||
1456 | static const struct user_regset_view user_ppc_compat_view = { | |
1457 | .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI, | |
1458 | .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets) | |
1459 | }; | |
1460 | #endif /* CONFIG_PPC64 */ | |
1461 | ||
80fdf470 RM |
1462 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) |
1463 | { | |
fa8f5cb0 RM |
1464 | #ifdef CONFIG_PPC64 |
1465 | if (test_tsk_thread_flag(task, TIF_32BIT)) | |
1466 | return &user_ppc_compat_view; | |
1467 | #endif | |
80fdf470 RM |
1468 | return &user_ppc_native_view; |
1469 | } | |
1470 | ||
1471 | ||
2a84b0d7 | 1472 | void user_enable_single_step(struct task_struct *task) |
865418d8 BH |
1473 | { |
1474 | struct pt_regs *regs = task->thread.regs; | |
1475 | ||
1476 | if (regs != NULL) { | |
172ae2e7 | 1477 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
1478 | task->thread.debug.dbcr0 &= ~DBCR0_BT; |
1479 | task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
865418d8 BH |
1480 | regs->msr |= MSR_DE; |
1481 | #else | |
ec097c84 | 1482 | regs->msr &= ~MSR_BE; |
865418d8 BH |
1483 | regs->msr |= MSR_SE; |
1484 | #endif | |
1485 | } | |
1486 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1487 | } | |
1488 | ||
ec097c84 RM |
1489 | void user_enable_block_step(struct task_struct *task) |
1490 | { | |
1491 | struct pt_regs *regs = task->thread.regs; | |
1492 | ||
1493 | if (regs != NULL) { | |
172ae2e7 | 1494 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
1495 | task->thread.debug.dbcr0 &= ~DBCR0_IC; |
1496 | task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; | |
ec097c84 RM |
1497 | regs->msr |= MSR_DE; |
1498 | #else | |
1499 | regs->msr &= ~MSR_SE; | |
1500 | regs->msr |= MSR_BE; | |
1501 | #endif | |
1502 | } | |
1503 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1504 | } | |
1505 | ||
2a84b0d7 | 1506 | void user_disable_single_step(struct task_struct *task) |
865418d8 BH |
1507 | { |
1508 | struct pt_regs *regs = task->thread.regs; | |
1509 | ||
1510 | if (regs != NULL) { | |
172ae2e7 | 1511 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1512 | /* |
1513 | * The logic to disable single stepping should be as | |
1514 | * simple as turning off the Instruction Complete flag. | |
1515 | * And, after doing so, if all debug flags are off, turn | |
1516 | * off DBCR0(IDM) and MSR(DE) .... Torez | |
1517 | */ | |
682775b8 | 1518 | task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT); |
3bffb652 DK |
1519 | /* |
1520 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. | |
1521 | */ | |
51ae8d4a BB |
1522 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
1523 | task->thread.debug.dbcr1)) { | |
3bffb652 DK |
1524 | /* |
1525 | * All debug events were off..... | |
1526 | */ | |
51ae8d4a | 1527 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
28477fb1 DK |
1528 | regs->msr &= ~MSR_DE; |
1529 | } | |
865418d8 | 1530 | #else |
ec097c84 | 1531 | regs->msr &= ~(MSR_SE | MSR_BE); |
865418d8 BH |
1532 | #endif |
1533 | } | |
1534 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1535 | } | |
1536 | ||
5aae8a53 | 1537 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
a8b0ca17 | 1538 | void ptrace_triggered(struct perf_event *bp, |
5aae8a53 P |
1539 | struct perf_sample_data *data, struct pt_regs *regs) |
1540 | { | |
1541 | struct perf_event_attr attr; | |
1542 | ||
1543 | /* | |
1544 | * Disable the breakpoint request here since ptrace has defined a | |
1545 | * one-shot behaviour for breakpoint exceptions in PPC64. | |
1546 | * The SIGTRAP signal is generated automatically for us in do_dabr(). | |
1547 | * We don't have to do anything about that here | |
1548 | */ | |
1549 | attr = bp->attr; | |
1550 | attr.disabled = true; | |
1551 | modify_user_hw_breakpoint(bp, &attr); | |
1552 | } | |
1553 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1554 | ||
e51df2c1 | 1555 | static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, |
abd06505 BH |
1556 | unsigned long data) |
1557 | { | |
5aae8a53 P |
1558 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1559 | int ret; | |
1560 | struct thread_struct *thread = &(task->thread); | |
1561 | struct perf_event *bp; | |
1562 | struct perf_event_attr attr; | |
1563 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e MN |
1564 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
1565 | struct arch_hw_breakpoint hw_brk; | |
1566 | #endif | |
5aae8a53 | 1567 | |
d6a61bfc LM |
1568 | /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). |
1569 | * For embedded processors we support one DAC and no IAC's at the | |
1570 | * moment. | |
1571 | */ | |
abd06505 BH |
1572 | if (addr > 0) |
1573 | return -EINVAL; | |
1574 | ||
2325f0a0 | 1575 | /* The bottom 3 bits in dabr are flags */ |
abd06505 BH |
1576 | if ((data & ~0x7UL) >= TASK_SIZE) |
1577 | return -EIO; | |
1578 | ||
172ae2e7 | 1579 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
d6a61bfc LM |
1580 | /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. |
1581 | * It was assumed, on previous implementations, that 3 bits were | |
1582 | * passed together with the data address, fitting the design of the | |
1583 | * DABR register, as follows: | |
1584 | * | |
1585 | * bit 0: Read flag | |
1586 | * bit 1: Write flag | |
1587 | * bit 2: Breakpoint translation | |
1588 | * | |
1589 | * Thus, we use them here as so. | |
1590 | */ | |
1591 | ||
1592 | /* Ensure breakpoint translation bit is set */ | |
9422de3e | 1593 | if (data && !(data & HW_BRK_TYPE_TRANSLATE)) |
abd06505 | 1594 | return -EIO; |
9422de3e MN |
1595 | hw_brk.address = data & (~HW_BRK_TYPE_DABR); |
1596 | hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL; | |
1597 | hw_brk.len = 8; | |
5aae8a53 P |
1598 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1599 | bp = thread->ptrace_bps[0]; | |
9422de3e | 1600 | if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) { |
5aae8a53 P |
1601 | if (bp) { |
1602 | unregister_hw_breakpoint(bp); | |
1603 | thread->ptrace_bps[0] = NULL; | |
1604 | } | |
1605 | return 0; | |
1606 | } | |
1607 | if (bp) { | |
1608 | attr = bp->attr; | |
9422de3e MN |
1609 | attr.bp_addr = hw_brk.address; |
1610 | arch_bp_generic_fields(hw_brk.type, &attr.bp_type); | |
a53fd61a AP |
1611 | |
1612 | /* Enable breakpoint */ | |
1613 | attr.disabled = false; | |
1614 | ||
5aae8a53 | 1615 | ret = modify_user_hw_breakpoint(bp, &attr); |
925f83c0 | 1616 | if (ret) { |
5aae8a53 | 1617 | return ret; |
925f83c0 | 1618 | } |
5aae8a53 | 1619 | thread->ptrace_bps[0] = bp; |
9422de3e | 1620 | thread->hw_brk = hw_brk; |
5aae8a53 P |
1621 | return 0; |
1622 | } | |
1623 | ||
1624 | /* Create a new breakpoint request if one doesn't exist already */ | |
1625 | hw_breakpoint_init(&attr); | |
9422de3e MN |
1626 | attr.bp_addr = hw_brk.address; |
1627 | arch_bp_generic_fields(hw_brk.type, | |
1628 | &attr.bp_type); | |
5aae8a53 P |
1629 | |
1630 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
4dc0da86 | 1631 | ptrace_triggered, NULL, task); |
5aae8a53 P |
1632 | if (IS_ERR(bp)) { |
1633 | thread->ptrace_bps[0] = NULL; | |
1634 | return PTR_ERR(bp); | |
1635 | } | |
1636 | ||
1637 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 1638 | task->thread.hw_brk = hw_brk; |
172ae2e7 | 1639 | #else /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc LM |
1640 | /* As described above, it was assumed 3 bits were passed with the data |
1641 | * address, but we will assume only the mode bits will be passed | |
1642 | * as to not cause alignment restrictions for DAC-based processors. | |
1643 | */ | |
1644 | ||
1645 | /* DAC's hold the whole address without any mode flags */ | |
51ae8d4a | 1646 | task->thread.debug.dac1 = data & ~0x3UL; |
3bffb652 | 1647 | |
51ae8d4a | 1648 | if (task->thread.debug.dac1 == 0) { |
3bffb652 | 1649 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
51ae8d4a BB |
1650 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
1651 | task->thread.debug.dbcr1)) { | |
3bffb652 | 1652 | task->thread.regs->msr &= ~MSR_DE; |
51ae8d4a | 1653 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 | 1654 | } |
d6a61bfc LM |
1655 | return 0; |
1656 | } | |
1657 | ||
1658 | /* Read or Write bits must be set */ | |
1659 | ||
1660 | if (!(data & 0x3UL)) | |
1661 | return -EINVAL; | |
1662 | ||
1663 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 | |
1664 | register */ | |
51ae8d4a | 1665 | task->thread.debug.dbcr0 |= DBCR0_IDM; |
d6a61bfc LM |
1666 | |
1667 | /* Check for write and read flags and set DBCR0 | |
1668 | accordingly */ | |
3bffb652 | 1669 | dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W); |
d6a61bfc | 1670 | if (data & 0x1UL) |
3bffb652 | 1671 | dbcr_dac(task) |= DBCR_DAC1R; |
d6a61bfc | 1672 | if (data & 0x2UL) |
3bffb652 | 1673 | dbcr_dac(task) |= DBCR_DAC1W; |
d6a61bfc | 1674 | task->thread.regs->msr |= MSR_DE; |
172ae2e7 | 1675 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
abd06505 BH |
1676 | return 0; |
1677 | } | |
abd06505 | 1678 | |
1da177e4 LT |
1679 | /* |
1680 | * Called by kernel/ptrace.c when detaching.. | |
1681 | * | |
1682 | * Make sure single step bits etc are not set. | |
1683 | */ | |
1684 | void ptrace_disable(struct task_struct *child) | |
1685 | { | |
1686 | /* make sure the single step bit is not set. */ | |
2a84b0d7 | 1687 | user_disable_single_step(child); |
1da177e4 LT |
1688 | } |
1689 | ||
3bffb652 | 1690 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
84295dfc | 1691 | static long set_instruction_bp(struct task_struct *child, |
3bffb652 DK |
1692 | struct ppc_hw_breakpoint *bp_info) |
1693 | { | |
1694 | int slot; | |
51ae8d4a BB |
1695 | int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0); |
1696 | int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0); | |
1697 | int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0); | |
1698 | int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0); | |
3bffb652 DK |
1699 | |
1700 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1701 | slot2_in_use = 1; | |
1702 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1703 | slot4_in_use = 1; | |
1704 | ||
1705 | if (bp_info->addr >= TASK_SIZE) | |
1706 | return -EIO; | |
1707 | ||
1708 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { | |
1709 | ||
1710 | /* Make sure range is valid. */ | |
1711 | if (bp_info->addr2 >= TASK_SIZE) | |
1712 | return -EIO; | |
1713 | ||
1714 | /* We need a pair of IAC regsisters */ | |
1715 | if ((!slot1_in_use) && (!slot2_in_use)) { | |
1716 | slot = 1; | |
51ae8d4a BB |
1717 | child->thread.debug.iac1 = bp_info->addr; |
1718 | child->thread.debug.iac2 = bp_info->addr2; | |
1719 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
1720 | if (bp_info->addr_mode == |
1721 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1722 | dbcr_iac_range(child) |= DBCR_IAC12X; | |
1723 | else | |
1724 | dbcr_iac_range(child) |= DBCR_IAC12I; | |
1725 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1726 | } else if ((!slot3_in_use) && (!slot4_in_use)) { | |
1727 | slot = 3; | |
51ae8d4a BB |
1728 | child->thread.debug.iac3 = bp_info->addr; |
1729 | child->thread.debug.iac4 = bp_info->addr2; | |
1730 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
1731 | if (bp_info->addr_mode == |
1732 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1733 | dbcr_iac_range(child) |= DBCR_IAC34X; | |
1734 | else | |
1735 | dbcr_iac_range(child) |= DBCR_IAC34I; | |
1736 | #endif | |
1737 | } else | |
1738 | return -ENOSPC; | |
1739 | } else { | |
1740 | /* We only need one. If possible leave a pair free in | |
1741 | * case a range is needed later | |
1742 | */ | |
1743 | if (!slot1_in_use) { | |
1744 | /* | |
1745 | * Don't use iac1 if iac1-iac2 are free and either | |
1746 | * iac3 or iac4 (but not both) are free | |
1747 | */ | |
1748 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { | |
1749 | slot = 1; | |
51ae8d4a BB |
1750 | child->thread.debug.iac1 = bp_info->addr; |
1751 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
1752 | goto out; |
1753 | } | |
1754 | } | |
1755 | if (!slot2_in_use) { | |
1756 | slot = 2; | |
51ae8d4a BB |
1757 | child->thread.debug.iac2 = bp_info->addr; |
1758 | child->thread.debug.dbcr0 |= DBCR0_IAC2; | |
3bffb652 DK |
1759 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
1760 | } else if (!slot3_in_use) { | |
1761 | slot = 3; | |
51ae8d4a BB |
1762 | child->thread.debug.iac3 = bp_info->addr; |
1763 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
1764 | } else if (!slot4_in_use) { |
1765 | slot = 4; | |
51ae8d4a BB |
1766 | child->thread.debug.iac4 = bp_info->addr; |
1767 | child->thread.debug.dbcr0 |= DBCR0_IAC4; | |
3bffb652 DK |
1768 | #endif |
1769 | } else | |
1770 | return -ENOSPC; | |
1771 | } | |
1772 | out: | |
51ae8d4a | 1773 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
1774 | child->thread.regs->msr |= MSR_DE; |
1775 | ||
1776 | return slot; | |
1777 | } | |
1778 | ||
1779 | static int del_instruction_bp(struct task_struct *child, int slot) | |
1780 | { | |
1781 | switch (slot) { | |
1782 | case 1: | |
51ae8d4a | 1783 | if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0) |
3bffb652 DK |
1784 | return -ENOENT; |
1785 | ||
1786 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { | |
1787 | /* address range - clear slots 1 & 2 */ | |
51ae8d4a | 1788 | child->thread.debug.iac2 = 0; |
3bffb652 DK |
1789 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; |
1790 | } | |
51ae8d4a BB |
1791 | child->thread.debug.iac1 = 0; |
1792 | child->thread.debug.dbcr0 &= ~DBCR0_IAC1; | |
3bffb652 DK |
1793 | break; |
1794 | case 2: | |
51ae8d4a | 1795 | if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0) |
3bffb652 DK |
1796 | return -ENOENT; |
1797 | ||
1798 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1799 | /* used in a range */ | |
1800 | return -EINVAL; | |
51ae8d4a BB |
1801 | child->thread.debug.iac2 = 0; |
1802 | child->thread.debug.dbcr0 &= ~DBCR0_IAC2; | |
3bffb652 DK |
1803 | break; |
1804 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1805 | case 3: | |
51ae8d4a | 1806 | if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0) |
3bffb652 DK |
1807 | return -ENOENT; |
1808 | ||
1809 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { | |
1810 | /* address range - clear slots 3 & 4 */ | |
51ae8d4a | 1811 | child->thread.debug.iac4 = 0; |
3bffb652 DK |
1812 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; |
1813 | } | |
51ae8d4a BB |
1814 | child->thread.debug.iac3 = 0; |
1815 | child->thread.debug.dbcr0 &= ~DBCR0_IAC3; | |
3bffb652 DK |
1816 | break; |
1817 | case 4: | |
51ae8d4a | 1818 | if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0) |
3bffb652 DK |
1819 | return -ENOENT; |
1820 | ||
1821 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1822 | /* Used in a range */ | |
1823 | return -EINVAL; | |
51ae8d4a BB |
1824 | child->thread.debug.iac4 = 0; |
1825 | child->thread.debug.dbcr0 &= ~DBCR0_IAC4; | |
3bffb652 DK |
1826 | break; |
1827 | #endif | |
1828 | default: | |
1829 | return -EINVAL; | |
1830 | } | |
1831 | return 0; | |
1832 | } | |
1833 | ||
1834 | static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |
1835 | { | |
1836 | int byte_enable = | |
1837 | (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) | |
1838 | & 0xf; | |
1839 | int condition_mode = | |
1840 | bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; | |
1841 | int slot; | |
1842 | ||
1843 | if (byte_enable && (condition_mode == 0)) | |
1844 | return -EINVAL; | |
1845 | ||
1846 | if (bp_info->addr >= TASK_SIZE) | |
1847 | return -EIO; | |
1848 | ||
1849 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { | |
1850 | slot = 1; | |
1851 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1852 | dbcr_dac(child) |= DBCR_DAC1R; | |
1853 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1854 | dbcr_dac(child) |= DBCR_DAC1W; | |
51ae8d4a | 1855 | child->thread.debug.dac1 = (unsigned long)bp_info->addr; |
3bffb652 DK |
1856 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1857 | if (byte_enable) { | |
51ae8d4a | 1858 | child->thread.debug.dvc1 = |
3bffb652 | 1859 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 1860 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
1861 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | |
1862 | (condition_mode << DBCR2_DVC1M_SHIFT)); | |
1863 | } | |
1864 | #endif | |
1865 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1866 | } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
3bffb652 DK |
1867 | /* Both dac1 and dac2 are part of a range */ |
1868 | return -ENOSPC; | |
1869 | #endif | |
1870 | } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { | |
1871 | slot = 2; | |
1872 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1873 | dbcr_dac(child) |= DBCR_DAC2R; | |
1874 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1875 | dbcr_dac(child) |= DBCR_DAC2W; | |
51ae8d4a | 1876 | child->thread.debug.dac2 = (unsigned long)bp_info->addr; |
3bffb652 DK |
1877 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1878 | if (byte_enable) { | |
51ae8d4a | 1879 | child->thread.debug.dvc2 = |
3bffb652 | 1880 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 1881 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
1882 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | |
1883 | (condition_mode << DBCR2_DVC2M_SHIFT)); | |
1884 | } | |
1885 | #endif | |
1886 | } else | |
1887 | return -ENOSPC; | |
51ae8d4a | 1888 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
1889 | child->thread.regs->msr |= MSR_DE; |
1890 | ||
1891 | return slot + 4; | |
1892 | } | |
1893 | ||
1894 | static int del_dac(struct task_struct *child, int slot) | |
1895 | { | |
1896 | if (slot == 1) { | |
30124d11 | 1897 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
3bffb652 DK |
1898 | return -ENOENT; |
1899 | ||
51ae8d4a | 1900 | child->thread.debug.dac1 = 0; |
3bffb652 DK |
1901 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
1902 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a BB |
1903 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
1904 | child->thread.debug.dac2 = 0; | |
1905 | child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; | |
3bffb652 | 1906 | } |
51ae8d4a | 1907 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); |
3bffb652 DK |
1908 | #endif |
1909 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 1910 | child->thread.debug.dvc1 = 0; |
3bffb652 DK |
1911 | #endif |
1912 | } else if (slot == 2) { | |
30124d11 | 1913 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
3bffb652 DK |
1914 | return -ENOENT; |
1915 | ||
1916 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1917 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) |
3bffb652 DK |
1918 | /* Part of a range */ |
1919 | return -EINVAL; | |
51ae8d4a | 1920 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); |
3bffb652 DK |
1921 | #endif |
1922 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 1923 | child->thread.debug.dvc2 = 0; |
3bffb652 | 1924 | #endif |
51ae8d4a | 1925 | child->thread.debug.dac2 = 0; |
3bffb652 DK |
1926 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
1927 | } else | |
1928 | return -EINVAL; | |
1929 | ||
1930 | return 0; | |
1931 | } | |
1932 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ | |
1933 | ||
1934 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1935 | static int set_dac_range(struct task_struct *child, | |
1936 | struct ppc_hw_breakpoint *bp_info) | |
1937 | { | |
1938 | int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; | |
1939 | ||
1940 | /* We don't allow range watchpoints to be used with DVC */ | |
1941 | if (bp_info->condition_mode) | |
1942 | return -EINVAL; | |
1943 | ||
1944 | /* | |
1945 | * Best effort to verify the address range. The user/supervisor bits | |
1946 | * prevent trapping in kernel space, but let's fail on an obvious bad | |
1947 | * range. The simple test on the mask is not fool-proof, and any | |
1948 | * exclusive range will spill over into kernel space. | |
1949 | */ | |
1950 | if (bp_info->addr >= TASK_SIZE) | |
1951 | return -EIO; | |
1952 | if (mode == PPC_BREAKPOINT_MODE_MASK) { | |
1953 | /* | |
1954 | * dac2 is a bitmask. Don't allow a mask that makes a | |
1955 | * kernel space address from a valid dac1 value | |
1956 | */ | |
1957 | if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) | |
1958 | return -EIO; | |
1959 | } else { | |
1960 | /* | |
1961 | * For range breakpoints, addr2 must also be a valid address | |
1962 | */ | |
1963 | if (bp_info->addr2 >= TASK_SIZE) | |
1964 | return -EIO; | |
1965 | } | |
1966 | ||
51ae8d4a | 1967 | if (child->thread.debug.dbcr0 & |
3bffb652 DK |
1968 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) |
1969 | return -ENOSPC; | |
1970 | ||
1971 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
51ae8d4a | 1972 | child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); |
3bffb652 | 1973 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
51ae8d4a BB |
1974 | child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); |
1975 | child->thread.debug.dac1 = bp_info->addr; | |
1976 | child->thread.debug.dac2 = bp_info->addr2; | |
3bffb652 | 1977 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
51ae8d4a | 1978 | child->thread.debug.dbcr2 |= DBCR2_DAC12M; |
3bffb652 | 1979 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
51ae8d4a | 1980 | child->thread.debug.dbcr2 |= DBCR2_DAC12MX; |
3bffb652 | 1981 | else /* PPC_BREAKPOINT_MODE_MASK */ |
51ae8d4a | 1982 | child->thread.debug.dbcr2 |= DBCR2_DAC12MM; |
3bffb652 DK |
1983 | child->thread.regs->msr |= MSR_DE; |
1984 | ||
1985 | return 5; | |
1986 | } | |
1987 | #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ | |
1988 | ||
3162d92d DK |
1989 | static long ppc_set_hwdebug(struct task_struct *child, |
1990 | struct ppc_hw_breakpoint *bp_info) | |
1991 | { | |
6c7a2856 P |
1992 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1993 | int len = 0; | |
1994 | struct thread_struct *thread = &(child->thread); | |
1995 | struct perf_event *bp; | |
1996 | struct perf_event_attr attr; | |
1997 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
4dfbf290 | 1998 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e | 1999 | struct arch_hw_breakpoint brk; |
4dfbf290 AS |
2000 | #endif |
2001 | ||
3bffb652 DK |
2002 | if (bp_info->version != 1) |
2003 | return -ENOTSUPP; | |
2004 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
2005 | /* | |
2006 | * Check for invalid flags and combinations | |
2007 | */ | |
2008 | if ((bp_info->trigger_type == 0) || | |
2009 | (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | | |
2010 | PPC_BREAKPOINT_TRIGGER_RW)) || | |
2011 | (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || | |
2012 | (bp_info->condition_mode & | |
2013 | ~(PPC_BREAKPOINT_CONDITION_MODE | | |
2014 | PPC_BREAKPOINT_CONDITION_BE_ALL))) | |
2015 | return -EINVAL; | |
2016 | #if CONFIG_PPC_ADV_DEBUG_DVCS == 0 | |
2017 | if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) | |
2018 | return -EINVAL; | |
2019 | #endif | |
2020 | ||
2021 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { | |
2022 | if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || | |
2023 | (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) | |
2024 | return -EINVAL; | |
84295dfc | 2025 | return set_instruction_bp(child, bp_info); |
3bffb652 DK |
2026 | } |
2027 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) | |
2028 | return set_dac(child, bp_info); | |
2029 | ||
2030 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2031 | return set_dac_range(child, bp_info); | |
2032 | #else | |
2033 | return -EINVAL; | |
2034 | #endif | |
2035 | #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */ | |
3162d92d | 2036 | /* |
3bffb652 | 2037 | * We only support one data breakpoint |
3162d92d | 2038 | */ |
4dfbf290 AS |
2039 | if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 || |
2040 | (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 || | |
4dfbf290 | 2041 | bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) |
3162d92d DK |
2042 | return -EINVAL; |
2043 | ||
3162d92d DK |
2044 | if ((unsigned long)bp_info->addr >= TASK_SIZE) |
2045 | return -EIO; | |
2046 | ||
9422de3e MN |
2047 | brk.address = bp_info->addr & ~7UL; |
2048 | brk.type = HW_BRK_TYPE_TRANSLATE; | |
2bb78efa | 2049 | brk.len = 8; |
4dfbf290 | 2050 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
9422de3e | 2051 | brk.type |= HW_BRK_TYPE_READ; |
4dfbf290 | 2052 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
9422de3e | 2053 | brk.type |= HW_BRK_TYPE_WRITE; |
6c7a2856 | 2054 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
6c7a2856 P |
2055 | /* |
2056 | * Check if the request is for 'range' breakpoints. We can | |
2057 | * support it if range < 8 bytes. | |
2058 | */ | |
6961ed96 | 2059 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
6c7a2856 | 2060 | len = bp_info->addr2 - bp_info->addr; |
6961ed96 | 2061 | else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) |
b0b0aa9c | 2062 | len = 1; |
6961ed96 | 2063 | else |
6c7a2856 | 2064 | return -EINVAL; |
6c7a2856 | 2065 | bp = thread->ptrace_bps[0]; |
6961ed96 | 2066 | if (bp) |
6c7a2856 | 2067 | return -ENOSPC; |
6c7a2856 P |
2068 | |
2069 | /* Create a new breakpoint request if one doesn't exist already */ | |
2070 | hw_breakpoint_init(&attr); | |
2071 | attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN; | |
2072 | attr.bp_len = len; | |
9422de3e | 2073 | arch_bp_generic_fields(brk.type, &attr.bp_type); |
6c7a2856 P |
2074 | |
2075 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
2076 | ptrace_triggered, NULL, child); | |
2077 | if (IS_ERR(bp)) { | |
2078 | thread->ptrace_bps[0] = NULL; | |
6c7a2856 P |
2079 | return PTR_ERR(bp); |
2080 | } | |
2081 | ||
6c7a2856 P |
2082 | return 1; |
2083 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
2084 | ||
2085 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) | |
2086 | return -EINVAL; | |
2087 | ||
9422de3e | 2088 | if (child->thread.hw_brk.address) |
6c7a2856 | 2089 | return -ENOSPC; |
4dfbf290 | 2090 | |
9422de3e | 2091 | child->thread.hw_brk = brk; |
3bffb652 | 2092 | |
3162d92d | 2093 | return 1; |
3bffb652 | 2094 | #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ |
3162d92d DK |
2095 | } |
2096 | ||
ec1b33dc | 2097 | static long ppc_del_hwdebug(struct task_struct *child, long data) |
3162d92d | 2098 | { |
6c7a2856 P |
2099 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2100 | int ret = 0; | |
2101 | struct thread_struct *thread = &(child->thread); | |
2102 | struct perf_event *bp; | |
2103 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
3bffb652 DK |
2104 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
2105 | int rc; | |
2106 | ||
2107 | if (data <= 4) | |
2108 | rc = del_instruction_bp(child, (int)data); | |
2109 | else | |
2110 | rc = del_dac(child, (int)data - 4); | |
2111 | ||
2112 | if (!rc) { | |
51ae8d4a BB |
2113 | if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, |
2114 | child->thread.debug.dbcr1)) { | |
2115 | child->thread.debug.dbcr0 &= ~DBCR0_IDM; | |
3bffb652 DK |
2116 | child->thread.regs->msr &= ~MSR_DE; |
2117 | } | |
2118 | } | |
2119 | return rc; | |
2120 | #else | |
3162d92d DK |
2121 | if (data != 1) |
2122 | return -EINVAL; | |
6c7a2856 P |
2123 | |
2124 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
6c7a2856 P |
2125 | bp = thread->ptrace_bps[0]; |
2126 | if (bp) { | |
2127 | unregister_hw_breakpoint(bp); | |
2128 | thread->ptrace_bps[0] = NULL; | |
2129 | } else | |
2130 | ret = -ENOENT; | |
6c7a2856 P |
2131 | return ret; |
2132 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 2133 | if (child->thread.hw_brk.address == 0) |
3162d92d DK |
2134 | return -ENOENT; |
2135 | ||
9422de3e MN |
2136 | child->thread.hw_brk.address = 0; |
2137 | child->thread.hw_brk.type = 0; | |
6c7a2856 | 2138 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 2139 | |
3162d92d | 2140 | return 0; |
3bffb652 | 2141 | #endif |
3162d92d DK |
2142 | } |
2143 | ||
9b05a69e NK |
2144 | long arch_ptrace(struct task_struct *child, long request, |
2145 | unsigned long addr, unsigned long data) | |
1da177e4 | 2146 | { |
1da177e4 | 2147 | int ret = -EPERM; |
f68d2048 NK |
2148 | void __user *datavp = (void __user *) data; |
2149 | unsigned long __user *datalp = datavp; | |
1da177e4 | 2150 | |
1da177e4 | 2151 | switch (request) { |
1da177e4 | 2152 | /* read the word at location addr in the USER area. */ |
1da177e4 LT |
2153 | case PTRACE_PEEKUSR: { |
2154 | unsigned long index, tmp; | |
2155 | ||
2156 | ret = -EIO; | |
2157 | /* convert to index and check */ | |
e8a30302 | 2158 | #ifdef CONFIG_PPC32 |
9b05a69e | 2159 | index = addr >> 2; |
e8a30302 SR |
2160 | if ((addr & 3) || (index > PT_FPSCR) |
2161 | || (child->thread.regs == NULL)) | |
2162 | #else | |
9b05a69e | 2163 | index = addr >> 3; |
e8a30302 SR |
2164 | if ((addr & 7) || (index > PT_FPSCR)) |
2165 | #endif | |
1da177e4 LT |
2166 | break; |
2167 | ||
2168 | CHECK_FULL_REGS(child->thread.regs); | |
2169 | if (index < PT_FPR0) { | |
ee4a3916 AK |
2170 | ret = ptrace_get_reg(child, (int) index, &tmp); |
2171 | if (ret) | |
2172 | break; | |
1da177e4 | 2173 | } else { |
e69b742a BH |
2174 | unsigned int fpidx = index - PT_FPR0; |
2175 | ||
e8a30302 | 2176 | flush_fp_to_thread(child); |
e69b742a | 2177 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 2178 | memcpy(&tmp, &child->thread.TS_FPR(fpidx), |
87fec051 | 2179 | sizeof(long)); |
e69b742a | 2180 | else |
de79f7b9 | 2181 | tmp = child->thread.fp_state.fpscr; |
1da177e4 | 2182 | } |
f68d2048 | 2183 | ret = put_user(tmp, datalp); |
1da177e4 LT |
2184 | break; |
2185 | } | |
2186 | ||
1da177e4 LT |
2187 | /* write the word at location addr in the USER area */ |
2188 | case PTRACE_POKEUSR: { | |
2189 | unsigned long index; | |
2190 | ||
2191 | ret = -EIO; | |
2192 | /* convert to index and check */ | |
e8a30302 | 2193 | #ifdef CONFIG_PPC32 |
9b05a69e | 2194 | index = addr >> 2; |
e8a30302 SR |
2195 | if ((addr & 3) || (index > PT_FPSCR) |
2196 | || (child->thread.regs == NULL)) | |
2197 | #else | |
9b05a69e | 2198 | index = addr >> 3; |
e8a30302 SR |
2199 | if ((addr & 7) || (index > PT_FPSCR)) |
2200 | #endif | |
1da177e4 LT |
2201 | break; |
2202 | ||
2203 | CHECK_FULL_REGS(child->thread.regs); | |
1da177e4 | 2204 | if (index < PT_FPR0) { |
865418d8 | 2205 | ret = ptrace_put_reg(child, index, data); |
1da177e4 | 2206 | } else { |
e69b742a BH |
2207 | unsigned int fpidx = index - PT_FPR0; |
2208 | ||
e8a30302 | 2209 | flush_fp_to_thread(child); |
e69b742a | 2210 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 2211 | memcpy(&child->thread.TS_FPR(fpidx), &data, |
87fec051 | 2212 | sizeof(long)); |
e69b742a | 2213 | else |
de79f7b9 | 2214 | child->thread.fp_state.fpscr = data; |
1da177e4 LT |
2215 | ret = 0; |
2216 | } | |
2217 | break; | |
2218 | } | |
2219 | ||
3162d92d DK |
2220 | case PPC_PTRACE_GETHWDBGINFO: { |
2221 | struct ppc_debug_info dbginfo; | |
2222 | ||
2223 | dbginfo.version = 1; | |
3bffb652 DK |
2224 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
2225 | dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; | |
2226 | dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; | |
2227 | dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; | |
2228 | dbginfo.data_bp_alignment = 4; | |
2229 | dbginfo.sizeof_condition = 4; | |
2230 | dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | | |
2231 | PPC_DEBUG_FEATURE_INSN_BP_MASK; | |
2232 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2233 | dbginfo.features |= | |
2234 | PPC_DEBUG_FEATURE_DATA_BP_RANGE | | |
2235 | PPC_DEBUG_FEATURE_DATA_BP_MASK; | |
2236 | #endif | |
2237 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
3162d92d DK |
2238 | dbginfo.num_instruction_bps = 0; |
2239 | dbginfo.num_data_bps = 1; | |
2240 | dbginfo.num_condition_regs = 0; | |
2241 | #ifdef CONFIG_PPC64 | |
2242 | dbginfo.data_bp_alignment = 8; | |
2243 | #else | |
2244 | dbginfo.data_bp_alignment = 4; | |
2245 | #endif | |
2246 | dbginfo.sizeof_condition = 0; | |
6c7a2856 P |
2247 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2248 | dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE; | |
517b7314 MN |
2249 | if (cpu_has_feature(CPU_FTR_DAWR)) |
2250 | dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR; | |
6c7a2856 | 2251 | #else |
3162d92d | 2252 | dbginfo.features = 0; |
6c7a2856 | 2253 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 2254 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
3162d92d | 2255 | |
f68d2048 | 2256 | if (!access_ok(VERIFY_WRITE, datavp, |
3162d92d DK |
2257 | sizeof(struct ppc_debug_info))) |
2258 | return -EFAULT; | |
f68d2048 NK |
2259 | ret = __copy_to_user(datavp, &dbginfo, |
2260 | sizeof(struct ppc_debug_info)) ? | |
3162d92d DK |
2261 | -EFAULT : 0; |
2262 | break; | |
2263 | } | |
2264 | ||
2265 | case PPC_PTRACE_SETHWDEBUG: { | |
2266 | struct ppc_hw_breakpoint bp_info; | |
2267 | ||
f68d2048 | 2268 | if (!access_ok(VERIFY_READ, datavp, |
3162d92d DK |
2269 | sizeof(struct ppc_hw_breakpoint))) |
2270 | return -EFAULT; | |
f68d2048 | 2271 | ret = __copy_from_user(&bp_info, datavp, |
3162d92d DK |
2272 | sizeof(struct ppc_hw_breakpoint)) ? |
2273 | -EFAULT : 0; | |
2274 | if (!ret) | |
2275 | ret = ppc_set_hwdebug(child, &bp_info); | |
2276 | break; | |
2277 | } | |
2278 | ||
2279 | case PPC_PTRACE_DELHWDEBUG: { | |
ec1b33dc | 2280 | ret = ppc_del_hwdebug(child, data); |
3162d92d DK |
2281 | break; |
2282 | } | |
2283 | ||
e8a30302 | 2284 | case PTRACE_GET_DEBUGREG: { |
9422de3e MN |
2285 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
2286 | unsigned long dabr_fake; | |
2287 | #endif | |
e8a30302 SR |
2288 | ret = -EINVAL; |
2289 | /* We only support one DABR and no IABRS at the moment */ | |
2290 | if (addr > 0) | |
2291 | break; | |
3bffb652 | 2292 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a | 2293 | ret = put_user(child->thread.debug.dac1, datalp); |
3bffb652 | 2294 | #else |
9422de3e MN |
2295 | dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | |
2296 | (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); | |
2297 | ret = put_user(dabr_fake, datalp); | |
3bffb652 | 2298 | #endif |
e8a30302 SR |
2299 | break; |
2300 | } | |
2301 | ||
2302 | case PTRACE_SET_DEBUGREG: | |
2303 | ret = ptrace_set_debugreg(child, addr, data); | |
2304 | break; | |
e8a30302 | 2305 | |
e17666ba BH |
2306 | #ifdef CONFIG_PPC64 |
2307 | case PTRACE_GETREGS64: | |
2308 | #endif | |
c391cd00 RM |
2309 | case PTRACE_GETREGS: /* Get all pt_regs from the child. */ |
2310 | return copy_regset_to_user(child, &user_ppc_native_view, | |
2311 | REGSET_GPR, | |
2312 | 0, sizeof(struct pt_regs), | |
f68d2048 | 2313 | datavp); |
e8a30302 | 2314 | |
e17666ba BH |
2315 | #ifdef CONFIG_PPC64 |
2316 | case PTRACE_SETREGS64: | |
2317 | #endif | |
c391cd00 RM |
2318 | case PTRACE_SETREGS: /* Set all gp regs in the child. */ |
2319 | return copy_regset_from_user(child, &user_ppc_native_view, | |
2320 | REGSET_GPR, | |
2321 | 0, sizeof(struct pt_regs), | |
f68d2048 | 2322 | datavp); |
c391cd00 RM |
2323 | |
2324 | case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */ | |
2325 | return copy_regset_to_user(child, &user_ppc_native_view, | |
2326 | REGSET_FPR, | |
2327 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 2328 | datavp); |
c391cd00 RM |
2329 | |
2330 | case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */ | |
2331 | return copy_regset_from_user(child, &user_ppc_native_view, | |
2332 | REGSET_FPR, | |
2333 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 2334 | datavp); |
e8a30302 | 2335 | |
1da177e4 LT |
2336 | #ifdef CONFIG_ALTIVEC |
2337 | case PTRACE_GETVRREGS: | |
c391cd00 RM |
2338 | return copy_regset_to_user(child, &user_ppc_native_view, |
2339 | REGSET_VMX, | |
2340 | 0, (33 * sizeof(vector128) + | |
2341 | sizeof(u32)), | |
f68d2048 | 2342 | datavp); |
1da177e4 LT |
2343 | |
2344 | case PTRACE_SETVRREGS: | |
c391cd00 RM |
2345 | return copy_regset_from_user(child, &user_ppc_native_view, |
2346 | REGSET_VMX, | |
2347 | 0, (33 * sizeof(vector128) + | |
2348 | sizeof(u32)), | |
f68d2048 | 2349 | datavp); |
1da177e4 | 2350 | #endif |
ce48b210 MN |
2351 | #ifdef CONFIG_VSX |
2352 | case PTRACE_GETVSRREGS: | |
2353 | return copy_regset_to_user(child, &user_ppc_native_view, | |
2354 | REGSET_VSX, | |
1ac42ef8 | 2355 | 0, 32 * sizeof(double), |
f68d2048 | 2356 | datavp); |
ce48b210 MN |
2357 | |
2358 | case PTRACE_SETVSRREGS: | |
2359 | return copy_regset_from_user(child, &user_ppc_native_view, | |
2360 | REGSET_VSX, | |
1ac42ef8 | 2361 | 0, 32 * sizeof(double), |
f68d2048 | 2362 | datavp); |
ce48b210 | 2363 | #endif |
1da177e4 LT |
2364 | #ifdef CONFIG_SPE |
2365 | case PTRACE_GETEVRREGS: | |
2366 | /* Get the child spe register state. */ | |
c391cd00 RM |
2367 | return copy_regset_to_user(child, &user_ppc_native_view, |
2368 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 2369 | datavp); |
1da177e4 LT |
2370 | |
2371 | case PTRACE_SETEVRREGS: | |
2372 | /* Set the child spe register state. */ | |
c391cd00 RM |
2373 | return copy_regset_from_user(child, &user_ppc_native_view, |
2374 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 2375 | datavp); |
1da177e4 LT |
2376 | #endif |
2377 | ||
2378 | default: | |
2379 | ret = ptrace_request(child, request, addr, data); | |
2380 | break; | |
2381 | } | |
1da177e4 LT |
2382 | return ret; |
2383 | } | |
2384 | ||
2449acc5 ME |
2385 | #ifdef CONFIG_SECCOMP |
2386 | static int do_seccomp(struct pt_regs *regs) | |
2387 | { | |
2388 | if (!test_thread_flag(TIF_SECCOMP)) | |
2389 | return 0; | |
2390 | ||
2391 | /* | |
2392 | * The ABI we present to seccomp tracers is that r3 contains | |
2393 | * the syscall return value and orig_gpr3 contains the first | |
2394 | * syscall parameter. This is different to the ptrace ABI where | |
2395 | * both r3 and orig_gpr3 contain the first syscall parameter. | |
2396 | */ | |
2397 | regs->gpr[3] = -ENOSYS; | |
2398 | ||
2399 | /* | |
2400 | * We use the __ version here because we have already checked | |
2401 | * TIF_SECCOMP. If this fails, there is nothing left to do, we | |
2402 | * have already loaded -ENOSYS into r3, or seccomp has put | |
2403 | * something else in r3 (via SECCOMP_RET_ERRNO/TRACE). | |
2404 | */ | |
2f275de5 | 2405 | if (__secure_computing(NULL)) |
2449acc5 ME |
2406 | return -1; |
2407 | ||
2408 | /* | |
2409 | * The syscall was allowed by seccomp, restore the register | |
1addc57e | 2410 | * state to what audit expects. |
2449acc5 ME |
2411 | * Note that we use orig_gpr3, which means a seccomp tracer can |
2412 | * modify the first syscall parameter (in orig_gpr3) and also | |
2413 | * allow the syscall to proceed. | |
2414 | */ | |
2415 | regs->gpr[3] = regs->orig_gpr3; | |
2416 | ||
2417 | return 0; | |
2418 | } | |
2419 | #else | |
2420 | static inline int do_seccomp(struct pt_regs *regs) { return 0; } | |
2421 | #endif /* CONFIG_SECCOMP */ | |
2422 | ||
d3837414 ME |
2423 | /** |
2424 | * do_syscall_trace_enter() - Do syscall tracing on kernel entry. | |
2425 | * @regs: the pt_regs of the task to trace (current) | |
2426 | * | |
2427 | * Performs various types of tracing on syscall entry. This includes seccomp, | |
2428 | * ptrace, syscall tracepoints and audit. | |
2429 | * | |
2430 | * The pt_regs are potentially visible to userspace via ptrace, so their | |
2431 | * contents is ABI. | |
2432 | * | |
2433 | * One or more of the tracers may modify the contents of pt_regs, in particular | |
2434 | * to modify arguments or even the syscall number itself. | |
2435 | * | |
2436 | * It's also possible that a tracer can choose to reject the system call. In | |
2437 | * that case this function will return an illegal syscall number, and will put | |
2438 | * an appropriate return value in regs->r3. | |
2439 | * | |
2440 | * Return: the (possibly changed) syscall number. | |
4f72c427 RM |
2441 | */ |
2442 | long do_syscall_trace_enter(struct pt_regs *regs) | |
1da177e4 | 2443 | { |
22ecbe8d LZ |
2444 | user_exit(); |
2445 | ||
1addc57e KC |
2446 | /* |
2447 | * The tracer may decide to abort the syscall, if so tracehook | |
2448 | * will return !0. Note that the tracer may also just change | |
2449 | * regs->gpr[0] to an invalid syscall number, that is handled | |
2450 | * below on the exit path. | |
2451 | */ | |
2452 | if (test_thread_flag(TIF_SYSCALL_TRACE) && | |
2453 | tracehook_report_syscall_entry(regs)) | |
2454 | goto skip; | |
2455 | ||
2456 | /* Run seccomp after ptrace; allow it to set gpr[3]. */ | |
2449acc5 ME |
2457 | if (do_seccomp(regs)) |
2458 | return -1; | |
e8a30302 | 2459 | |
1addc57e KC |
2460 | /* Avoid trace and audit when syscall is invalid. */ |
2461 | if (regs->gpr[0] >= NR_syscalls) | |
2462 | goto skip; | |
ea9c102c | 2463 | |
02424d89 IM |
2464 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
2465 | trace_sys_enter(regs, regs->gpr[0]); | |
2466 | ||
cfcd1705 | 2467 | #ifdef CONFIG_PPC64 |
b05d8447 | 2468 | if (!is_32bit_task()) |
91397401 | 2469 | audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4], |
b05d8447 EP |
2470 | regs->gpr[5], regs->gpr[6]); |
2471 | else | |
e8a30302 | 2472 | #endif |
91397401 | 2473 | audit_syscall_entry(regs->gpr[0], |
b05d8447 EP |
2474 | regs->gpr[3] & 0xffffffff, |
2475 | regs->gpr[4] & 0xffffffff, | |
2476 | regs->gpr[5] & 0xffffffff, | |
2477 | regs->gpr[6] & 0xffffffff); | |
4f72c427 | 2478 | |
d3837414 ME |
2479 | /* Return the possibly modified but valid syscall number */ |
2480 | return regs->gpr[0]; | |
1addc57e KC |
2481 | |
2482 | skip: | |
2483 | /* | |
2484 | * If we are aborting explicitly, or if the syscall number is | |
2485 | * now invalid, set the return value to -ENOSYS. | |
2486 | */ | |
2487 | regs->gpr[3] = -ENOSYS; | |
2488 | return -1; | |
ea9c102c DW |
2489 | } |
2490 | ||
2491 | void do_syscall_trace_leave(struct pt_regs *regs) | |
2492 | { | |
4f72c427 RM |
2493 | int step; |
2494 | ||
d7e7528b | 2495 | audit_syscall_exit(regs); |
ea9c102c | 2496 | |
02424d89 IM |
2497 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
2498 | trace_sys_exit(regs, regs->result); | |
2499 | ||
4f72c427 RM |
2500 | step = test_thread_flag(TIF_SINGLESTEP); |
2501 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) | |
2502 | tracehook_report_syscall_exit(regs, step); | |
22ecbe8d LZ |
2503 | |
2504 | user_enter(); | |
ea9c102c | 2505 | } |