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Merge git://git.infradead.org/battery-2.6
[deliverable/linux.git] / arch / powerpc / kernel / ptrace.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
b123923d 11 * and Paul Mackerras (paulus@samba.org).
1da177e4
LT		 12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
1da177e4
LT		 22#include <linux/errno.h>
23#include <linux/ptrace.h>
f65255e8 24#include <linux/regset.h>
4f72c427 25#include <linux/tracehook.h>
3caf06c6 26#include <linux/elf.h>
1da177e4
LT		 27#include <linux/user.h>
28#include <linux/security.h>
7ed20e1a 29#include <linux/signal.h>
ea9c102c
DW		 30#include <linux/seccomp.h>
31#include <linux/audit.h>
e8a30302 32#ifdef CONFIG_PPC32
ea9c102c 33#include <linux/module.h>
e8a30302 34#endif
5aae8a53
P		 35#include <linux/hw_breakpoint.h>
36#include <linux/perf_event.h>
1da177e4
LT		 37
38#include <asm/uaccess.h>
39#include <asm/page.h>
40#include <asm/pgtable.h>
41#include <asm/system.h>
21a62902 42
359e4284
MS		 43/*
44 * The parameter save area on the stack is used to store arguments being passed
45 * to callee function and is located at fixed offset from stack pointer.
46 */
47#ifdef CONFIG_PPC32
48#define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
49#else /* CONFIG_PPC32 */
50#define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
51#endif
52
53struct pt_regs_offset {
54 const char *name;
55 int offset;
56};
57
58#define STR(s) #s /* convert to string */
59#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
60#define GPR_OFFSET_NAME(num) \
61 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
62#define REG_OFFSET_END {.name = NULL, .offset = 0}
63
64static const struct pt_regs_offset regoffset_table[] = {
65 GPR_OFFSET_NAME(0),
66 GPR_OFFSET_NAME(1),
67 GPR_OFFSET_NAME(2),
68 GPR_OFFSET_NAME(3),
69 GPR_OFFSET_NAME(4),
70 GPR_OFFSET_NAME(5),
71 GPR_OFFSET_NAME(6),
72 GPR_OFFSET_NAME(7),
73 GPR_OFFSET_NAME(8),
74 GPR_OFFSET_NAME(9),
75 GPR_OFFSET_NAME(10),
76 GPR_OFFSET_NAME(11),
77 GPR_OFFSET_NAME(12),
78 GPR_OFFSET_NAME(13),
79 GPR_OFFSET_NAME(14),
80 GPR_OFFSET_NAME(15),
81 GPR_OFFSET_NAME(16),
82 GPR_OFFSET_NAME(17),
83 GPR_OFFSET_NAME(18),
84 GPR_OFFSET_NAME(19),
85 GPR_OFFSET_NAME(20),
86 GPR_OFFSET_NAME(21),
87 GPR_OFFSET_NAME(22),
88 GPR_OFFSET_NAME(23),
89 GPR_OFFSET_NAME(24),
90 GPR_OFFSET_NAME(25),
91 GPR_OFFSET_NAME(26),
92 GPR_OFFSET_NAME(27),
93 GPR_OFFSET_NAME(28),
94 GPR_OFFSET_NAME(29),
95 GPR_OFFSET_NAME(30),
96 GPR_OFFSET_NAME(31),
97 REG_OFFSET_NAME(nip),
98 REG_OFFSET_NAME(msr),
99 REG_OFFSET_NAME(ctr),
100 REG_OFFSET_NAME(link),
101 REG_OFFSET_NAME(xer),
102 REG_OFFSET_NAME(ccr),
103#ifdef CONFIG_PPC64
104 REG_OFFSET_NAME(softe),
105#else
106 REG_OFFSET_NAME(mq),
107#endif
108 REG_OFFSET_NAME(trap),
109 REG_OFFSET_NAME(dar),
110 REG_OFFSET_NAME(dsisr),
111 REG_OFFSET_END,
112};
113
114/**
115 * regs_query_register_offset() - query register offset from its name
116 * @name: the name of a register
117 *
118 * regs_query_register_offset() returns the offset of a register in struct
119 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
120 */
121int regs_query_register_offset(const char *name)
122{
123 const struct pt_regs_offset *roff;
124 for (roff = regoffset_table; roff->name != NULL; roff++)
125 if (!strcmp(roff->name, name))
126 return roff->offset;
127 return -EINVAL;
128}
129
130/**
131 * regs_query_register_name() - query register name from its offset
132 * @offset: the offset of a register in struct pt_regs.
133 *
134 * regs_query_register_name() returns the name of a register from its
135 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
136 */
137const char *regs_query_register_name(unsigned int offset)
138{
139 const struct pt_regs_offset *roff;
140 for (roff = regoffset_table; roff->name != NULL; roff++)
141 if (roff->offset == offset)
142 return roff->name;
143 return NULL;
144}
145
abd06505
BH		 146/*
147 * does not yet catch signals sent when the child dies.
148 * in exit.c or in signal.c.
149 */
150
151/*
152 * Set of msr bits that gdb can change on behalf of a process.
153 */
172ae2e7 154#ifdef CONFIG_PPC_ADV_DEBUG_REGS
abd06505 155#define MSR_DEBUGCHANGE 0
1da177e4 156#else
abd06505 157#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
1da177e4 158#endif
acd89828 159
1da177e4 160/*
abd06505 161 * Max register writeable via put_reg
1da177e4 162 */
abd06505
BH		 163#ifdef CONFIG_PPC32
164#define PT_MAX_PUT_REG PT_MQ
165#else
166#define PT_MAX_PUT_REG PT_CCR
167#endif
1da177e4 168
26f77130
RM		 169static unsigned long get_user_msr(struct task_struct *task)
170{
171 return task->thread.regs->msr | task->thread.fpexc_mode;
172}
173
174static int set_user_msr(struct task_struct *task, unsigned long msr)
175{
176 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
177 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
178 return 0;
179}
180
181/*
182 * We prevent mucking around with the reserved area of trap
183 * which are used internally by the kernel.
184 */
185static int set_user_trap(struct task_struct *task, unsigned long trap)
186{
187 task->thread.regs->trap = trap & 0xfff0;
188 return 0;
189}
190
865418d8
BH		 191/*
192 * Get contents of register REGNO in task TASK.
193 */
194unsigned long ptrace_get_reg(struct task_struct *task, int regno)
195{
865418d8
BH		 196 if (task->thread.regs == NULL)
197 return -EIO;
198
26f77130
RM		 199 if (regno == PT_MSR)
200 return get_user_msr(task);
865418d8
BH		 201
202 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
203 return ((unsigned long *)task->thread.regs)[regno];
204
205 return -EIO;
206}
207
208/*
209 * Write contents of register REGNO in task TASK.
210 */
211int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
212{
213 if (task->thread.regs == NULL)
214 return -EIO;
215
26f77130
RM		 216 if (regno == PT_MSR)
217 return set_user_msr(task, data);
218 if (regno == PT_TRAP)
219 return set_user_trap(task, data);
220
221 if (regno <= PT_MAX_PUT_REG) {
865418d8
BH		 222 ((unsigned long *)task->thread.regs)[regno] = data;
223 return 0;
224 }
225 return -EIO;
226}
227
44dd3f50
RM		 228static int gpr_get(struct task_struct *target, const struct user_regset *regset,
229 unsigned int pos, unsigned int count,
230 void *kbuf, void __user *ubuf)
231{
a71f5d5d 232 int i, ret;
44dd3f50
RM		 233
234 if (target->thread.regs == NULL)
235 return -EIO;
236
a71f5d5d
MW		 237 if (!FULL_REGS(target->thread.regs)) {
238 /* We have a partial register set. Fill 14-31 with bogus values */
239 for (i = 14; i < 32; i++)
240 target->thread.regs->gpr[i] = NV_REG_POISON;
241 }
44dd3f50
RM		 242
243 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
244 target->thread.regs,
245 0, offsetof(struct pt_regs, msr));
246 if (!ret) {
247 unsigned long msr = get_user_msr(target);
248 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
249 offsetof(struct pt_regs, msr),
250 offsetof(struct pt_regs, msr) +
251 sizeof(msr));
252 }
253
254 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
255 offsetof(struct pt_regs, msr) + sizeof(long));
256
257 if (!ret)
258 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
259 &target->thread.regs->orig_gpr3,
260 offsetof(struct pt_regs, orig_gpr3),
261 sizeof(struct pt_regs));
262 if (!ret)
263 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
264 sizeof(struct pt_regs), -1);
265
266 return ret;
267}
268
269static int gpr_set(struct task_struct *target, const struct user_regset *regset,
270 unsigned int pos, unsigned int count,
271 const void *kbuf, const void __user *ubuf)
272{
273 unsigned long reg;
274 int ret;
275
276 if (target->thread.regs == NULL)
277 return -EIO;
278
279 CHECK_FULL_REGS(target->thread.regs);
280
281 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
282 target->thread.regs,
283 0, PT_MSR * sizeof(reg));
284
285 if (!ret && count > 0) {
286 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
287 PT_MSR * sizeof(reg),
288 (PT_MSR + 1) * sizeof(reg));
289 if (!ret)
290 ret = set_user_msr(target, reg);
291 }
292
293 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
294 offsetof(struct pt_regs, msr) + sizeof(long));
295
296 if (!ret)
297 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
298 &target->thread.regs->orig_gpr3,
299 PT_ORIG_R3 * sizeof(reg),
300 (PT_MAX_PUT_REG + 1) * sizeof(reg));
301
302 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
303 ret = user_regset_copyin_ignore(
304 &pos, &count, &kbuf, &ubuf,
305 (PT_MAX_PUT_REG + 1) * sizeof(reg),
306 PT_TRAP * sizeof(reg));
307
308 if (!ret && count > 0) {
309 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
310 PT_TRAP * sizeof(reg),
311 (PT_TRAP + 1) * sizeof(reg));
312 if (!ret)
313 ret = set_user_trap(target, reg);
314 }
315
316 if (!ret)
317 ret = user_regset_copyin_ignore(
318 &pos, &count, &kbuf, &ubuf,
319 (PT_TRAP + 1) * sizeof(reg), -1);
320
321 return ret;
322}
865418d8 323
f65255e8
RM		 324static int fpr_get(struct task_struct *target, const struct user_regset *regset,
325 unsigned int pos, unsigned int count,
326 void *kbuf, void __user *ubuf)
327{
c6e6771b
MN		 328#ifdef CONFIG_VSX
329 double buf[33];
330 int i;
331#endif
f65255e8
RM		 332 flush_fp_to_thread(target);
333
c6e6771b
MN		 334#ifdef CONFIG_VSX
335 /* copy to local buffer then write that out */
336 for (i = 0; i < 32 ; i++)
337 buf[i] = target->thread.TS_FPR(i);
338 memcpy(&buf[32], &target->thread.fpscr, sizeof(double));
339 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
340
341#else
f65255e8 342 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
9c75a31c 343 offsetof(struct thread_struct, TS_FPR(32)));
f65255e8
RM		 344
345 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
346 &target->thread.fpr, 0, -1);
c6e6771b 347#endif
f65255e8
RM		 348}
349
350static int fpr_set(struct task_struct *target, const struct user_regset *regset,
351 unsigned int pos, unsigned int count,
352 const void *kbuf, const void __user *ubuf)
353{
c6e6771b
MN		 354#ifdef CONFIG_VSX
355 double buf[33];
356 int i;
357#endif
f65255e8
RM		 358 flush_fp_to_thread(target);
359
c6e6771b
MN		 360#ifdef CONFIG_VSX
361 /* copy to local buffer then write that out */
362 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
363 if (i)
364 return i;
365 for (i = 0; i < 32 ; i++)
366 target->thread.TS_FPR(i) = buf[i];
367 memcpy(&target->thread.fpscr, &buf[32], sizeof(double));
368 return 0;
369#else
f65255e8 370 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
9c75a31c 371 offsetof(struct thread_struct, TS_FPR(32)));
f65255e8
RM		 372
373 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
374 &target->thread.fpr, 0, -1);
c6e6771b 375#endif
f65255e8
RM		 376}
377
865418d8
BH		 378#ifdef CONFIG_ALTIVEC
379/*
380 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
381 * The transfer totals 34 quadword. Quadwords 0-31 contain the
382 * corresponding vector registers. Quadword 32 contains the vscr as the
383 * last word (offset 12) within that quadword. Quadword 33 contains the
384 * vrsave as the first word (offset 0) within the quadword.
385 *
386 * This definition of the VMX state is compatible with the current PPC32
387 * ptrace interface. This allows signal handling and ptrace to use the
388 * same structures. This also simplifies the implementation of a bi-arch
389 * (combined (32- and 64-bit) gdb.
390 */
391
3caf06c6
RM		 392static int vr_active(struct task_struct *target,
393 const struct user_regset *regset)
394{
395 flush_altivec_to_thread(target);
396 return target->thread.used_vr ? regset->n : 0;
397}
398
399static int vr_get(struct task_struct *target, const struct user_regset *regset,
400 unsigned int pos, unsigned int count,
401 void *kbuf, void __user *ubuf)
402{
403 int ret;
404
405 flush_altivec_to_thread(target);
406
407 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
408 offsetof(struct thread_struct, vr[32]));
409
410 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
411 &target->thread.vr, 0,
412 33 * sizeof(vector128));
413 if (!ret) {
414 /*
415 * Copy out only the low-order word of vrsave.
416 */
417 union {
418 elf_vrreg_t reg;
419 u32 word;
420 } vrsave;
421 memset(&vrsave, 0, sizeof(vrsave));
422 vrsave.word = target->thread.vrsave;
423 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
424 33 * sizeof(vector128), -1);
425 }
426
427 return ret;
428}
429
430static int vr_set(struct task_struct *target, const struct user_regset *regset,
431 unsigned int pos, unsigned int count,
432 const void *kbuf, const void __user *ubuf)
433{
434 int ret;
435
436 flush_altivec_to_thread(target);
437
438 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
439 offsetof(struct thread_struct, vr[32]));
440
441 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
442 &target->thread.vr, 0, 33 * sizeof(vector128));
443 if (!ret && count > 0) {
444 /*
445 * We use only the first word of vrsave.
446 */
447 union {
448 elf_vrreg_t reg;
449 u32 word;
450 } vrsave;
451 memset(&vrsave, 0, sizeof(vrsave));
452 vrsave.word = target->thread.vrsave;
453 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
454 33 * sizeof(vector128), -1);
455 if (!ret)
456 target->thread.vrsave = vrsave.word;
457 }
458
459 return ret;
460}
865418d8
BH		 461#endif /* CONFIG_ALTIVEC */
462
ce48b210
MN		 463#ifdef CONFIG_VSX
464/*
465 * Currently to set and and get all the vsx state, you need to call
466 * the fp and VMX calls aswell. This only get/sets the lower 32
467 * 128bit VSX registers.
468 */
469
470static int vsr_active(struct task_struct *target,
471 const struct user_regset *regset)
472{
473 flush_vsx_to_thread(target);
474 return target->thread.used_vsr ? regset->n : 0;
475}
476
477static int vsr_get(struct task_struct *target, const struct user_regset *regset,
478 unsigned int pos, unsigned int count,
479 void *kbuf, void __user *ubuf)
480{
f3e909c2
MN		 481 double buf[32];
482 int ret, i;
ce48b210
MN		 483
484 flush_vsx_to_thread(target);
485
f3e909c2 486 for (i = 0; i < 32 ; i++)
7d2a175b 487 buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET];
ce48b210 488 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
f3e909c2 489 buf, 0, 32 * sizeof(double));
ce48b210
MN		 490
491 return ret;
492}
493
494static int vsr_set(struct task_struct *target, const struct user_regset *regset,
495 unsigned int pos, unsigned int count,
496 const void *kbuf, const void __user *ubuf)
497{
f3e909c2
MN		 498 double buf[32];
499 int ret,i;
ce48b210
MN		 500
501 flush_vsx_to_thread(target);
502
503 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
f3e909c2
MN		 504 buf, 0, 32 * sizeof(double));
505 for (i = 0; i < 32 ; i++)
7d2a175b 506 target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
f3e909c2 507
ce48b210
MN		 508
509 return ret;
510}
511#endif /* CONFIG_VSX */
512
865418d8
BH		 513#ifdef CONFIG_SPE
514
515/*
516 * For get_evrregs/set_evrregs functions 'data' has the following layout:
517 *
518 * struct {
519 * u32 evr[32];
520 * u64 acc;
521 * u32 spefscr;
522 * }
523 */
524
a4e4b175
RM		 525static int evr_active(struct task_struct *target,
526 const struct user_regset *regset)
865418d8 527{
a4e4b175
RM		 528 flush_spe_to_thread(target);
529 return target->thread.used_spe ? regset->n : 0;
530}
865418d8 531
a4e4b175
RM		 532static int evr_get(struct task_struct *target, const struct user_regset *regset,
533 unsigned int pos, unsigned int count,
534 void *kbuf, void __user *ubuf)
535{
536 int ret;
865418d8 537
a4e4b175 538 flush_spe_to_thread(target);
865418d8 539
a4e4b175
RM		 540 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
541 &target->thread.evr,
542 0, sizeof(target->thread.evr));
865418d8 543
a4e4b175
RM		 544 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
545 offsetof(struct thread_struct, spefscr));
546
547 if (!ret)
548 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
549 &target->thread.acc,
550 sizeof(target->thread.evr), -1);
551
552 return ret;
553}
554
555static int evr_set(struct task_struct *target, const struct user_regset *regset,
556 unsigned int pos, unsigned int count,
557 const void *kbuf, const void __user *ubuf)
558{
559 int ret;
560
561 flush_spe_to_thread(target);
562
563 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
564 &target->thread.evr,
565 0, sizeof(target->thread.evr));
865418d8 566
a4e4b175
RM		 567 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
568 offsetof(struct thread_struct, spefscr));
569
570 if (!ret)
571 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
572 &target->thread.acc,
573 sizeof(target->thread.evr), -1);
574
575 return ret;
865418d8 576}
865418d8
BH		 577#endif /* CONFIG_SPE */
578
579
80fdf470
RM		 580/*
581 * These are our native regset flavors.
582 */
583enum powerpc_regset {
584 REGSET_GPR,
585 REGSET_FPR,
586#ifdef CONFIG_ALTIVEC
587 REGSET_VMX,
588#endif
ce48b210
MN		 589#ifdef CONFIG_VSX
590 REGSET_VSX,
591#endif
80fdf470
RM		 592#ifdef CONFIG_SPE
593 REGSET_SPE,
594#endif
595};
596
597static const struct user_regset native_regsets[] = {
598 [REGSET_GPR] = {
599 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
600 .size = sizeof(long), .align = sizeof(long),
601 .get = gpr_get, .set = gpr_set
602 },
603 [REGSET_FPR] = {
604 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
605 .size = sizeof(double), .align = sizeof(double),
606 .get = fpr_get, .set = fpr_set
607 },
608#ifdef CONFIG_ALTIVEC
609 [REGSET_VMX] = {
610 .core_note_type = NT_PPC_VMX, .n = 34,
611 .size = sizeof(vector128), .align = sizeof(vector128),
612 .active = vr_active, .get = vr_get, .set = vr_set
613 },
614#endif
ce48b210
MN		 615#ifdef CONFIG_VSX
616 [REGSET_VSX] = {
f3e909c2
MN		 617 .core_note_type = NT_PPC_VSX, .n = 32,
618 .size = sizeof(double), .align = sizeof(double),
ce48b210
MN		 619 .active = vsr_active, .get = vsr_get, .set = vsr_set
620 },
621#endif
80fdf470
RM		 622#ifdef CONFIG_SPE
623 [REGSET_SPE] = {
624 .n = 35,
625 .size = sizeof(u32), .align = sizeof(u32),
626 .active = evr_active, .get = evr_get, .set = evr_set
627 },
628#endif
629};
630
631static const struct user_regset_view user_ppc_native_view = {
632 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
633 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
634};
635
fa8f5cb0
RM		 636#ifdef CONFIG_PPC64
637#include <linux/compat.h>
638
639static int gpr32_get(struct task_struct *target,
640 const struct user_regset *regset,
641 unsigned int pos, unsigned int count,
642 void *kbuf, void __user *ubuf)
643{
644 const unsigned long *regs = &target->thread.regs->gpr[0];
645 compat_ulong_t *k = kbuf;
646 compat_ulong_t __user *u = ubuf;
647 compat_ulong_t reg;
a71f5d5d 648 int i;
fa8f5cb0
RM		 649
650 if (target->thread.regs == NULL)
651 return -EIO;
652
a71f5d5d
MW		 653 if (!FULL_REGS(target->thread.regs)) {
654 /* We have a partial register set. Fill 14-31 with bogus values */
655 for (i = 14; i < 32; i++)
656 target->thread.regs->gpr[i] = NV_REG_POISON;
657 }
fa8f5cb0
RM		 658
659 pos /= sizeof(reg);
660 count /= sizeof(reg);
661
662 if (kbuf)
663 for (; count > 0 && pos < PT_MSR; --count)
664 *k++ = regs[pos++];
665 else
666 for (; count > 0 && pos < PT_MSR; --count)
667 if (__put_user((compat_ulong_t) regs[pos++], u++))
668 return -EFAULT;
669
670 if (count > 0 && pos == PT_MSR) {
671 reg = get_user_msr(target);
672 if (kbuf)
673 *k++ = reg;
674 else if (__put_user(reg, u++))
675 return -EFAULT;
676 ++pos;
677 --count;
678 }
679
680 if (kbuf)
681 for (; count > 0 && pos < PT_REGS_COUNT; --count)
682 *k++ = regs[pos++];
683 else
684 for (; count > 0 && pos < PT_REGS_COUNT; --count)
685 if (__put_user((compat_ulong_t) regs[pos++], u++))
686 return -EFAULT;
687
688 kbuf = k;
689 ubuf = u;
690 pos *= sizeof(reg);
691 count *= sizeof(reg);
692 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
693 PT_REGS_COUNT * sizeof(reg), -1);
694}
695
696static int gpr32_set(struct task_struct *target,
697 const struct user_regset *regset,
698 unsigned int pos, unsigned int count,
699 const void *kbuf, const void __user *ubuf)
700{
701 unsigned long *regs = &target->thread.regs->gpr[0];
702 const compat_ulong_t *k = kbuf;
703 const compat_ulong_t __user *u = ubuf;
704 compat_ulong_t reg;
705
706 if (target->thread.regs == NULL)
707 return -EIO;
708
709 CHECK_FULL_REGS(target->thread.regs);
710
711 pos /= sizeof(reg);
712 count /= sizeof(reg);
713
714 if (kbuf)
715 for (; count > 0 && pos < PT_MSR; --count)
716 regs[pos++] = *k++;
717 else
718 for (; count > 0 && pos < PT_MSR; --count) {
719 if (__get_user(reg, u++))
720 return -EFAULT;
721 regs[pos++] = reg;
722 }
723
724
725 if (count > 0 && pos == PT_MSR) {
726 if (kbuf)
727 reg = *k++;
728 else if (__get_user(reg, u++))
729 return -EFAULT;
730 set_user_msr(target, reg);
731 ++pos;
732 --count;
733 }
734
c2372eb9 735 if (kbuf) {
fa8f5cb0
RM		 736 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
737 regs[pos++] = *k++;
c2372eb9
RM		 738 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
739 ++k;
740 } else {
fa8f5cb0
RM		 741 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
742 if (__get_user(reg, u++))
743 return -EFAULT;
744 regs[pos++] = reg;
745 }
c2372eb9
RM		 746 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
747 if (__get_user(reg, u++))
748 return -EFAULT;
749 }
fa8f5cb0
RM		 750
751 if (count > 0 && pos == PT_TRAP) {
752 if (kbuf)
753 reg = *k++;
754 else if (__get_user(reg, u++))
755 return -EFAULT;
756 set_user_trap(target, reg);
757 ++pos;
758 --count;
759 }
760
761 kbuf = k;
762 ubuf = u;
763 pos *= sizeof(reg);
764 count *= sizeof(reg);
765 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
766 (PT_TRAP + 1) * sizeof(reg), -1);
767}
768
769/*
770 * These are the regset flavors matching the CONFIG_PPC32 native set.
771 */
772static const struct user_regset compat_regsets[] = {
773 [REGSET_GPR] = {
774 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
775 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
776 .get = gpr32_get, .set = gpr32_set
777 },
778 [REGSET_FPR] = {
779 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
780 .size = sizeof(double), .align = sizeof(double),
781 .get = fpr_get, .set = fpr_set
782 },
783#ifdef CONFIG_ALTIVEC
784 [REGSET_VMX] = {
785 .core_note_type = NT_PPC_VMX, .n = 34,
786 .size = sizeof(vector128), .align = sizeof(vector128),
787 .active = vr_active, .get = vr_get, .set = vr_set
788 },
789#endif
790#ifdef CONFIG_SPE
791 [REGSET_SPE] = {
24f1a849 792 .core_note_type = NT_PPC_SPE, .n = 35,
fa8f5cb0
RM		 793 .size = sizeof(u32), .align = sizeof(u32),
794 .active = evr_active, .get = evr_get, .set = evr_set
795 },
796#endif
797};
798
799static const struct user_regset_view user_ppc_compat_view = {
800 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
801 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
802};
803#endif /* CONFIG_PPC64 */
804
80fdf470
RM		 805const struct user_regset_view *task_user_regset_view(struct task_struct *task)
806{
fa8f5cb0
RM		 807#ifdef CONFIG_PPC64
808 if (test_tsk_thread_flag(task, TIF_32BIT))
809 return &user_ppc_compat_view;
810#endif
80fdf470
RM		 811 return &user_ppc_native_view;
812}
813
814
2a84b0d7 815void user_enable_single_step(struct task_struct *task)
865418d8
BH		 816{
817 struct pt_regs *regs = task->thread.regs;
818
819 if (regs != NULL) {
172ae2e7 820#ifdef CONFIG_PPC_ADV_DEBUG_REGS
ec097c84 821 task->thread.dbcr0 &= ~DBCR0_BT;
d6a61bfc 822 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
865418d8
BH		 823 regs->msr |= MSR_DE;
824#else
ec097c84 825 regs->msr &= ~MSR_BE;
865418d8
BH		 826 regs->msr |= MSR_SE;
827#endif
828 }
829 set_tsk_thread_flag(task, TIF_SINGLESTEP);
830}
831
ec097c84
RM		 832void user_enable_block_step(struct task_struct *task)
833{
834 struct pt_regs *regs = task->thread.regs;
835
836 if (regs != NULL) {
172ae2e7 837#ifdef CONFIG_PPC_ADV_DEBUG_REGS
ec097c84
RM		 838 task->thread.dbcr0 &= ~DBCR0_IC;
839 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
840 regs->msr |= MSR_DE;
841#else
842 regs->msr &= ~MSR_SE;
843 regs->msr |= MSR_BE;
844#endif
845 }
846 set_tsk_thread_flag(task, TIF_SINGLESTEP);
847}
848
2a84b0d7 849void user_disable_single_step(struct task_struct *task)
865418d8
BH		 850{
851 struct pt_regs *regs = task->thread.regs;
852
853 if (regs != NULL) {
172ae2e7 854#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3bffb652
DK		 855 /*
856 * The logic to disable single stepping should be as
857 * simple as turning off the Instruction Complete flag.
858 * And, after doing so, if all debug flags are off, turn
859 * off DBCR0(IDM) and MSR(DE) .... Torez
860 */
861 task->thread.dbcr0 &= ~DBCR0_IC;
862 /*
863 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
864 */
865 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
866 task->thread.dbcr1)) {
867 /*
868 * All debug events were off.....
869 */
870 task->thread.dbcr0 &= ~DBCR0_IDM;
28477fb1
DK		 871 regs->msr &= ~MSR_DE;
872 }
865418d8 873#else
ec097c84 874 regs->msr &= ~(MSR_SE | MSR_BE);
865418d8
BH		 875#endif
876 }
877 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
878}
879
5aae8a53
P		 880#ifdef CONFIG_HAVE_HW_BREAKPOINT
881void ptrace_triggered(struct perf_event *bp, int nmi,
882 struct perf_sample_data *data, struct pt_regs *regs)
883{
884 struct perf_event_attr attr;
885
886 /*
887 * Disable the breakpoint request here since ptrace has defined a
888 * one-shot behaviour for breakpoint exceptions in PPC64.
889 * The SIGTRAP signal is generated automatically for us in do_dabr().
890 * We don't have to do anything about that here
891 */
892 attr = bp->attr;
893 attr.disabled = true;
894 modify_user_hw_breakpoint(bp, &attr);
895}
896#endif /* CONFIG_HAVE_HW_BREAKPOINT */
897
d6a61bfc 898int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
abd06505
BH		 899 unsigned long data)
900{
5aae8a53
P		 901#ifdef CONFIG_HAVE_HW_BREAKPOINT
902 int ret;
903 struct thread_struct *thread = &(task->thread);
904 struct perf_event *bp;
905 struct perf_event_attr attr;
906#endif /* CONFIG_HAVE_HW_BREAKPOINT */
907
d6a61bfc
LM		 908 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
909 * For embedded processors we support one DAC and no IAC's at the
910 * moment.
911 */
abd06505
BH		 912 if (addr > 0)
913 return -EINVAL;
914
2325f0a0 915 /* The bottom 3 bits in dabr are flags */
abd06505
BH		 916 if ((data & ~0x7UL) >= TASK_SIZE)
917 return -EIO;
918
172ae2e7 919#ifndef CONFIG_PPC_ADV_DEBUG_REGS
d6a61bfc
LM		 920 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
921 * It was assumed, on previous implementations, that 3 bits were
922 * passed together with the data address, fitting the design of the
923 * DABR register, as follows:
924 *
925 * bit 0: Read flag
926 * bit 1: Write flag
927 * bit 2: Breakpoint translation
928 *
929 * Thus, we use them here as so.
930 */
931
932 /* Ensure breakpoint translation bit is set */
abd06505
BH		 933 if (data && !(data & DABR_TRANSLATION))
934 return -EIO;
5aae8a53
P		 935#ifdef CONFIG_HAVE_HW_BREAKPOINT
936 bp = thread->ptrace_bps[0];
937 if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
938 if (bp) {
939 unregister_hw_breakpoint(bp);
940 thread->ptrace_bps[0] = NULL;
941 }
942 return 0;
943 }
944 if (bp) {
945 attr = bp->attr;
946 attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
947 arch_bp_generic_fields(data &
948 (DABR_DATA_WRITE | DABR_DATA_READ),
949 &attr.bp_type);
950 ret = modify_user_hw_breakpoint(bp, &attr);
951 if (ret)
952 return ret;
953 thread->ptrace_bps[0] = bp;
954 thread->dabr = data;
955 return 0;
956 }
957
958 /* Create a new breakpoint request if one doesn't exist already */
959 hw_breakpoint_init(&attr);
960 attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
961 arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
962 &attr.bp_type);
963
964 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
965 ptrace_triggered, task);
966 if (IS_ERR(bp)) {
967 thread->ptrace_bps[0] = NULL;
968 return PTR_ERR(bp);
969 }
970
971#endif /* CONFIG_HAVE_HW_BREAKPOINT */
abd06505 972
d6a61bfc 973 /* Move contents to the DABR register */
abd06505 974 task->thread.dabr = data;
172ae2e7 975#else /* CONFIG_PPC_ADV_DEBUG_REGS */
d6a61bfc
LM		 976 /* As described above, it was assumed 3 bits were passed with the data
977 * address, but we will assume only the mode bits will be passed
978 * as to not cause alignment restrictions for DAC-based processors.
979 */
980
981 /* DAC's hold the whole address without any mode flags */
3bffb652
DK		 982 task->thread.dac1 = data & ~0x3UL;
983
984 if (task->thread.dac1 == 0) {
985 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
986 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
987 task->thread.dbcr1)) {
988 task->thread.regs->msr &= ~MSR_DE;
989 task->thread.dbcr0 &= ~DBCR0_IDM;
990 }
d6a61bfc
LM		 991 return 0;
992 }
993
994 /* Read or Write bits must be set */
995
996 if (!(data & 0x3UL))
997 return -EINVAL;
998
999 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
1000 register */
3bffb652 1001 task->thread.dbcr0 |= DBCR0_IDM;
d6a61bfc
LM		 1002
1003 /* Check for write and read flags and set DBCR0
1004 accordingly */
3bffb652 1005 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
d6a61bfc 1006 if (data & 0x1UL)
3bffb652 1007 dbcr_dac(task) |= DBCR_DAC1R;
d6a61bfc 1008 if (data & 0x2UL)
3bffb652 1009 dbcr_dac(task) |= DBCR_DAC1W;
d6a61bfc 1010 task->thread.regs->msr |= MSR_DE;
172ae2e7 1011#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
abd06505
BH		 1012 return 0;
1013}
abd06505 1014
1da177e4
LT		 1015/*
1016 * Called by kernel/ptrace.c when detaching..
1017 *
1018 * Make sure single step bits etc are not set.
1019 */
1020void ptrace_disable(struct task_struct *child)
1021{
1022 /* make sure the single step bit is not set. */
2a84b0d7 1023 user_disable_single_step(child);
1da177e4
LT		 1024}
1025
3bffb652
DK		 1026#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1027static long set_intruction_bp(struct task_struct *child,
1028 struct ppc_hw_breakpoint *bp_info)
1029{
1030 int slot;
1031 int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
1032 int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
1033 int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
1034 int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
1035
1036 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1037 slot2_in_use = 1;
1038 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1039 slot4_in_use = 1;
1040
1041 if (bp_info->addr >= TASK_SIZE)
1042 return -EIO;
1043
1044 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1045
1046 /* Make sure range is valid. */
1047 if (bp_info->addr2 >= TASK_SIZE)
1048 return -EIO;
1049
1050 /* We need a pair of IAC regsisters */
1051 if ((!slot1_in_use) && (!slot2_in_use)) {
1052 slot = 1;
1053 child->thread.iac1 = bp_info->addr;
1054 child->thread.iac2 = bp_info->addr2;
1055 child->thread.dbcr0 |= DBCR0_IAC1;
1056 if (bp_info->addr_mode ==
1057 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1058 dbcr_iac_range(child) |= DBCR_IAC12X;
1059 else
1060 dbcr_iac_range(child) |= DBCR_IAC12I;
1061#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1062 } else if ((!slot3_in_use) && (!slot4_in_use)) {
1063 slot = 3;
1064 child->thread.iac3 = bp_info->addr;
1065 child->thread.iac4 = bp_info->addr2;
1066 child->thread.dbcr0 |= DBCR0_IAC3;
1067 if (bp_info->addr_mode ==
1068 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1069 dbcr_iac_range(child) |= DBCR_IAC34X;
1070 else
1071 dbcr_iac_range(child) |= DBCR_IAC34I;
1072#endif
1073 } else
1074 return -ENOSPC;
1075 } else {
1076 /* We only need one. If possible leave a pair free in
1077 * case a range is needed later
1078 */
1079 if (!slot1_in_use) {
1080 /*
1081 * Don't use iac1 if iac1-iac2 are free and either
1082 * iac3 or iac4 (but not both) are free
1083 */
1084 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
1085 slot = 1;
1086 child->thread.iac1 = bp_info->addr;
1087 child->thread.dbcr0 |= DBCR0_IAC1;
1088 goto out;
1089 }
1090 }
1091 if (!slot2_in_use) {
1092 slot = 2;
1093 child->thread.iac2 = bp_info->addr;
1094 child->thread.dbcr0 |= DBCR0_IAC2;
1095#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1096 } else if (!slot3_in_use) {
1097 slot = 3;
1098 child->thread.iac3 = bp_info->addr;
1099 child->thread.dbcr0 |= DBCR0_IAC3;
1100 } else if (!slot4_in_use) {
1101 slot = 4;
1102 child->thread.iac4 = bp_info->addr;
1103 child->thread.dbcr0 |= DBCR0_IAC4;
1104#endif
1105 } else
1106 return -ENOSPC;
1107 }
1108out:
1109 child->thread.dbcr0 |= DBCR0_IDM;
1110 child->thread.regs->msr |= MSR_DE;
1111
1112 return slot;
1113}
1114
1115static int del_instruction_bp(struct task_struct *child, int slot)
1116{
1117 switch (slot) {
1118 case 1:
30124d11 1119 if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
3bffb652
DK		 1120 return -ENOENT;
1121
1122 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
1123 /* address range - clear slots 1 & 2 */
1124 child->thread.iac2 = 0;
1125 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
1126 }
1127 child->thread.iac1 = 0;
1128 child->thread.dbcr0 &= ~DBCR0_IAC1;
1129 break;
1130 case 2:
30124d11 1131 if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
3bffb652
DK		 1132 return -ENOENT;
1133
1134 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1135 /* used in a range */
1136 return -EINVAL;
1137 child->thread.iac2 = 0;
1138 child->thread.dbcr0 &= ~DBCR0_IAC2;
1139 break;
1140#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1141 case 3:
30124d11 1142 if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
3bffb652
DK		 1143 return -ENOENT;
1144
1145 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
1146 /* address range - clear slots 3 & 4 */
1147 child->thread.iac4 = 0;
1148 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
1149 }
1150 child->thread.iac3 = 0;
1151 child->thread.dbcr0 &= ~DBCR0_IAC3;
1152 break;
1153 case 4:
30124d11 1154 if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
3bffb652
DK		 1155 return -ENOENT;
1156
1157 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1158 /* Used in a range */
1159 return -EINVAL;
1160 child->thread.iac4 = 0;
1161 child->thread.dbcr0 &= ~DBCR0_IAC4;
1162 break;
1163#endif
1164 default:
1165 return -EINVAL;
1166 }
1167 return 0;
1168}
1169
1170static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1171{
1172 int byte_enable =
1173 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
1174 & 0xf;
1175 int condition_mode =
1176 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
1177 int slot;
1178
1179 if (byte_enable && (condition_mode == 0))
1180 return -EINVAL;
1181
1182 if (bp_info->addr >= TASK_SIZE)
1183 return -EIO;
1184
1185 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
1186 slot = 1;
1187 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1188 dbcr_dac(child) |= DBCR_DAC1R;
1189 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1190 dbcr_dac(child) |= DBCR_DAC1W;
1191 child->thread.dac1 = (unsigned long)bp_info->addr;
1192#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1193 if (byte_enable) {
1194 child->thread.dvc1 =
1195 (unsigned long)bp_info->condition_value;
1196 child->thread.dbcr2 |=
1197 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
1198 (condition_mode << DBCR2_DVC1M_SHIFT));
1199 }
1200#endif
1201#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1202 } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1203 /* Both dac1 and dac2 are part of a range */
1204 return -ENOSPC;
1205#endif
1206 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
1207 slot = 2;
1208 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1209 dbcr_dac(child) |= DBCR_DAC2R;
1210 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1211 dbcr_dac(child) |= DBCR_DAC2W;
1212 child->thread.dac2 = (unsigned long)bp_info->addr;
1213#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1214 if (byte_enable) {
1215 child->thread.dvc2 =
1216 (unsigned long)bp_info->condition_value;
1217 child->thread.dbcr2 |=
1218 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
1219 (condition_mode << DBCR2_DVC2M_SHIFT));
1220 }
1221#endif
1222 } else
1223 return -ENOSPC;
1224 child->thread.dbcr0 |= DBCR0_IDM;
1225 child->thread.regs->msr |= MSR_DE;
1226
1227 return slot + 4;
1228}
1229
1230static int del_dac(struct task_struct *child, int slot)
1231{
1232 if (slot == 1) {
30124d11 1233 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
3bffb652
DK		 1234 return -ENOENT;
1235
1236 child->thread.dac1 = 0;
1237 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1238#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1239 if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1240 child->thread.dac2 = 0;
1241 child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1242 }
1243 child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
1244#endif
1245#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1246 child->thread.dvc1 = 0;
1247#endif
1248 } else if (slot == 2) {
30124d11 1249 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
3bffb652
DK		 1250 return -ENOENT;
1251
1252#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1253 if (child->thread.dbcr2 & DBCR2_DAC12MODE)
1254 /* Part of a range */
1255 return -EINVAL;
1256 child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
1257#endif
1258#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1259 child->thread.dvc2 = 0;
1260#endif
1261 child->thread.dac2 = 0;
1262 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1263 } else
1264 return -EINVAL;
1265
1266 return 0;
1267}
1268#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1269
1270#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1271static int set_dac_range(struct task_struct *child,
1272 struct ppc_hw_breakpoint *bp_info)
1273{
1274 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
1275
1276 /* We don't allow range watchpoints to be used with DVC */
1277 if (bp_info->condition_mode)
1278 return -EINVAL;
1279
1280 /*
1281 * Best effort to verify the address range. The user/supervisor bits
1282 * prevent trapping in kernel space, but let's fail on an obvious bad
1283 * range. The simple test on the mask is not fool-proof, and any
1284 * exclusive range will spill over into kernel space.
1285 */
1286 if (bp_info->addr >= TASK_SIZE)
1287 return -EIO;
1288 if (mode == PPC_BREAKPOINT_MODE_MASK) {
1289 /*
1290 * dac2 is a bitmask. Don't allow a mask that makes a
1291 * kernel space address from a valid dac1 value
1292 */
1293 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
1294 return -EIO;
1295 } else {
1296 /*
1297 * For range breakpoints, addr2 must also be a valid address
1298 */
1299 if (bp_info->addr2 >= TASK_SIZE)
1300 return -EIO;
1301 }
1302
1303 if (child->thread.dbcr0 &
1304 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
1305 return -ENOSPC;
1306
1307 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1308 child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
1309 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1310 child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
1311 child->thread.dac1 = bp_info->addr;
1312 child->thread.dac2 = bp_info->addr2;
1313 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
1314 child->thread.dbcr2 |= DBCR2_DAC12M;
1315 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1316 child->thread.dbcr2 |= DBCR2_DAC12MX;
1317 else /* PPC_BREAKPOINT_MODE_MASK */
1318 child->thread.dbcr2 |= DBCR2_DAC12MM;
1319 child->thread.regs->msr |= MSR_DE;
1320
1321 return 5;
1322}
1323#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
1324
3162d92d
DK		 1325static long ppc_set_hwdebug(struct task_struct *child,
1326 struct ppc_hw_breakpoint *bp_info)
1327{
4dfbf290
AS		 1328#ifndef CONFIG_PPC_ADV_DEBUG_REGS
1329 unsigned long dabr;
1330#endif
1331
3bffb652
DK		 1332 if (bp_info->version != 1)
1333 return -ENOTSUPP;
1334#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1335 /*
1336 * Check for invalid flags and combinations
1337 */
1338 if ((bp_info->trigger_type == 0) ||
1339 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
1340 PPC_BREAKPOINT_TRIGGER_RW)) ||
1341 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
1342 (bp_info->condition_mode &
1343 ~(PPC_BREAKPOINT_CONDITION_MODE |
1344 PPC_BREAKPOINT_CONDITION_BE_ALL)))
1345 return -EINVAL;
1346#if CONFIG_PPC_ADV_DEBUG_DVCS == 0
1347 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1348 return -EINVAL;
1349#endif
1350
1351 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
1352 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
1353 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
1354 return -EINVAL;
1355 return set_intruction_bp(child, bp_info);
1356 }
1357 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
1358 return set_dac(child, bp_info);
1359
1360#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1361 return set_dac_range(child, bp_info);
1362#else
1363 return -EINVAL;
1364#endif
1365#else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
3162d92d 1366 /*
3bffb652 1367 * We only support one data breakpoint
3162d92d 1368 */
4dfbf290
AS		 1369 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
1370 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
1371 bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT ||
1372 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
3162d92d
DK		 1373 return -EINVAL;
1374
1375 if (child->thread.dabr)
1376 return -ENOSPC;
1377
1378 if ((unsigned long)bp_info->addr >= TASK_SIZE)
1379 return -EIO;
1380
4dfbf290
AS		 1381 dabr = (unsigned long)bp_info->addr & ~7UL;
1382 dabr |= DABR_TRANSLATION;
1383 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1384 dabr |= DABR_DATA_READ;
1385 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1386 dabr |= DABR_DATA_WRITE;
1387
1388 child->thread.dabr = dabr;
3bffb652 1389
3162d92d 1390 return 1;
3bffb652 1391#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
3162d92d
DK		 1392}
1393
1394static long ppc_del_hwdebug(struct task_struct *child, long addr, long data)
1395{
3bffb652
DK		 1396#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1397 int rc;
1398
1399 if (data <= 4)
1400 rc = del_instruction_bp(child, (int)data);
1401 else
1402 rc = del_dac(child, (int)data - 4);
1403
1404 if (!rc) {
1405 if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
1406 child->thread.dbcr1)) {
1407 child->thread.dbcr0 &= ~DBCR0_IDM;
1408 child->thread.regs->msr &= ~MSR_DE;
1409 }
1410 }
1411 return rc;
1412#else
3162d92d
DK		 1413 if (data != 1)
1414 return -EINVAL;
1415 if (child->thread.dabr == 0)
1416 return -ENOENT;
1417
1418 child->thread.dabr = 0;
3bffb652 1419
3162d92d 1420 return 0;
3bffb652 1421#endif
3162d92d
DK		 1422}
1423
e17666ba
BH		 1424/*
1425 * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls,
1426 * we mark them as obsolete now, they will be removed in a future version
1427 */
9b05a69e
NK		 1428static long arch_ptrace_old(struct task_struct *child, long request,
1429 unsigned long addr, unsigned long data)
e17666ba 1430{
f68d2048
NK		 1431 void __user *datavp = (void __user *) data;
1432
c391cd00
RM		 1433 switch (request) {
1434 case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */
1435 return copy_regset_to_user(child, &user_ppc_native_view,
1436 REGSET_GPR, 0, 32 * sizeof(long),
f68d2048 1437 datavp);
c391cd00
RM		 1438
1439 case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */
1440 return copy_regset_from_user(child, &user_ppc_native_view,
1441 REGSET_GPR, 0, 32 * sizeof(long),
f68d2048 1442 datavp);
c391cd00
RM		 1443
1444 case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */
1445 return copy_regset_to_user(child, &user_ppc_native_view,
1446 REGSET_FPR, 0, 32 * sizeof(double),
f68d2048 1447 datavp);
c391cd00
RM		 1448
1449 case PPC_PTRACE_SETFPREGS: /* Set FPRs 0 - 31. */
1450 return copy_regset_from_user(child, &user_ppc_native_view,
1451 REGSET_FPR, 0, 32 * sizeof(double),
f68d2048 1452 datavp);
e17666ba
BH		 1453 }
1454
c391cd00 1455 return -EPERM;
e17666ba
BH		 1456}
1457
9b05a69e
NK		 1458long arch_ptrace(struct task_struct *child, long request,
1459 unsigned long addr, unsigned long data)
1da177e4 1460{
1da177e4 1461 int ret = -EPERM;
f68d2048
NK		 1462 void __user *datavp = (void __user *) data;
1463 unsigned long __user *datalp = datavp;
1da177e4 1464
1da177e4 1465 switch (request) {
1da177e4 1466 /* read the word at location addr in the USER area. */
1da177e4
LT		 1467 case PTRACE_PEEKUSR: {
1468 unsigned long index, tmp;
1469
1470 ret = -EIO;
1471 /* convert to index and check */
e8a30302 1472#ifdef CONFIG_PPC32
9b05a69e 1473 index = addr >> 2;
e8a30302
SR		 1474 if ((addr & 3) || (index > PT_FPSCR)
1475 || (child->thread.regs == NULL))
1476#else
9b05a69e 1477 index = addr >> 3;
e8a30302
SR		 1478 if ((addr & 7) || (index > PT_FPSCR))
1479#endif
1da177e4
LT		 1480 break;
1481
1482 CHECK_FULL_REGS(child->thread.regs);
1483 if (index < PT_FPR0) {
865418d8 1484 tmp = ptrace_get_reg(child, (int) index);
1da177e4 1485 } else {
e8a30302 1486 flush_fp_to_thread(child);
9c75a31c
MN		 1487 tmp = ((unsigned long *)child->thread.fpr)
1488 [TS_FPRWIDTH * (index - PT_FPR0)];
1da177e4 1489 }
f68d2048 1490 ret = put_user(tmp, datalp);
1da177e4
LT		 1491 break;
1492 }
1493
1da177e4
LT		 1494 /* write the word at location addr in the USER area */
1495 case PTRACE_POKEUSR: {
1496 unsigned long index;
1497
1498 ret = -EIO;
1499 /* convert to index and check */
e8a30302 1500#ifdef CONFIG_PPC32
9b05a69e 1501 index = addr >> 2;
e8a30302
SR		 1502 if ((addr & 3) || (index > PT_FPSCR)
1503 || (child->thread.regs == NULL))
1504#else
9b05a69e 1505 index = addr >> 3;
e8a30302
SR		 1506 if ((addr & 7) || (index > PT_FPSCR))
1507#endif
1da177e4
LT		 1508 break;
1509
1510 CHECK_FULL_REGS(child->thread.regs);
1da177e4 1511 if (index < PT_FPR0) {
865418d8 1512 ret = ptrace_put_reg(child, index, data);
1da177e4 1513 } else {
e8a30302 1514 flush_fp_to_thread(child);
9c75a31c
MN		 1515 ((unsigned long *)child->thread.fpr)
1516 [TS_FPRWIDTH * (index - PT_FPR0)] = data;
1da177e4
LT		 1517 ret = 0;
1518 }
1519 break;
1520 }
1521
3162d92d
DK		 1522 case PPC_PTRACE_GETHWDBGINFO: {
1523 struct ppc_debug_info dbginfo;
1524
1525 dbginfo.version = 1;
3bffb652
DK		 1526#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1527 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
1528 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
1529 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
1530 dbginfo.data_bp_alignment = 4;
1531 dbginfo.sizeof_condition = 4;
1532 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
1533 PPC_DEBUG_FEATURE_INSN_BP_MASK;
1534#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1535 dbginfo.features |=
1536 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
1537 PPC_DEBUG_FEATURE_DATA_BP_MASK;
1538#endif
1539#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
3162d92d
DK		 1540 dbginfo.num_instruction_bps = 0;
1541 dbginfo.num_data_bps = 1;
1542 dbginfo.num_condition_regs = 0;
1543#ifdef CONFIG_PPC64
1544 dbginfo.data_bp_alignment = 8;
1545#else
1546 dbginfo.data_bp_alignment = 4;
1547#endif
1548 dbginfo.sizeof_condition = 0;
1549 dbginfo.features = 0;
3bffb652 1550#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
3162d92d 1551
f68d2048 1552 if (!access_ok(VERIFY_WRITE, datavp,
3162d92d
DK		 1553 sizeof(struct ppc_debug_info)))
1554 return -EFAULT;
f68d2048
NK		 1555 ret = __copy_to_user(datavp, &dbginfo,
1556 sizeof(struct ppc_debug_info)) ?
3162d92d
DK		 1557 -EFAULT : 0;
1558 break;
1559 }
1560
1561 case PPC_PTRACE_SETHWDEBUG: {
1562 struct ppc_hw_breakpoint bp_info;
1563
f68d2048 1564 if (!access_ok(VERIFY_READ, datavp,
3162d92d
DK		 1565 sizeof(struct ppc_hw_breakpoint)))
1566 return -EFAULT;
f68d2048 1567 ret = __copy_from_user(&bp_info, datavp,
3162d92d
DK		 1568 sizeof(struct ppc_hw_breakpoint)) ?
1569 -EFAULT : 0;
1570 if (!ret)
1571 ret = ppc_set_hwdebug(child, &bp_info);
1572 break;
1573 }
1574
1575 case PPC_PTRACE_DELHWDEBUG: {
1576 ret = ppc_del_hwdebug(child, addr, data);
1577 break;
1578 }
1579
e8a30302
SR		 1580 case PTRACE_GET_DEBUGREG: {
1581 ret = -EINVAL;
1582 /* We only support one DABR and no IABRS at the moment */
1583 if (addr > 0)
1584 break;
3bffb652 1585#ifdef CONFIG_PPC_ADV_DEBUG_REGS
f68d2048 1586 ret = put_user(child->thread.dac1, datalp);
3bffb652 1587#else
f68d2048 1588 ret = put_user(child->thread.dabr, datalp);
3bffb652 1589#endif
e8a30302
SR		 1590 break;
1591 }
1592
1593 case PTRACE_SET_DEBUGREG:
1594 ret = ptrace_set_debugreg(child, addr, data);
1595 break;
e8a30302 1596
e17666ba
BH		 1597#ifdef CONFIG_PPC64
1598 case PTRACE_GETREGS64:
1599#endif
c391cd00
RM		 1600 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
1601 return copy_regset_to_user(child, &user_ppc_native_view,
1602 REGSET_GPR,
1603 0, sizeof(struct pt_regs),
f68d2048 1604 datavp);
e8a30302 1605
e17666ba
BH		 1606#ifdef CONFIG_PPC64
1607 case PTRACE_SETREGS64:
1608#endif
c391cd00
RM		 1609 case PTRACE_SETREGS: /* Set all gp regs in the child. */
1610 return copy_regset_from_user(child, &user_ppc_native_view,
1611 REGSET_GPR,
1612 0, sizeof(struct pt_regs),
f68d2048 1613 datavp);
c391cd00
RM		 1614
1615 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
1616 return copy_regset_to_user(child, &user_ppc_native_view,
1617 REGSET_FPR,
1618 0, sizeof(elf_fpregset_t),
f68d2048 1619 datavp);
c391cd00
RM		 1620
1621 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
1622 return copy_regset_from_user(child, &user_ppc_native_view,
1623 REGSET_FPR,
1624 0, sizeof(elf_fpregset_t),
f68d2048 1625 datavp);
e8a30302 1626
1da177e4
LT		 1627#ifdef CONFIG_ALTIVEC
1628 case PTRACE_GETVRREGS:
c391cd00
RM		 1629 return copy_regset_to_user(child, &user_ppc_native_view,
1630 REGSET_VMX,
1631 0, (33 * sizeof(vector128) +
1632 sizeof(u32)),
f68d2048 1633 datavp);
1da177e4
LT		 1634
1635 case PTRACE_SETVRREGS:
c391cd00
RM		 1636 return copy_regset_from_user(child, &user_ppc_native_view,
1637 REGSET_VMX,
1638 0, (33 * sizeof(vector128) +
1639 sizeof(u32)),
f68d2048 1640 datavp);
1da177e4 1641#endif
ce48b210
MN		 1642#ifdef CONFIG_VSX
1643 case PTRACE_GETVSRREGS:
1644 return copy_regset_to_user(child, &user_ppc_native_view,
1645 REGSET_VSX,
1ac42ef8 1646 0, 32 * sizeof(double),
f68d2048 1647 datavp);
ce48b210
MN		 1648
1649 case PTRACE_SETVSRREGS:
1650 return copy_regset_from_user(child, &user_ppc_native_view,
1651 REGSET_VSX,
1ac42ef8 1652 0, 32 * sizeof(double),
f68d2048 1653 datavp);
ce48b210 1654#endif
1da177e4
LT		 1655#ifdef CONFIG_SPE
1656 case PTRACE_GETEVRREGS:
1657 /* Get the child spe register state. */
c391cd00
RM		 1658 return copy_regset_to_user(child, &user_ppc_native_view,
1659 REGSET_SPE, 0, 35 * sizeof(u32),
f68d2048 1660 datavp);
1da177e4
LT		 1661
1662 case PTRACE_SETEVRREGS:
1663 /* Set the child spe register state. */
c391cd00
RM		 1664 return copy_regset_from_user(child, &user_ppc_native_view,
1665 REGSET_SPE, 0, 35 * sizeof(u32),
f68d2048 1666 datavp);
1da177e4
LT		 1667#endif
1668
e17666ba
BH		 1669 /* Old reverse args ptrace callss */
1670 case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */
1671 case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */
1672 case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */
1673 case PPC_PTRACE_SETFPREGS: /* Get FPRs 0 - 31. */
1674 ret = arch_ptrace_old(child, request, addr, data);
1675 break;
1676
1da177e4
LT		 1677 default:
1678 ret = ptrace_request(child, request, addr, data);
1679 break;
1680 }
1da177e4
LT		 1681 return ret;
1682}
1683
4f72c427
RM		 1684/*
1685 * We must return the syscall number to actually look up in the table.
1686 * This can be -1L to skip running any syscall at all.
1687 */
1688long do_syscall_trace_enter(struct pt_regs *regs)
1da177e4 1689{
4f72c427 1690 long ret = 0;
ea9c102c 1691
e8a30302 1692 secure_computing(regs->gpr[0]);
e8a30302 1693
4f72c427
RM		 1694 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
1695 tracehook_report_syscall_entry(regs))
1696 /*
1697 * Tracing decided this syscall should not happen.
1698 * We'll return a bogus call number to get an ENOSYS
1699 * error, but leave the original number in regs->gpr[0].
1700 */
1701 ret = -1L;
ea9c102c 1702
cfcd1705
DW		 1703 if (unlikely(current->audit_context)) {
1704#ifdef CONFIG_PPC64
cab175f9 1705 if (!is_32bit_task())
cfcd1705
DW		 1706 audit_syscall_entry(AUDIT_ARCH_PPC64,
1707 regs->gpr[0],
1708 regs->gpr[3], regs->gpr[4],
1709 regs->gpr[5], regs->gpr[6]);
1710 else
e8a30302 1711#endif
cfcd1705
DW		 1712 audit_syscall_entry(AUDIT_ARCH_PPC,
1713 regs->gpr[0],
1714 regs->gpr[3] & 0xffffffff,
1715 regs->gpr[4] & 0xffffffff,
1716 regs->gpr[5] & 0xffffffff,
1717 regs->gpr[6] & 0xffffffff);
1718 }
4f72c427
RM		 1719
1720 return ret ?: regs->gpr[0];
ea9c102c
DW		 1721}
1722
1723void do_syscall_trace_leave(struct pt_regs *regs)
1724{
4f72c427
RM		 1725 int step;
1726
ea9c102c 1727 if (unlikely(current->audit_context))
4b9c876a 1728 audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
ea9c102c
DW		 1729 regs->result);
1730
4f72c427
RM		 1731 step = test_thread_flag(TIF_SINGLESTEP);
1732 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
1733 tracehook_report_syscall_exit(regs, step);
ea9c102c 1734}
Linux kernel - Deliverables
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