Commit | Line | Data |
---|---|---|
9b6b563c PM |
1 | /* |
2 | * Common prep/pmac/chrp boot and setup code. | |
3 | */ | |
4 | ||
9b6b563c PM |
5 | #include <linux/module.h> |
6 | #include <linux/string.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/reboot.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/initrd.h> | |
9b6b563c | 13 | #include <linux/tty.h> |
9b6b563c PM |
14 | #include <linux/seq_file.h> |
15 | #include <linux/root_dev.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/console.h> | |
95f72d1e | 18 | #include <linux/memblock.h> |
9b6b563c | 19 | |
9b6b563c PM |
20 | #include <asm/io.h> |
21 | #include <asm/prom.h> | |
22 | #include <asm/processor.h> | |
23 | #include <asm/pgtable.h> | |
9b6b563c | 24 | #include <asm/setup.h> |
9b6b563c PM |
25 | #include <asm/smp.h> |
26 | #include <asm/elf.h> | |
27 | #include <asm/cputable.h> | |
28 | #include <asm/bootx.h> | |
29 | #include <asm/btext.h> | |
30 | #include <asm/machdep.h> | |
31 | #include <asm/uaccess.h> | |
9b6b563c PM |
32 | #include <asm/pmac_feature.h> |
33 | #include <asm/sections.h> | |
34 | #include <asm/nvram.h> | |
35 | #include <asm/xmon.h> | |
6d7f58b0 | 36 | #include <asm/time.h> |
463ce0e1 | 37 | #include <asm/serial.h> |
51d3082f | 38 | #include <asm/udbg.h> |
77520351 | 39 | #include <asm/mmu_context.h> |
4e21b94c | 40 | #include <asm/epapr_hcalls.h> |
9b6b563c | 41 | |
03501dab PM |
42 | #define DBG(fmt...) |
43 | ||
9b6b563c PM |
44 | extern void bootx_init(unsigned long r4, unsigned long phys); |
45 | ||
80579e1f | 46 | int boot_cpuid_phys; |
9974eec2 | 47 | EXPORT_SYMBOL_GPL(boot_cpuid_phys); |
80579e1f | 48 | |
13a9801e NL |
49 | int smp_hw_index[NR_CPUS]; |
50 | ||
9b6b563c PM |
51 | unsigned long ISA_DMA_THRESHOLD; |
52 | unsigned int DMA_MODE_READ; | |
53 | unsigned int DMA_MODE_WRITE; | |
54 | ||
9b6b563c PM |
55 | /* |
56 | * These are used in binfmt_elf.c to put aux entries on the stack | |
57 | * for each elf executable being started. | |
58 | */ | |
59 | int dcache_bsize; | |
60 | int icache_bsize; | |
61 | int ucache_bsize; | |
62 | ||
9b6b563c PM |
63 | /* |
64 | * We're called here very early in the boot. We determine the machine | |
65 | * type and call the appropriate low-level setup functions. | |
66 | * -- Cort <cort@fsmlabs.com> | |
67 | * | |
68 | * Note that the kernel may be running at an address which is different | |
69 | * from the address that it was linked at, so we must use RELOC/PTRRELOC | |
70 | * to access static data (including strings). -- paulus | |
71 | */ | |
4e491d14 | 72 | notrace unsigned long __init early_init(unsigned long dt_ptr) |
9b6b563c PM |
73 | { |
74 | unsigned long offset = reloc_offset(); | |
42c4aaad | 75 | struct cpu_spec *spec; |
9b6b563c | 76 | |
dd184343 PM |
77 | /* First zero the BSS -- use memset_io, some platforms don't have |
78 | * caches on yet */ | |
556b09c8 MG |
79 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, |
80 | __bss_stop - __bss_start); | |
dd184343 | 81 | |
9b6b563c PM |
82 | /* |
83 | * Identify the CPU type and fix up code sections | |
84 | * that depend on which cpu we have. | |
85 | */ | |
974a76f5 | 86 | spec = identify_cpu(offset, mfspr(SPRN_PVR)); |
42c4aaad | 87 | |
0909c8c2 | 88 | do_feature_fixups(spec->cpu_features, |
42c4aaad BH |
89 | PTRRELOC(&__start___ftr_fixup), |
90 | PTRRELOC(&__stop___ftr_fixup)); | |
9b6b563c | 91 | |
7c03d653 BH |
92 | do_feature_fixups(spec->mmu_features, |
93 | PTRRELOC(&__start___mmu_ftr_fixup), | |
94 | PTRRELOC(&__stop___mmu_ftr_fixup)); | |
95 | ||
2d1b2027 KG |
96 | do_lwsync_fixups(spec->cpu_features, |
97 | PTRRELOC(&__start___lwsync_fixup), | |
98 | PTRRELOC(&__stop___lwsync_fixup)); | |
99 | ||
d715e433 AB |
100 | do_final_fixups(); |
101 | ||
9b6b563c PM |
102 | return KERNELBASE + offset; |
103 | } | |
104 | ||
9b6b563c | 105 | |
9b6b563c PM |
106 | /* |
107 | * Find out what kind of machine we're on and save any data we need | |
108 | * from the early boot process (devtree is copied on pmac by prom_init()). | |
109 | * This is called very early on the boot process, after a minimal | |
110 | * MMU environment has been set up but before MMU_init is called. | |
111 | */ | |
6dece0eb | 112 | notrace void __init machine_init(u64 dt_ptr) |
9b6b563c | 113 | { |
5d38902c BH |
114 | lockdep_init(); |
115 | ||
719c91cc DG |
116 | /* Enable early debugging if any specified (see udbg.h) */ |
117 | udbg_early_init(); | |
51d3082f BH |
118 | |
119 | /* Do some early initialization based on the flat device tree */ | |
9b6b563c PM |
120 | early_init_devtree(__va(dt_ptr)); |
121 | ||
4e21b94c LT |
122 | epapr_paravirt_early_init(); |
123 | ||
91b191c7 DK |
124 | early_init_mmu(); |
125 | ||
e8222502 | 126 | probe_machine(); |
35499c01 | 127 | |
f8f50b1b DF |
128 | setup_kdump_trampoline(); |
129 | ||
9b6b563c | 130 | #ifdef CONFIG_6xx |
a0652fc9 PM |
131 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
132 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
133 | ppc_md.power_save = ppc6xx_idle; | |
9b6b563c | 134 | #endif |
9b6b563c | 135 | |
fc4033b2 KG |
136 | #ifdef CONFIG_E500 |
137 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
138 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
139 | ppc_md.power_save = e500_idle; | |
140 | #endif | |
9b6b563c PM |
141 | if (ppc_md.progress) |
142 | ppc_md.progress("id mach(): done", 0x200); | |
143 | } | |
144 | ||
9b6b563c PM |
145 | /* Checks "l2cr=xxxx" command-line option */ |
146 | int __init ppc_setup_l2cr(char *str) | |
147 | { | |
148 | if (cpu_has_feature(CPU_FTR_L2CR)) { | |
149 | unsigned long val = simple_strtoul(str, NULL, 0); | |
150 | printk(KERN_INFO "l2cr set to %lx\n", val); | |
151 | _set_L2CR(0); /* force invalidate by disable cache */ | |
152 | _set_L2CR(val); /* and enable it */ | |
153 | } | |
154 | return 1; | |
155 | } | |
156 | __setup("l2cr=", ppc_setup_l2cr); | |
157 | ||
a78bfbfc RB |
158 | /* Checks "l3cr=xxxx" command-line option */ |
159 | int __init ppc_setup_l3cr(char *str) | |
160 | { | |
161 | if (cpu_has_feature(CPU_FTR_L3CR)) { | |
162 | unsigned long val = simple_strtoul(str, NULL, 0); | |
163 | printk(KERN_INFO "l3cr set to %lx\n", val); | |
164 | _set_L3CR(val); /* and enable it */ | |
165 | } | |
166 | return 1; | |
167 | } | |
168 | __setup("l3cr=", ppc_setup_l3cr); | |
169 | ||
9b6b563c PM |
170 | #ifdef CONFIG_GENERIC_NVRAM |
171 | ||
172 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ | |
173 | unsigned char nvram_read_byte(int addr) | |
174 | { | |
175 | if (ppc_md.nvram_read_val) | |
176 | return ppc_md.nvram_read_val(addr); | |
177 | return 0xff; | |
178 | } | |
179 | EXPORT_SYMBOL(nvram_read_byte); | |
180 | ||
181 | void nvram_write_byte(unsigned char val, int addr) | |
182 | { | |
183 | if (ppc_md.nvram_write_val) | |
184 | ppc_md.nvram_write_val(addr, val); | |
185 | } | |
186 | EXPORT_SYMBOL(nvram_write_byte); | |
187 | ||
d331d830 MW |
188 | ssize_t nvram_get_size(void) |
189 | { | |
190 | if (ppc_md.nvram_size) | |
191 | return ppc_md.nvram_size(); | |
192 | return -1; | |
193 | } | |
194 | EXPORT_SYMBOL(nvram_get_size); | |
195 | ||
9b6b563c PM |
196 | void nvram_sync(void) |
197 | { | |
198 | if (ppc_md.nvram_sync) | |
199 | ppc_md.nvram_sync(); | |
200 | } | |
201 | EXPORT_SYMBOL(nvram_sync); | |
202 | ||
203 | #endif /* CONFIG_NVRAM */ | |
204 | ||
9b6b563c PM |
205 | int __init ppc_init(void) |
206 | { | |
9b6b563c | 207 | /* clear the progress line */ |
5e41763a GP |
208 | if (ppc_md.progress) |
209 | ppc_md.progress(" ", 0xffff); | |
9b6b563c | 210 | |
9b6b563c PM |
211 | /* call platform init */ |
212 | if (ppc_md.init != NULL) { | |
213 | ppc_md.init(); | |
214 | } | |
215 | return 0; | |
216 | } | |
217 | ||
218 | arch_initcall(ppc_init); | |
219 | ||
85218827 KG |
220 | static void __init irqstack_early_init(void) |
221 | { | |
222 | unsigned int i; | |
223 | ||
224 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
e63075a3 | 225 | * as the memblock is limited to lowmem by default */ |
85218827 KG |
226 | for_each_possible_cpu(i) { |
227 | softirq_ctx[i] = (struct thread_info *) | |
95f72d1e | 228 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 | 229 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 230 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 KG |
231 | } |
232 | } | |
85218827 | 233 | |
bcf0b088 KG |
234 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
235 | static void __init exc_lvl_early_init(void) | |
236 | { | |
3e7f45ad | 237 | unsigned int i, hw_cpu; |
bcf0b088 KG |
238 | |
239 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
95f72d1e | 240 | * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ |
bcf0b088 | 241 | for_each_possible_cpu(i) { |
04a34113 | 242 | #ifdef CONFIG_SMP |
3e7f45ad | 243 | hw_cpu = get_hard_smp_processor_id(i); |
04a34113 KH |
244 | #else |
245 | hw_cpu = 0; | |
246 | #endif | |
247 | ||
3e7f45ad | 248 | critirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 249 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 | 250 | #ifdef CONFIG_BOOKE |
3e7f45ad | 251 | dbgirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 252 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
3e7f45ad | 253 | mcheckirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 254 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 KG |
255 | #endif |
256 | } | |
257 | } | |
258 | #else | |
259 | #define exc_lvl_early_init() | |
260 | #endif | |
261 | ||
9b6b563c PM |
262 | /* Warning, IO base is not yet inited */ |
263 | void __init setup_arch(char **cmdline_p) | |
264 | { | |
3e47d147 | 265 | *cmdline_p = boot_command_line; |
846f77b0 | 266 | |
9b6b563c PM |
267 | /* so udelay does something sensible, assume <= 1000 bogomips */ |
268 | loops_per_jiffy = 500000000 / HZ; | |
269 | ||
9b6b563c | 270 | unflatten_device_tree(); |
a82765b6 | 271 | check_for_initrd(); |
463ce0e1 BH |
272 | |
273 | if (ppc_md.init_early) | |
274 | ppc_md.init_early(); | |
275 | ||
463ce0e1 | 276 | find_legacy_serial_ports(); |
9b6b563c | 277 | |
5ad57078 PM |
278 | smp_setup_cpu_maps(); |
279 | ||
51d3082f BH |
280 | /* Register early console */ |
281 | register_early_udbg_console(); | |
9b6b563c | 282 | |
47679283 ME |
283 | xmon_setup(); |
284 | ||
9b6b563c PM |
285 | /* |
286 | * Set cache line size based on type of cpu as a default. | |
287 | * Systems with OF can look in the properties on the cpu node(s) | |
288 | * for a possibly more accurate value. | |
289 | */ | |
4508dc21 DG |
290 | dcache_bsize = cur_cpu_spec->dcache_bsize; |
291 | icache_bsize = cur_cpu_spec->icache_bsize; | |
292 | ucache_bsize = 0; | |
293 | if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) | |
294 | ucache_bsize = icache_bsize = dcache_bsize; | |
9b6b563c | 295 | |
7e990266 KG |
296 | if (ppc_md.panic) |
297 | setup_panic(); | |
298 | ||
4846c5de | 299 | init_mm.start_code = (unsigned long)_stext; |
9b6b563c PM |
300 | init_mm.end_code = (unsigned long) _etext; |
301 | init_mm.end_data = (unsigned long) _edata; | |
49b09853 | 302 | init_mm.brk = klimit; |
9b6b563c | 303 | |
bcf0b088 KG |
304 | exc_lvl_early_init(); |
305 | ||
85218827 KG |
306 | irqstack_early_init(); |
307 | ||
10239733 AB |
308 | initmem_init(); |
309 | if ( ppc_md.progress ) ppc_md.progress("setup_arch: initmem", 0x3eab); | |
9b6b563c | 310 | |
9b6b563c PM |
311 | #ifdef CONFIG_DUMMY_CONSOLE |
312 | conswitchp = &dummy_con; | |
313 | #endif | |
314 | ||
38db7e74 GL |
315 | if (ppc_md.setup_arch) |
316 | ppc_md.setup_arch(); | |
9b6b563c PM |
317 | if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); |
318 | ||
319 | paging_init(); | |
77520351 BH |
320 | |
321 | /* Initialize the MMU context management stuff */ | |
322 | mmu_context_init(); | |
9b6b563c | 323 | } |