Commit | Line | Data |
---|---|---|
9b6b563c PM |
1 | /* |
2 | * Common prep/pmac/chrp boot and setup code. | |
3 | */ | |
4 | ||
9b6b563c PM |
5 | #include <linux/module.h> |
6 | #include <linux/string.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/reboot.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/initrd.h> | |
9b6b563c | 13 | #include <linux/tty.h> |
9b6b563c PM |
14 | #include <linux/seq_file.h> |
15 | #include <linux/root_dev.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/console.h> | |
95f72d1e | 18 | #include <linux/memblock.h> |
9b6b563c | 19 | |
9b6b563c PM |
20 | #include <asm/io.h> |
21 | #include <asm/prom.h> | |
22 | #include <asm/processor.h> | |
23 | #include <asm/pgtable.h> | |
9b6b563c | 24 | #include <asm/setup.h> |
9b6b563c PM |
25 | #include <asm/smp.h> |
26 | #include <asm/elf.h> | |
27 | #include <asm/cputable.h> | |
28 | #include <asm/bootx.h> | |
29 | #include <asm/btext.h> | |
30 | #include <asm/machdep.h> | |
31 | #include <asm/uaccess.h> | |
9b6b563c PM |
32 | #include <asm/pmac_feature.h> |
33 | #include <asm/sections.h> | |
34 | #include <asm/nvram.h> | |
35 | #include <asm/xmon.h> | |
6d7f58b0 | 36 | #include <asm/time.h> |
463ce0e1 | 37 | #include <asm/serial.h> |
51d3082f | 38 | #include <asm/udbg.h> |
77520351 | 39 | #include <asm/mmu_context.h> |
4e21b94c | 40 | #include <asm/epapr_hcalls.h> |
1cd03890 | 41 | #include <asm/code-patching.h> |
9b6b563c | 42 | |
03501dab PM |
43 | #define DBG(fmt...) |
44 | ||
9b6b563c PM |
45 | extern void bootx_init(unsigned long r4, unsigned long phys); |
46 | ||
80579e1f | 47 | int boot_cpuid_phys; |
9974eec2 | 48 | EXPORT_SYMBOL_GPL(boot_cpuid_phys); |
80579e1f | 49 | |
13a9801e NL |
50 | int smp_hw_index[NR_CPUS]; |
51 | ||
9b6b563c PM |
52 | unsigned long ISA_DMA_THRESHOLD; |
53 | unsigned int DMA_MODE_READ; | |
54 | unsigned int DMA_MODE_WRITE; | |
55 | ||
9b6b563c PM |
56 | /* |
57 | * These are used in binfmt_elf.c to put aux entries on the stack | |
58 | * for each elf executable being started. | |
59 | */ | |
60 | int dcache_bsize; | |
61 | int icache_bsize; | |
62 | int ucache_bsize; | |
63 | ||
9b6b563c PM |
64 | /* |
65 | * We're called here very early in the boot. We determine the machine | |
66 | * type and call the appropriate low-level setup functions. | |
67 | * -- Cort <cort@fsmlabs.com> | |
68 | * | |
69 | * Note that the kernel may be running at an address which is different | |
70 | * from the address that it was linked at, so we must use RELOC/PTRRELOC | |
71 | * to access static data (including strings). -- paulus | |
72 | */ | |
4e491d14 | 73 | notrace unsigned long __init early_init(unsigned long dt_ptr) |
9b6b563c PM |
74 | { |
75 | unsigned long offset = reloc_offset(); | |
42c4aaad | 76 | struct cpu_spec *spec; |
9b6b563c | 77 | |
dd184343 PM |
78 | /* First zero the BSS -- use memset_io, some platforms don't have |
79 | * caches on yet */ | |
556b09c8 MG |
80 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, |
81 | __bss_stop - __bss_start); | |
dd184343 | 82 | |
9b6b563c PM |
83 | /* |
84 | * Identify the CPU type and fix up code sections | |
85 | * that depend on which cpu we have. | |
86 | */ | |
974a76f5 | 87 | spec = identify_cpu(offset, mfspr(SPRN_PVR)); |
42c4aaad | 88 | |
0909c8c2 | 89 | do_feature_fixups(spec->cpu_features, |
42c4aaad BH |
90 | PTRRELOC(&__start___ftr_fixup), |
91 | PTRRELOC(&__stop___ftr_fixup)); | |
9b6b563c | 92 | |
7c03d653 BH |
93 | do_feature_fixups(spec->mmu_features, |
94 | PTRRELOC(&__start___mmu_ftr_fixup), | |
95 | PTRRELOC(&__stop___mmu_ftr_fixup)); | |
96 | ||
2d1b2027 KG |
97 | do_lwsync_fixups(spec->cpu_features, |
98 | PTRRELOC(&__start___lwsync_fixup), | |
99 | PTRRELOC(&__stop___lwsync_fixup)); | |
100 | ||
d715e433 AB |
101 | do_final_fixups(); |
102 | ||
9b6b563c PM |
103 | return KERNELBASE + offset; |
104 | } | |
105 | ||
9b6b563c | 106 | |
9b6b563c PM |
107 | /* |
108 | * Find out what kind of machine we're on and save any data we need | |
109 | * from the early boot process (devtree is copied on pmac by prom_init()). | |
110 | * This is called very early on the boot process, after a minimal | |
111 | * MMU environment has been set up but before MMU_init is called. | |
112 | */ | |
400c47d8 LC |
113 | extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */ |
114 | ||
6dece0eb | 115 | notrace void __init machine_init(u64 dt_ptr) |
9b6b563c | 116 | { |
719c91cc DG |
117 | /* Enable early debugging if any specified (see udbg.h) */ |
118 | udbg_early_init(); | |
51d3082f | 119 | |
1cd03890 | 120 | patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP); |
400c47d8 | 121 | patch_instruction(&memset_nocache_branch, PPC_INST_NOP); |
1cd03890 | 122 | |
51d3082f | 123 | /* Do some early initialization based on the flat device tree */ |
9b6b563c PM |
124 | early_init_devtree(__va(dt_ptr)); |
125 | ||
4e21b94c LT |
126 | epapr_paravirt_early_init(); |
127 | ||
91b191c7 DK |
128 | early_init_mmu(); |
129 | ||
e8222502 | 130 | probe_machine(); |
35499c01 | 131 | |
f8f50b1b DF |
132 | setup_kdump_trampoline(); |
133 | ||
9b6b563c | 134 | #ifdef CONFIG_6xx |
a0652fc9 PM |
135 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
136 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
137 | ppc_md.power_save = ppc6xx_idle; | |
9b6b563c | 138 | #endif |
9b6b563c | 139 | |
fc4033b2 KG |
140 | #ifdef CONFIG_E500 |
141 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
142 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
143 | ppc_md.power_save = e500_idle; | |
144 | #endif | |
9b6b563c PM |
145 | if (ppc_md.progress) |
146 | ppc_md.progress("id mach(): done", 0x200); | |
147 | } | |
148 | ||
9b6b563c PM |
149 | /* Checks "l2cr=xxxx" command-line option */ |
150 | int __init ppc_setup_l2cr(char *str) | |
151 | { | |
152 | if (cpu_has_feature(CPU_FTR_L2CR)) { | |
153 | unsigned long val = simple_strtoul(str, NULL, 0); | |
154 | printk(KERN_INFO "l2cr set to %lx\n", val); | |
155 | _set_L2CR(0); /* force invalidate by disable cache */ | |
156 | _set_L2CR(val); /* and enable it */ | |
157 | } | |
158 | return 1; | |
159 | } | |
160 | __setup("l2cr=", ppc_setup_l2cr); | |
161 | ||
a78bfbfc RB |
162 | /* Checks "l3cr=xxxx" command-line option */ |
163 | int __init ppc_setup_l3cr(char *str) | |
164 | { | |
165 | if (cpu_has_feature(CPU_FTR_L3CR)) { | |
166 | unsigned long val = simple_strtoul(str, NULL, 0); | |
167 | printk(KERN_INFO "l3cr set to %lx\n", val); | |
168 | _set_L3CR(val); /* and enable it */ | |
169 | } | |
170 | return 1; | |
171 | } | |
172 | __setup("l3cr=", ppc_setup_l3cr); | |
173 | ||
9b6b563c PM |
174 | #ifdef CONFIG_GENERIC_NVRAM |
175 | ||
176 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ | |
177 | unsigned char nvram_read_byte(int addr) | |
178 | { | |
179 | if (ppc_md.nvram_read_val) | |
180 | return ppc_md.nvram_read_val(addr); | |
181 | return 0xff; | |
182 | } | |
183 | EXPORT_SYMBOL(nvram_read_byte); | |
184 | ||
185 | void nvram_write_byte(unsigned char val, int addr) | |
186 | { | |
187 | if (ppc_md.nvram_write_val) | |
188 | ppc_md.nvram_write_val(addr, val); | |
189 | } | |
190 | EXPORT_SYMBOL(nvram_write_byte); | |
191 | ||
d331d830 MW |
192 | ssize_t nvram_get_size(void) |
193 | { | |
194 | if (ppc_md.nvram_size) | |
195 | return ppc_md.nvram_size(); | |
196 | return -1; | |
197 | } | |
198 | EXPORT_SYMBOL(nvram_get_size); | |
199 | ||
9b6b563c PM |
200 | void nvram_sync(void) |
201 | { | |
202 | if (ppc_md.nvram_sync) | |
203 | ppc_md.nvram_sync(); | |
204 | } | |
205 | EXPORT_SYMBOL(nvram_sync); | |
206 | ||
207 | #endif /* CONFIG_NVRAM */ | |
208 | ||
9b6b563c PM |
209 | int __init ppc_init(void) |
210 | { | |
9b6b563c | 211 | /* clear the progress line */ |
5e41763a GP |
212 | if (ppc_md.progress) |
213 | ppc_md.progress(" ", 0xffff); | |
9b6b563c | 214 | |
9b6b563c PM |
215 | /* call platform init */ |
216 | if (ppc_md.init != NULL) { | |
217 | ppc_md.init(); | |
218 | } | |
219 | return 0; | |
220 | } | |
221 | ||
222 | arch_initcall(ppc_init); | |
223 | ||
85218827 KG |
224 | static void __init irqstack_early_init(void) |
225 | { | |
226 | unsigned int i; | |
227 | ||
228 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
e63075a3 | 229 | * as the memblock is limited to lowmem by default */ |
85218827 KG |
230 | for_each_possible_cpu(i) { |
231 | softirq_ctx[i] = (struct thread_info *) | |
95f72d1e | 232 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 | 233 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 234 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 KG |
235 | } |
236 | } | |
85218827 | 237 | |
bcf0b088 KG |
238 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
239 | static void __init exc_lvl_early_init(void) | |
240 | { | |
3e7f45ad | 241 | unsigned int i, hw_cpu; |
bcf0b088 KG |
242 | |
243 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
95f72d1e | 244 | * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ |
bcf0b088 | 245 | for_each_possible_cpu(i) { |
04a34113 | 246 | #ifdef CONFIG_SMP |
3e7f45ad | 247 | hw_cpu = get_hard_smp_processor_id(i); |
04a34113 KH |
248 | #else |
249 | hw_cpu = 0; | |
250 | #endif | |
251 | ||
3e7f45ad | 252 | critirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 253 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 | 254 | #ifdef CONFIG_BOOKE |
3e7f45ad | 255 | dbgirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 256 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
3e7f45ad | 257 | mcheckirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 258 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 KG |
259 | #endif |
260 | } | |
261 | } | |
262 | #else | |
263 | #define exc_lvl_early_init() | |
264 | #endif | |
265 | ||
9b6b563c PM |
266 | /* Warning, IO base is not yet inited */ |
267 | void __init setup_arch(char **cmdline_p) | |
268 | { | |
3e47d147 | 269 | *cmdline_p = boot_command_line; |
846f77b0 | 270 | |
9b6b563c PM |
271 | /* so udelay does something sensible, assume <= 1000 bogomips */ |
272 | loops_per_jiffy = 500000000 / HZ; | |
273 | ||
9b6b563c | 274 | unflatten_device_tree(); |
a82765b6 | 275 | check_for_initrd(); |
463ce0e1 BH |
276 | |
277 | if (ppc_md.init_early) | |
278 | ppc_md.init_early(); | |
279 | ||
463ce0e1 | 280 | find_legacy_serial_ports(); |
9b6b563c | 281 | |
5ad57078 PM |
282 | smp_setup_cpu_maps(); |
283 | ||
51d3082f BH |
284 | /* Register early console */ |
285 | register_early_udbg_console(); | |
9b6b563c | 286 | |
47679283 ME |
287 | xmon_setup(); |
288 | ||
9b6b563c PM |
289 | /* |
290 | * Set cache line size based on type of cpu as a default. | |
291 | * Systems with OF can look in the properties on the cpu node(s) | |
292 | * for a possibly more accurate value. | |
293 | */ | |
4508dc21 DG |
294 | dcache_bsize = cur_cpu_spec->dcache_bsize; |
295 | icache_bsize = cur_cpu_spec->icache_bsize; | |
296 | ucache_bsize = 0; | |
297 | if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) | |
298 | ucache_bsize = icache_bsize = dcache_bsize; | |
9b6b563c | 299 | |
7e990266 KG |
300 | if (ppc_md.panic) |
301 | setup_panic(); | |
302 | ||
4846c5de | 303 | init_mm.start_code = (unsigned long)_stext; |
9b6b563c PM |
304 | init_mm.end_code = (unsigned long) _etext; |
305 | init_mm.end_data = (unsigned long) _edata; | |
49b09853 | 306 | init_mm.brk = klimit; |
9b6b563c | 307 | |
bcf0b088 KG |
308 | exc_lvl_early_init(); |
309 | ||
85218827 KG |
310 | irqstack_early_init(); |
311 | ||
10239733 AB |
312 | initmem_init(); |
313 | if ( ppc_md.progress ) ppc_md.progress("setup_arch: initmem", 0x3eab); | |
9b6b563c | 314 | |
9b6b563c PM |
315 | #ifdef CONFIG_DUMMY_CONSOLE |
316 | conswitchp = &dummy_con; | |
317 | #endif | |
318 | ||
38db7e74 GL |
319 | if (ppc_md.setup_arch) |
320 | ppc_md.setup_arch(); | |
9b6b563c PM |
321 | if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); |
322 | ||
323 | paging_init(); | |
77520351 BH |
324 | |
325 | /* Initialize the MMU context management stuff */ | |
326 | mmu_context_init(); | |
9b6b563c | 327 | } |