Commit | Line | Data |
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9b6b563c PM |
1 | /* |
2 | * Common prep/pmac/chrp boot and setup code. | |
3 | */ | |
4 | ||
9b6b563c PM |
5 | #include <linux/module.h> |
6 | #include <linux/string.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/reboot.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/initrd.h> | |
9b6b563c | 13 | #include <linux/tty.h> |
9b6b563c PM |
14 | #include <linux/seq_file.h> |
15 | #include <linux/root_dev.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/console.h> | |
95f72d1e | 18 | #include <linux/memblock.h> |
9b6b563c | 19 | |
9b6b563c PM |
20 | #include <asm/io.h> |
21 | #include <asm/prom.h> | |
22 | #include <asm/processor.h> | |
23 | #include <asm/pgtable.h> | |
9b6b563c | 24 | #include <asm/setup.h> |
9b6b563c PM |
25 | #include <asm/smp.h> |
26 | #include <asm/elf.h> | |
27 | #include <asm/cputable.h> | |
28 | #include <asm/bootx.h> | |
29 | #include <asm/btext.h> | |
30 | #include <asm/machdep.h> | |
31 | #include <asm/uaccess.h> | |
9b6b563c PM |
32 | #include <asm/pmac_feature.h> |
33 | #include <asm/sections.h> | |
34 | #include <asm/nvram.h> | |
35 | #include <asm/xmon.h> | |
6d7f58b0 | 36 | #include <asm/time.h> |
463ce0e1 | 37 | #include <asm/serial.h> |
51d3082f | 38 | #include <asm/udbg.h> |
1cd03890 | 39 | #include <asm/code-patching.h> |
b92a226e | 40 | #include <asm/cpu_has_feature.h> |
9b6b563c | 41 | |
03501dab PM |
42 | #define DBG(fmt...) |
43 | ||
9b6b563c PM |
44 | extern void bootx_init(unsigned long r4, unsigned long phys); |
45 | ||
80579e1f | 46 | int boot_cpuid_phys; |
9974eec2 | 47 | EXPORT_SYMBOL_GPL(boot_cpuid_phys); |
80579e1f | 48 | |
13a9801e NL |
49 | int smp_hw_index[NR_CPUS]; |
50 | ||
9b6b563c PM |
51 | unsigned long ISA_DMA_THRESHOLD; |
52 | unsigned int DMA_MODE_READ; | |
53 | unsigned int DMA_MODE_WRITE; | |
54 | ||
9b6b563c PM |
55 | /* |
56 | * These are used in binfmt_elf.c to put aux entries on the stack | |
57 | * for each elf executable being started. | |
58 | */ | |
59 | int dcache_bsize; | |
60 | int icache_bsize; | |
61 | int ucache_bsize; | |
62 | ||
9b6b563c | 63 | /* |
bd7c93cc | 64 | * We're called here very early in the boot. |
9b6b563c PM |
65 | * |
66 | * Note that the kernel may be running at an address which is different | |
67 | * from the address that it was linked at, so we must use RELOC/PTRRELOC | |
68 | * to access static data (including strings). -- paulus | |
69 | */ | |
4e491d14 | 70 | notrace unsigned long __init early_init(unsigned long dt_ptr) |
9b6b563c PM |
71 | { |
72 | unsigned long offset = reloc_offset(); | |
73 | ||
dd184343 PM |
74 | /* First zero the BSS -- use memset_io, some platforms don't have |
75 | * caches on yet */ | |
556b09c8 MG |
76 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, |
77 | __bss_stop - __bss_start); | |
dd184343 | 78 | |
9b6b563c PM |
79 | /* |
80 | * Identify the CPU type and fix up code sections | |
81 | * that depend on which cpu we have. | |
82 | */ | |
9402c684 | 83 | identify_cpu(offset, mfspr(SPRN_PVR)); |
42c4aaad | 84 | |
9402c684 | 85 | apply_feature_fixups(); |
d715e433 | 86 | |
9b6b563c PM |
87 | return KERNELBASE + offset; |
88 | } | |
89 | ||
9b6b563c | 90 | |
9b6b563c | 91 | /* |
bd7c93cc BH |
92 | * This is run before start_kernel(), the kernel has been relocated |
93 | * and we are running with enough of the MMU enabled to have our | |
94 | * proper kernel virtual addresses | |
95 | * | |
f9cc1d1f BH |
96 | * We do the initial parsing of the flat device-tree and prepares |
97 | * for the MMU to be fully initialized. | |
9b6b563c | 98 | */ |
400c47d8 LC |
99 | extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */ |
100 | ||
6dece0eb | 101 | notrace void __init machine_init(u64 dt_ptr) |
9b6b563c | 102 | { |
97f6e0cc BH |
103 | /* Configure static keys first, now that we're relocated. */ |
104 | setup_feature_keys(); | |
105 | ||
719c91cc DG |
106 | /* Enable early debugging if any specified (see udbg.h) */ |
107 | udbg_early_init(); | |
51d3082f | 108 | |
1cd03890 | 109 | patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP); |
400c47d8 | 110 | patch_instruction(&memset_nocache_branch, PPC_INST_NOP); |
1cd03890 | 111 | |
51d3082f | 112 | /* Do some early initialization based on the flat device tree */ |
9b6b563c PM |
113 | early_init_devtree(__va(dt_ptr)); |
114 | ||
91b191c7 DK |
115 | early_init_mmu(); |
116 | ||
f8f50b1b | 117 | setup_kdump_trampoline(); |
9b6b563c PM |
118 | } |
119 | ||
9b6b563c PM |
120 | /* Checks "l2cr=xxxx" command-line option */ |
121 | int __init ppc_setup_l2cr(char *str) | |
122 | { | |
123 | if (cpu_has_feature(CPU_FTR_L2CR)) { | |
124 | unsigned long val = simple_strtoul(str, NULL, 0); | |
125 | printk(KERN_INFO "l2cr set to %lx\n", val); | |
126 | _set_L2CR(0); /* force invalidate by disable cache */ | |
127 | _set_L2CR(val); /* and enable it */ | |
128 | } | |
129 | return 1; | |
130 | } | |
131 | __setup("l2cr=", ppc_setup_l2cr); | |
132 | ||
a78bfbfc RB |
133 | /* Checks "l3cr=xxxx" command-line option */ |
134 | int __init ppc_setup_l3cr(char *str) | |
135 | { | |
136 | if (cpu_has_feature(CPU_FTR_L3CR)) { | |
137 | unsigned long val = simple_strtoul(str, NULL, 0); | |
138 | printk(KERN_INFO "l3cr set to %lx\n", val); | |
139 | _set_L3CR(val); /* and enable it */ | |
140 | } | |
141 | return 1; | |
142 | } | |
143 | __setup("l3cr=", ppc_setup_l3cr); | |
144 | ||
9b6b563c PM |
145 | #ifdef CONFIG_GENERIC_NVRAM |
146 | ||
147 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ | |
148 | unsigned char nvram_read_byte(int addr) | |
149 | { | |
150 | if (ppc_md.nvram_read_val) | |
151 | return ppc_md.nvram_read_val(addr); | |
152 | return 0xff; | |
153 | } | |
154 | EXPORT_SYMBOL(nvram_read_byte); | |
155 | ||
156 | void nvram_write_byte(unsigned char val, int addr) | |
157 | { | |
158 | if (ppc_md.nvram_write_val) | |
159 | ppc_md.nvram_write_val(addr, val); | |
160 | } | |
161 | EXPORT_SYMBOL(nvram_write_byte); | |
162 | ||
d331d830 MW |
163 | ssize_t nvram_get_size(void) |
164 | { | |
165 | if (ppc_md.nvram_size) | |
166 | return ppc_md.nvram_size(); | |
167 | return -1; | |
168 | } | |
169 | EXPORT_SYMBOL(nvram_get_size); | |
170 | ||
9b6b563c PM |
171 | void nvram_sync(void) |
172 | { | |
173 | if (ppc_md.nvram_sync) | |
174 | ppc_md.nvram_sync(); | |
175 | } | |
176 | EXPORT_SYMBOL(nvram_sync); | |
177 | ||
178 | #endif /* CONFIG_NVRAM */ | |
179 | ||
9b6b563c PM |
180 | int __init ppc_init(void) |
181 | { | |
9b6b563c | 182 | /* clear the progress line */ |
5e41763a GP |
183 | if (ppc_md.progress) |
184 | ppc_md.progress(" ", 0xffff); | |
9b6b563c | 185 | |
9b6b563c PM |
186 | /* call platform init */ |
187 | if (ppc_md.init != NULL) { | |
188 | ppc_md.init(); | |
189 | } | |
190 | return 0; | |
191 | } | |
192 | ||
193 | arch_initcall(ppc_init); | |
194 | ||
b1923caa | 195 | void __init irqstack_early_init(void) |
85218827 KG |
196 | { |
197 | unsigned int i; | |
198 | ||
199 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
e63075a3 | 200 | * as the memblock is limited to lowmem by default */ |
85218827 KG |
201 | for_each_possible_cpu(i) { |
202 | softirq_ctx[i] = (struct thread_info *) | |
95f72d1e | 203 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 | 204 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 205 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 KG |
206 | } |
207 | } | |
85218827 | 208 | |
bcf0b088 | 209 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
b1923caa | 210 | void __init exc_lvl_early_init(void) |
bcf0b088 | 211 | { |
3e7f45ad | 212 | unsigned int i, hw_cpu; |
bcf0b088 KG |
213 | |
214 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
95f72d1e | 215 | * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ |
bcf0b088 | 216 | for_each_possible_cpu(i) { |
04a34113 | 217 | #ifdef CONFIG_SMP |
3e7f45ad | 218 | hw_cpu = get_hard_smp_processor_id(i); |
04a34113 KH |
219 | #else |
220 | hw_cpu = 0; | |
221 | #endif | |
222 | ||
3e7f45ad | 223 | critirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 224 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 | 225 | #ifdef CONFIG_BOOKE |
3e7f45ad | 226 | dbgirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 227 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
3e7f45ad | 228 | mcheckirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 229 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 KG |
230 | #endif |
231 | } | |
232 | } | |
bcf0b088 KG |
233 | #endif |
234 | ||
b1923caa | 235 | void __init setup_power_save(void) |
56571384 BH |
236 | { |
237 | #ifdef CONFIG_6xx | |
238 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
239 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
240 | ppc_md.power_save = ppc6xx_idle; | |
241 | #endif | |
242 | ||
243 | #ifdef CONFIG_E500 | |
244 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
245 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
246 | ppc_md.power_save = e500_idle; | |
247 | #endif | |
248 | } | |
249 | ||
b1923caa | 250 | __init void initialize_cache_info(void) |
8f212cb2 BH |
251 | { |
252 | /* | |
253 | * Set cache line size based on type of cpu as a default. | |
254 | * Systems with OF can look in the properties on the cpu node(s) | |
255 | * for a possibly more accurate value. | |
256 | */ | |
257 | dcache_bsize = cur_cpu_spec->dcache_bsize; | |
258 | icache_bsize = cur_cpu_spec->icache_bsize; | |
259 | ucache_bsize = 0; | |
260 | if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) | |
261 | ucache_bsize = icache_bsize = dcache_bsize; | |
262 | } |