Commit | Line | Data |
---|---|---|
40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #undef DEBUG | |
14 | ||
40ef8cbc PM |
15 | #include <linux/module.h> |
16 | #include <linux/string.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
40ef8cbc | 38 | #include <asm/io.h> |
0cc4746c | 39 | #include <asm/kdump.h> |
40ef8cbc PM |
40 | #include <asm/prom.h> |
41 | #include <asm/processor.h> | |
42 | #include <asm/pgtable.h> | |
40ef8cbc PM |
43 | #include <asm/smp.h> |
44 | #include <asm/elf.h> | |
45 | #include <asm/machdep.h> | |
46 | #include <asm/paca.h> | |
40ef8cbc PM |
47 | #include <asm/time.h> |
48 | #include <asm/cputable.h> | |
49 | #include <asm/sections.h> | |
50 | #include <asm/btext.h> | |
51 | #include <asm/nvram.h> | |
52 | #include <asm/setup.h> | |
53 | #include <asm/system.h> | |
54 | #include <asm/rtas.h> | |
55 | #include <asm/iommu.h> | |
56 | #include <asm/serial.h> | |
57 | #include <asm/cache.h> | |
58 | #include <asm/page.h> | |
59 | #include <asm/mmu.h> | |
40ef8cbc | 60 | #include <asm/firmware.h> |
f78541dc | 61 | #include <asm/xmon.h> |
dcad47fc | 62 | #include <asm/udbg.h> |
593e537b | 63 | #include <asm/kexec.h> |
25d21ad6 | 64 | #include <asm/mmu_context.h> |
40ef8cbc | 65 | |
66ba135c SR |
66 | #include "setup.h" |
67 | ||
40ef8cbc PM |
68 | #ifdef DEBUG |
69 | #define DBG(fmt...) udbg_printf(fmt) | |
70 | #else | |
71 | #define DBG(fmt...) | |
72 | #endif | |
73 | ||
40ef8cbc | 74 | int boot_cpuid = 0; |
40ef8cbc PM |
75 | u64 ppc64_pft_size; |
76 | ||
dabcafd3 OJ |
77 | /* Pick defaults since we might want to patch instructions |
78 | * before we've read this from the device tree. | |
79 | */ | |
80 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
81 | .dline_size = 0x40, |
82 | .log_dline_size = 6, | |
83 | .iline_size = 0x40, | |
84 | .log_iline_size = 6 | |
dabcafd3 | 85 | }; |
40ef8cbc PM |
86 | EXPORT_SYMBOL_GPL(ppc64_caches); |
87 | ||
88 | /* | |
89 | * These are used in binfmt_elf.c to put aux entries on the stack | |
90 | * for each elf executable being started. | |
91 | */ | |
92 | int dcache_bsize; | |
93 | int icache_bsize; | |
94 | int ucache_bsize; | |
95 | ||
40ef8cbc PM |
96 | #ifdef CONFIG_SMP |
97 | ||
954e6da5 | 98 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
99 | |
100 | /* Look for ibm,smt-enabled OF option */ | |
101 | static void check_smt_enabled(void) | |
102 | { | |
103 | struct device_node *dn; | |
a7f67bdf | 104 | const char *smt_option; |
40ef8cbc | 105 | |
954e6da5 NF |
106 | /* Default to enabling all threads */ |
107 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 108 | |
954e6da5 NF |
109 | /* Allow the command line to overrule the OF option */ |
110 | if (smt_enabled_cmdline) { | |
111 | if (!strcmp(smt_enabled_cmdline, "on")) | |
112 | smt_enabled_at_boot = threads_per_core; | |
113 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
114 | smt_enabled_at_boot = 0; | |
115 | else { | |
116 | long smt; | |
117 | int rc; | |
118 | ||
119 | rc = strict_strtol(smt_enabled_cmdline, 10, &smt); | |
120 | if (!rc) | |
121 | smt_enabled_at_boot = | |
122 | min(threads_per_core, (int)smt); | |
123 | } | |
124 | } else { | |
125 | dn = of_find_node_by_path("/options"); | |
126 | if (dn) { | |
127 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
128 | NULL); | |
129 | ||
130 | if (smt_option) { | |
131 | if (!strcmp(smt_option, "on")) | |
132 | smt_enabled_at_boot = threads_per_core; | |
133 | else if (!strcmp(smt_option, "off")) | |
134 | smt_enabled_at_boot = 0; | |
135 | } | |
136 | ||
137 | of_node_put(dn); | |
138 | } | |
139 | } | |
40ef8cbc PM |
140 | } |
141 | ||
142 | /* Look for smt-enabled= cmdline option */ | |
143 | static int __init early_smt_enabled(char *p) | |
144 | { | |
954e6da5 | 145 | smt_enabled_cmdline = p; |
40ef8cbc PM |
146 | return 0; |
147 | } | |
148 | early_param("smt-enabled", early_smt_enabled); | |
149 | ||
5ad57078 PM |
150 | #else |
151 | #define check_smt_enabled() | |
40ef8cbc PM |
152 | #endif /* CONFIG_SMP */ |
153 | ||
40ef8cbc PM |
154 | /* |
155 | * Early initialization entry point. This is called by head.S | |
156 | * with MMU translation disabled. We rely on the "feature" of | |
157 | * the CPU that ignores the top 2 bits of the address in real | |
158 | * mode so we can access kernel globals normally provided we | |
159 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 160 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
161 | * data structures, and allocate & initialize the hash table |
162 | * and segment tables so we can start running with translation | |
163 | * enabled. | |
164 | * | |
165 | * It is this function which will call the probe() callback of | |
166 | * the various platform types and copy the matching one to the | |
167 | * global ppc_md structure. Your platform can eventually do | |
168 | * some very early initializations from the probe() routine, but | |
169 | * this is not recommended, be very careful as, for example, the | |
170 | * device-tree is not accessible via normal means at this point. | |
171 | */ | |
172 | ||
173 | void __init early_setup(unsigned long dt_ptr) | |
174 | { | |
24d96495 BH |
175 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
176 | ||
42c4aaad | 177 | /* Identify CPU type */ |
974a76f5 | 178 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 179 | |
33dbcf72 | 180 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
181 | initialise_paca(&boot_paca, 0); |
182 | setup_paca(&boot_paca); | |
33dbcf72 | 183 | |
945feb17 BH |
184 | /* Initialize lockdep early or else spinlocks will blow */ |
185 | lockdep_init(); | |
186 | ||
24d96495 BH |
187 | /* -------- printk is now safe to use ------- */ |
188 | ||
f2fd2513 BH |
189 | /* Enable early debugging if any specified (see udbg.h) */ |
190 | udbg_early_init(); | |
191 | ||
e8222502 | 192 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 193 | |
40ef8cbc | 194 | /* |
3c607ce2 LV |
195 | * Do early initialization using the flattened device |
196 | * tree, such as retrieving the physical memory map or | |
197 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
198 | */ |
199 | early_init_devtree(__va(dt_ptr)); | |
200 | ||
4df20460 | 201 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 202 | setup_paca(&paca[boot_cpuid]); |
4df20460 AB |
203 | |
204 | /* Fix up paca fields required for the boot cpu */ | |
205 | get_paca()->cpu_start = 1; | |
4df20460 | 206 | |
e8222502 BH |
207 | /* Probe the machine type */ |
208 | probe_machine(); | |
40ef8cbc | 209 | |
47310413 | 210 | setup_kdump_trampoline(); |
0cc4746c | 211 | |
40ef8cbc PM |
212 | DBG("Found, Initializing memory management...\n"); |
213 | ||
757c74d2 BH |
214 | /* Initialize the hash table or TLB handling */ |
215 | early_init_mmu(); | |
40ef8cbc PM |
216 | |
217 | DBG(" <- early_setup()\n"); | |
218 | } | |
219 | ||
799d6046 PM |
220 | #ifdef CONFIG_SMP |
221 | void early_setup_secondary(void) | |
222 | { | |
d04c56f7 | 223 | /* Mark interrupts enabled in PACA */ |
757c74d2 | 224 | get_paca()->soft_enabled = 0; |
799d6046 | 225 | |
757c74d2 BH |
226 | /* Initialize the hash table or TLB handling */ |
227 | early_init_mmu_secondary(); | |
799d6046 PM |
228 | } |
229 | ||
230 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 231 | |
b8f51021 ME |
232 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
233 | void smp_release_cpus(void) | |
234 | { | |
758438a7 | 235 | unsigned long *ptr; |
b8f51021 ME |
236 | |
237 | DBG(" -> smp_release_cpus()\n"); | |
238 | ||
239 | /* All secondary cpus are spinning on a common spinloop, release them | |
240 | * all now so they can start to spin on their individual paca | |
241 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
242 | * of the common spinloop. | |
1f6a93e4 | 243 | */ |
b8f51021 | 244 | |
758438a7 ME |
245 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
246 | - PHYSICAL_START); | |
1f6a93e4 | 247 | *ptr = __pa(generic_secondary_smp_init); |
b8f51021 ME |
248 | mb(); |
249 | ||
250 | DBG(" <- smp_release_cpus()\n"); | |
251 | } | |
252 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
253 | ||
40ef8cbc | 254 | /* |
799d6046 PM |
255 | * Initialize some remaining members of the ppc64_caches and systemcfg |
256 | * structures | |
40ef8cbc PM |
257 | * (at least until we get rid of them completely). This is mostly some |
258 | * cache informations about the CPU that will be used by cache flush | |
259 | * routines and/or provided to userland | |
260 | */ | |
261 | static void __init initialize_cache_info(void) | |
262 | { | |
263 | struct device_node *np; | |
264 | unsigned long num_cpus = 0; | |
265 | ||
266 | DBG(" -> initialize_cache_info()\n"); | |
267 | ||
268 | for (np = NULL; (np = of_find_node_by_type(np, "cpu"));) { | |
269 | num_cpus += 1; | |
270 | ||
271 | /* We're assuming *all* of the CPUs have the same | |
272 | * d-cache and i-cache sizes... -Peter | |
273 | */ | |
274 | ||
275 | if ( num_cpus == 1 ) { | |
a7f67bdf | 276 | const u32 *sizep, *lsizep; |
40ef8cbc | 277 | u32 size, lsize; |
40ef8cbc PM |
278 | |
279 | size = 0; | |
280 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 281 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc PM |
282 | if (sizep != NULL) |
283 | size = *sizep; | |
20474abd BH |
284 | lsizep = of_get_property(np, "d-cache-block-size", NULL); |
285 | /* fallback if block size missing */ | |
286 | if (lsizep == NULL) | |
287 | lsizep = of_get_property(np, "d-cache-line-size", NULL); | |
40ef8cbc PM |
288 | if (lsizep != NULL) |
289 | lsize = *lsizep; | |
290 | if (sizep == 0 || lsizep == 0) | |
291 | DBG("Argh, can't find dcache properties ! " | |
292 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
293 | ||
a7f290da BH |
294 | ppc64_caches.dsize = size; |
295 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
296 | ppc64_caches.log_dline_size = __ilog2(lsize); |
297 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
298 | ||
299 | size = 0; | |
300 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 301 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc PM |
302 | if (sizep != NULL) |
303 | size = *sizep; | |
20474abd BH |
304 | lsizep = of_get_property(np, "i-cache-block-size", NULL); |
305 | if (lsizep == NULL) | |
306 | lsizep = of_get_property(np, "i-cache-line-size", NULL); | |
40ef8cbc PM |
307 | if (lsizep != NULL) |
308 | lsize = *lsizep; | |
309 | if (sizep == 0 || lsizep == 0) | |
310 | DBG("Argh, can't find icache properties ! " | |
311 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
312 | ||
a7f290da BH |
313 | ppc64_caches.isize = size; |
314 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
315 | ppc64_caches.log_iline_size = __ilog2(lsize); |
316 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
317 | } | |
318 | } | |
319 | ||
40ef8cbc PM |
320 | DBG(" <- initialize_cache_info()\n"); |
321 | } | |
322 | ||
40ef8cbc PM |
323 | |
324 | /* | |
325 | * Do some initial setup of the system. The parameters are those which | |
326 | * were passed in from the bootloader. | |
327 | */ | |
328 | void __init setup_system(void) | |
329 | { | |
330 | DBG(" -> setup_system()\n"); | |
331 | ||
826ea8f2 TB |
332 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
333 | * text (nop out sections not relevant to this CPU or this firmware) | |
42c4aaad | 334 | */ |
0909c8c2 | 335 | do_feature_fixups(cur_cpu_spec->cpu_features, |
42c4aaad | 336 | &__start___ftr_fixup, &__stop___ftr_fixup); |
7c03d653 BH |
337 | do_feature_fixups(cur_cpu_spec->mmu_features, |
338 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | |
826ea8f2 TB |
339 | do_feature_fixups(powerpc_firmware_features, |
340 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | |
2d1b2027 KG |
341 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
342 | &__start___lwsync_fixup, &__stop___lwsync_fixup); | |
42c4aaad | 343 | |
40ef8cbc PM |
344 | /* |
345 | * Unflatten the device-tree passed by prom_init or kexec | |
346 | */ | |
347 | unflatten_device_tree(); | |
348 | ||
349 | /* | |
350 | * Fill the ppc64_caches & systemcfg structures with informations | |
0ebfff14 | 351 | * retrieved from the device-tree. |
40ef8cbc PM |
352 | */ |
353 | initialize_cache_info(); | |
354 | ||
355 | #ifdef CONFIG_PPC_RTAS | |
356 | /* | |
357 | * Initialize RTAS if available | |
358 | */ | |
359 | rtas_initialize(); | |
360 | #endif /* CONFIG_PPC_RTAS */ | |
40ef8cbc PM |
361 | |
362 | /* | |
363 | * Check if we have an initrd provided via the device-tree | |
364 | */ | |
365 | check_for_initrd(); | |
40ef8cbc PM |
366 | |
367 | /* | |
368 | * Do some platform specific early initializations, that includes | |
369 | * setting up the hash table pointers. It also sets up some interrupt-mapping | |
370 | * related options that will be used by finish_device_tree() | |
371 | */ | |
57744ea9 GL |
372 | if (ppc_md.init_early) |
373 | ppc_md.init_early(); | |
40ef8cbc | 374 | |
463ce0e1 BH |
375 | /* |
376 | * We can discover serial ports now since the above did setup the | |
377 | * hash table management for us, thus ioremap works. We do that early | |
378 | * so that further code can be debugged | |
379 | */ | |
463ce0e1 | 380 | find_legacy_serial_ports(); |
463ce0e1 | 381 | |
40ef8cbc PM |
382 | /* |
383 | * Register early console | |
384 | */ | |
385 | register_early_udbg_console(); | |
40ef8cbc | 386 | |
47679283 ME |
387 | /* |
388 | * Initialize xmon | |
389 | */ | |
390 | xmon_setup(); | |
480f6f35 | 391 | |
5ad57078 | 392 | smp_setup_cpu_maps(); |
954e6da5 | 393 | check_smt_enabled(); |
40ef8cbc | 394 | |
f018b36f | 395 | #ifdef CONFIG_SMP |
40ef8cbc PM |
396 | /* Release secondary cpus out of their spinloops at 0x60 now that |
397 | * we can map physical -> logical CPU ids | |
398 | */ | |
399 | smp_release_cpus(); | |
f018b36f | 400 | #endif |
40ef8cbc | 401 | |
96b644bd | 402 | printk("Starting Linux PPC64 %s\n", init_utsname()->version); |
40ef8cbc PM |
403 | |
404 | printk("-----------------------------------------------------\n"); | |
fe333321 | 405 | printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); |
95f72d1e | 406 | printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); |
9697add0 AB |
407 | if (ppc64_caches.dline_size != 0x80) |
408 | printk("ppc64_caches.dcache_line_size = 0x%x\n", | |
409 | ppc64_caches.dline_size); | |
410 | if (ppc64_caches.iline_size != 0x80) | |
411 | printk("ppc64_caches.icache_line_size = 0x%x\n", | |
412 | ppc64_caches.iline_size); | |
94491685 | 413 | #ifdef CONFIG_PPC_STD_MMU_64 |
9697add0 AB |
414 | if (htab_address) |
415 | printk("htab_address = 0x%p\n", htab_address); | |
40ef8cbc | 416 | printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
94491685 | 417 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
b160544c | 418 | if (PHYSICAL_START > 0) |
e468455e ME |
419 | printk("physical_start = 0x%llx\n", |
420 | (unsigned long long)PHYSICAL_START); | |
40ef8cbc | 421 | printk("-----------------------------------------------------\n"); |
40ef8cbc | 422 | |
40ef8cbc PM |
423 | DBG(" <- setup_system()\n"); |
424 | } | |
425 | ||
095c7965 AB |
426 | static u64 slb0_limit(void) |
427 | { | |
428 | if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) { | |
429 | return 1UL << SID_SHIFT_1T; | |
430 | } | |
431 | return 1UL << SID_SHIFT; | |
432 | } | |
433 | ||
40ef8cbc PM |
434 | static void __init irqstack_early_init(void) |
435 | { | |
095c7965 | 436 | u64 limit = slb0_limit(); |
40ef8cbc PM |
437 | unsigned int i; |
438 | ||
439 | /* | |
8f4da26e AB |
440 | * Interrupt stacks must be in the first segment since we |
441 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 442 | */ |
0e551954 | 443 | for_each_possible_cpu(i) { |
3c726f8d | 444 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 445 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 446 | THREAD_SIZE, limit)); |
3c726f8d | 447 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 448 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 449 | THREAD_SIZE, limit)); |
40ef8cbc PM |
450 | } |
451 | } | |
40ef8cbc | 452 | |
2d27cfd3 BH |
453 | #ifdef CONFIG_PPC_BOOK3E |
454 | static void __init exc_lvl_early_init(void) | |
455 | { | |
456 | unsigned int i; | |
457 | ||
458 | for_each_possible_cpu(i) { | |
459 | critirq_ctx[i] = (struct thread_info *) | |
95f72d1e | 460 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 | 461 | dbgirq_ctx[i] = (struct thread_info *) |
95f72d1e | 462 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 | 463 | mcheckirq_ctx[i] = (struct thread_info *) |
95f72d1e | 464 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 BH |
465 | } |
466 | } | |
467 | #else | |
468 | #define exc_lvl_early_init() | |
469 | #endif | |
470 | ||
40ef8cbc PM |
471 | /* |
472 | * Stack space used when we detect a bad kernel stack pointer, and | |
473 | * early in SMP boots before relocation is enabled. | |
474 | */ | |
475 | static void __init emergency_stack_init(void) | |
476 | { | |
095c7965 | 477 | u64 limit; |
40ef8cbc PM |
478 | unsigned int i; |
479 | ||
480 | /* | |
481 | * Emergency stacks must be under 256MB, we cannot afford to take | |
482 | * SLB misses on them. The ABI also requires them to be 128-byte | |
483 | * aligned. | |
484 | * | |
485 | * Since we use these as temporary stacks during secondary CPU | |
486 | * bringup, we need to get at them in real mode. This means they | |
487 | * must also be within the RMO region. | |
488 | */ | |
cd3db0c4 | 489 | limit = min(slb0_limit(), ppc64_rma_size); |
40ef8cbc | 490 | |
3243d874 ME |
491 | for_each_possible_cpu(i) { |
492 | unsigned long sp; | |
95f72d1e | 493 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
3243d874 ME |
494 | sp += THREAD_SIZE; |
495 | paca[i].emergency_sp = __va(sp); | |
496 | } | |
40ef8cbc PM |
497 | } |
498 | ||
40ef8cbc | 499 | /* |
0f6b77ca AIB |
500 | * Called into from start_kernel this initializes bootmem, which is used |
501 | * to manage page allocation until mem_init is called. | |
40ef8cbc PM |
502 | */ |
503 | void __init setup_arch(char **cmdline_p) | |
504 | { | |
40ef8cbc PM |
505 | ppc64_boot_msg(0x12, "Setup Arch"); |
506 | ||
507 | *cmdline_p = cmd_line; | |
508 | ||
509 | /* | |
510 | * Set cache line size based on type of cpu as a default. | |
511 | * Systems with OF can look in the properties on the cpu node(s) | |
512 | * for a possibly more accurate value. | |
513 | */ | |
514 | dcache_bsize = ppc64_caches.dline_size; | |
515 | icache_bsize = ppc64_caches.iline_size; | |
516 | ||
517 | /* reboot on panic */ | |
518 | panic_timeout = 180; | |
40ef8cbc PM |
519 | |
520 | if (ppc_md.panic) | |
7e990266 | 521 | setup_panic(); |
40ef8cbc | 522 | |
4846c5de | 523 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
524 | init_mm.end_code = (unsigned long) _etext; |
525 | init_mm.end_data = (unsigned long) _edata; | |
526 | init_mm.brk = klimit; | |
527 | ||
528 | irqstack_early_init(); | |
2d27cfd3 | 529 | exc_lvl_early_init(); |
40ef8cbc PM |
530 | emergency_stack_init(); |
531 | ||
94491685 | 532 | #ifdef CONFIG_PPC_STD_MMU_64 |
40ef8cbc | 533 | stabs_alloc(); |
94491685 | 534 | #endif |
40ef8cbc PM |
535 | /* set up the bootmem stuff with available memory */ |
536 | do_init_bootmem(); | |
537 | sparse_init(); | |
538 | ||
0458060c PM |
539 | #ifdef CONFIG_DUMMY_CONSOLE |
540 | conswitchp = &dummy_con; | |
541 | #endif | |
542 | ||
38db7e74 GL |
543 | if (ppc_md.setup_arch) |
544 | ppc_md.setup_arch(); | |
40ef8cbc | 545 | |
40ef8cbc | 546 | paging_init(); |
6f0ef0f5 BH |
547 | |
548 | /* Initialize the MMU context management stuff */ | |
549 | mmu_context_init(); | |
550 | ||
40ef8cbc PM |
551 | ppc64_boot_msg(0x15, "Setup Done"); |
552 | } | |
553 | ||
554 | ||
555 | /* ToDo: do something useful if ppc_md is not yet setup. */ | |
556 | #define PPC64_LINUX_FUNCTION 0x0f000000 | |
557 | #define PPC64_IPL_MESSAGE 0xc0000000 | |
558 | #define PPC64_TERM_MESSAGE 0xb0000000 | |
559 | ||
560 | static void ppc64_do_msg(unsigned int src, const char *msg) | |
561 | { | |
562 | if (ppc_md.progress) { | |
563 | char buf[128]; | |
564 | ||
565 | sprintf(buf, "%08X\n", src); | |
566 | ppc_md.progress(buf, 0); | |
567 | snprintf(buf, 128, "%s", msg); | |
568 | ppc_md.progress(buf, 0); | |
569 | } | |
570 | } | |
571 | ||
572 | /* Print a boot progress message. */ | |
573 | void ppc64_boot_msg(unsigned int src, const char *msg) | |
574 | { | |
575 | ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); | |
576 | printk("[boot]%04x %s\n", src, msg); | |
577 | } | |
578 | ||
7a0268fa | 579 | #ifdef CONFIG_SMP |
c2a7e818 TH |
580 | #define PCPU_DYN_SIZE () |
581 | ||
582 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 583 | { |
c2a7e818 TH |
584 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
585 | __pa(MAX_DMA_ADDRESS)); | |
586 | } | |
7a0268fa | 587 | |
c2a7e818 TH |
588 | static void __init pcpu_fc_free(void *ptr, size_t size) |
589 | { | |
590 | free_bootmem(__pa(ptr), size); | |
591 | } | |
7a0268fa | 592 | |
c2a7e818 TH |
593 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
594 | { | |
595 | if (cpu_to_node(from) == cpu_to_node(to)) | |
596 | return LOCAL_DISTANCE; | |
597 | else | |
598 | return REMOTE_DISTANCE; | |
599 | } | |
600 | ||
ae01f84b AB |
601 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
602 | EXPORT_SYMBOL(__per_cpu_offset); | |
603 | ||
c2a7e818 TH |
604 | void __init setup_per_cpu_areas(void) |
605 | { | |
606 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
607 | size_t atom_size; | |
608 | unsigned long delta; | |
609 | unsigned int cpu; | |
610 | int rc; | |
611 | ||
612 | /* | |
613 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
614 | * to group units. For larger mappings, use 1M atom which | |
615 | * should be large enough to contain a number of units. | |
616 | */ | |
617 | if (mmu_linear_psize == MMU_PAGE_4K) | |
618 | atom_size = PAGE_SIZE; | |
619 | else | |
620 | atom_size = 1 << 20; | |
621 | ||
622 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
623 | pcpu_fc_alloc, pcpu_fc_free); | |
624 | if (rc < 0) | |
625 | panic("cannot initialize percpu area (err=%d)", rc); | |
626 | ||
627 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
628 | for_each_possible_cpu(cpu) { |
629 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
630 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
631 | } | |
7a0268fa AB |
632 | } |
633 | #endif | |
4cb3cee0 BH |
634 | |
635 | ||
636 | #ifdef CONFIG_PPC_INDIRECT_IO | |
637 | struct ppc_pci_io ppc_pci_io; | |
638 | EXPORT_SYMBOL(ppc_pci_io); | |
639 | #endif /* CONFIG_PPC_INDIRECT_IO */ | |
640 |