Commit | Line | Data |
---|---|---|
40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #undef DEBUG | |
14 | ||
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a6146888 BB |
38 | #include <linux/hugetlb.h> |
39 | ||
40ef8cbc | 40 | #include <asm/io.h> |
0cc4746c | 41 | #include <asm/kdump.h> |
40ef8cbc PM |
42 | #include <asm/prom.h> |
43 | #include <asm/processor.h> | |
44 | #include <asm/pgtable.h> | |
40ef8cbc PM |
45 | #include <asm/smp.h> |
46 | #include <asm/elf.h> | |
47 | #include <asm/machdep.h> | |
48 | #include <asm/paca.h> | |
40ef8cbc PM |
49 | #include <asm/time.h> |
50 | #include <asm/cputable.h> | |
51 | #include <asm/sections.h> | |
52 | #include <asm/btext.h> | |
53 | #include <asm/nvram.h> | |
54 | #include <asm/setup.h> | |
40ef8cbc PM |
55 | #include <asm/rtas.h> |
56 | #include <asm/iommu.h> | |
57 | #include <asm/serial.h> | |
58 | #include <asm/cache.h> | |
59 | #include <asm/page.h> | |
60 | #include <asm/mmu.h> | |
40ef8cbc | 61 | #include <asm/firmware.h> |
f78541dc | 62 | #include <asm/xmon.h> |
dcad47fc | 63 | #include <asm/udbg.h> |
593e537b | 64 | #include <asm/kexec.h> |
25d21ad6 | 65 | #include <asm/mmu_context.h> |
d36b4c4f | 66 | #include <asm/code-patching.h> |
aa04b4cc | 67 | #include <asm/kvm_ppc.h> |
a6146888 | 68 | #include <asm/hugetlb.h> |
40ef8cbc | 69 | |
66ba135c SR |
70 | #include "setup.h" |
71 | ||
40ef8cbc PM |
72 | #ifdef DEBUG |
73 | #define DBG(fmt...) udbg_printf(fmt) | |
74 | #else | |
75 | #define DBG(fmt...) | |
76 | #endif | |
77 | ||
40ef8cbc | 78 | int boot_cpuid = 0; |
7ac87abb | 79 | int __initdata spinning_secondaries; |
40ef8cbc PM |
80 | u64 ppc64_pft_size; |
81 | ||
dabcafd3 OJ |
82 | /* Pick defaults since we might want to patch instructions |
83 | * before we've read this from the device tree. | |
84 | */ | |
85 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
86 | .dline_size = 0x40, |
87 | .log_dline_size = 6, | |
88 | .iline_size = 0x40, | |
89 | .log_iline_size = 6 | |
dabcafd3 | 90 | }; |
40ef8cbc PM |
91 | EXPORT_SYMBOL_GPL(ppc64_caches); |
92 | ||
93 | /* | |
94 | * These are used in binfmt_elf.c to put aux entries on the stack | |
95 | * for each elf executable being started. | |
96 | */ | |
97 | int dcache_bsize; | |
98 | int icache_bsize; | |
99 | int ucache_bsize; | |
100 | ||
40ef8cbc PM |
101 | #ifdef CONFIG_SMP |
102 | ||
954e6da5 | 103 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
104 | |
105 | /* Look for ibm,smt-enabled OF option */ | |
106 | static void check_smt_enabled(void) | |
107 | { | |
108 | struct device_node *dn; | |
a7f67bdf | 109 | const char *smt_option; |
40ef8cbc | 110 | |
954e6da5 NF |
111 | /* Default to enabling all threads */ |
112 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 113 | |
954e6da5 NF |
114 | /* Allow the command line to overrule the OF option */ |
115 | if (smt_enabled_cmdline) { | |
116 | if (!strcmp(smt_enabled_cmdline, "on")) | |
117 | smt_enabled_at_boot = threads_per_core; | |
118 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
119 | smt_enabled_at_boot = 0; | |
120 | else { | |
121 | long smt; | |
122 | int rc; | |
123 | ||
124 | rc = strict_strtol(smt_enabled_cmdline, 10, &smt); | |
125 | if (!rc) | |
126 | smt_enabled_at_boot = | |
127 | min(threads_per_core, (int)smt); | |
128 | } | |
129 | } else { | |
130 | dn = of_find_node_by_path("/options"); | |
131 | if (dn) { | |
132 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
133 | NULL); | |
134 | ||
135 | if (smt_option) { | |
136 | if (!strcmp(smt_option, "on")) | |
137 | smt_enabled_at_boot = threads_per_core; | |
138 | else if (!strcmp(smt_option, "off")) | |
139 | smt_enabled_at_boot = 0; | |
140 | } | |
141 | ||
142 | of_node_put(dn); | |
143 | } | |
144 | } | |
40ef8cbc PM |
145 | } |
146 | ||
147 | /* Look for smt-enabled= cmdline option */ | |
148 | static int __init early_smt_enabled(char *p) | |
149 | { | |
954e6da5 | 150 | smt_enabled_cmdline = p; |
40ef8cbc PM |
151 | return 0; |
152 | } | |
153 | early_param("smt-enabled", early_smt_enabled); | |
154 | ||
5ad57078 PM |
155 | #else |
156 | #define check_smt_enabled() | |
40ef8cbc PM |
157 | #endif /* CONFIG_SMP */ |
158 | ||
40ef8cbc PM |
159 | /* |
160 | * Early initialization entry point. This is called by head.S | |
161 | * with MMU translation disabled. We rely on the "feature" of | |
162 | * the CPU that ignores the top 2 bits of the address in real | |
163 | * mode so we can access kernel globals normally provided we | |
164 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 165 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
166 | * data structures, and allocate & initialize the hash table |
167 | * and segment tables so we can start running with translation | |
168 | * enabled. | |
169 | * | |
170 | * It is this function which will call the probe() callback of | |
171 | * the various platform types and copy the matching one to the | |
172 | * global ppc_md structure. Your platform can eventually do | |
173 | * some very early initializations from the probe() routine, but | |
174 | * this is not recommended, be very careful as, for example, the | |
175 | * device-tree is not accessible via normal means at this point. | |
176 | */ | |
177 | ||
178 | void __init early_setup(unsigned long dt_ptr) | |
179 | { | |
24d96495 BH |
180 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
181 | ||
42c4aaad | 182 | /* Identify CPU type */ |
974a76f5 | 183 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 184 | |
33dbcf72 | 185 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
186 | initialise_paca(&boot_paca, 0); |
187 | setup_paca(&boot_paca); | |
33dbcf72 | 188 | |
945feb17 BH |
189 | /* Initialize lockdep early or else spinlocks will blow */ |
190 | lockdep_init(); | |
191 | ||
24d96495 BH |
192 | /* -------- printk is now safe to use ------- */ |
193 | ||
f2fd2513 BH |
194 | /* Enable early debugging if any specified (see udbg.h) */ |
195 | udbg_early_init(); | |
196 | ||
e8222502 | 197 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 198 | |
40ef8cbc | 199 | /* |
3c607ce2 LV |
200 | * Do early initialization using the flattened device |
201 | * tree, such as retrieving the physical memory map or | |
202 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
203 | */ |
204 | early_init_devtree(__va(dt_ptr)); | |
205 | ||
4df20460 | 206 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 207 | setup_paca(&paca[boot_cpuid]); |
4df20460 AB |
208 | |
209 | /* Fix up paca fields required for the boot cpu */ | |
210 | get_paca()->cpu_start = 1; | |
466921c5 ME |
211 | /* Allow percpu accesses to "work" until we setup percpu data */ |
212 | get_paca()->data_offset = 0; | |
4df20460 | 213 | |
e8222502 BH |
214 | /* Probe the machine type */ |
215 | probe_machine(); | |
40ef8cbc | 216 | |
47310413 | 217 | setup_kdump_trampoline(); |
0cc4746c | 218 | |
40ef8cbc PM |
219 | DBG("Found, Initializing memory management...\n"); |
220 | ||
757c74d2 BH |
221 | /* Initialize the hash table or TLB handling */ |
222 | early_init_mmu(); | |
40ef8cbc | 223 | |
a6146888 BB |
224 | /* |
225 | * Reserve any gigantic pages requested on the command line. | |
226 | * memblock needs to have been initialized by the time this is | |
227 | * called since this will reserve memory. | |
228 | */ | |
229 | reserve_hugetlb_gpages(); | |
230 | ||
40ef8cbc PM |
231 | DBG(" <- early_setup()\n"); |
232 | } | |
233 | ||
799d6046 PM |
234 | #ifdef CONFIG_SMP |
235 | void early_setup_secondary(void) | |
236 | { | |
d04c56f7 | 237 | /* Mark interrupts enabled in PACA */ |
757c74d2 | 238 | get_paca()->soft_enabled = 0; |
799d6046 | 239 | |
757c74d2 BH |
240 | /* Initialize the hash table or TLB handling */ |
241 | early_init_mmu_secondary(); | |
799d6046 PM |
242 | } |
243 | ||
244 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 245 | |
b8f51021 ME |
246 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
247 | void smp_release_cpus(void) | |
248 | { | |
758438a7 | 249 | unsigned long *ptr; |
9d07bc84 | 250 | int i; |
b8f51021 ME |
251 | |
252 | DBG(" -> smp_release_cpus()\n"); | |
253 | ||
254 | /* All secondary cpus are spinning on a common spinloop, release them | |
255 | * all now so they can start to spin on their individual paca | |
256 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
257 | * of the common spinloop. | |
1f6a93e4 | 258 | */ |
b8f51021 | 259 | |
758438a7 ME |
260 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
261 | - PHYSICAL_START); | |
1f6a93e4 | 262 | *ptr = __pa(generic_secondary_smp_init); |
9d07bc84 BH |
263 | |
264 | /* And wait a bit for them to catch up */ | |
265 | for (i = 0; i < 100000; i++) { | |
266 | mb(); | |
267 | HMT_low(); | |
7ac87abb | 268 | if (spinning_secondaries == 0) |
9d07bc84 BH |
269 | break; |
270 | udelay(1); | |
271 | } | |
7ac87abb | 272 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
273 | |
274 | DBG(" <- smp_release_cpus()\n"); | |
275 | } | |
276 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
277 | ||
40ef8cbc | 278 | /* |
799d6046 PM |
279 | * Initialize some remaining members of the ppc64_caches and systemcfg |
280 | * structures | |
40ef8cbc PM |
281 | * (at least until we get rid of them completely). This is mostly some |
282 | * cache informations about the CPU that will be used by cache flush | |
283 | * routines and/or provided to userland | |
284 | */ | |
285 | static void __init initialize_cache_info(void) | |
286 | { | |
287 | struct device_node *np; | |
288 | unsigned long num_cpus = 0; | |
289 | ||
290 | DBG(" -> initialize_cache_info()\n"); | |
291 | ||
94db7c5e | 292 | for_each_node_by_type(np, "cpu") { |
40ef8cbc PM |
293 | num_cpus += 1; |
294 | ||
dfbe93a2 AB |
295 | /* |
296 | * We're assuming *all* of the CPUs have the same | |
40ef8cbc PM |
297 | * d-cache and i-cache sizes... -Peter |
298 | */ | |
dfbe93a2 | 299 | if (num_cpus == 1) { |
a7f67bdf | 300 | const u32 *sizep, *lsizep; |
40ef8cbc | 301 | u32 size, lsize; |
40ef8cbc PM |
302 | |
303 | size = 0; | |
304 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 305 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc PM |
306 | if (sizep != NULL) |
307 | size = *sizep; | |
dfbe93a2 AB |
308 | lsizep = of_get_property(np, "d-cache-block-size", |
309 | NULL); | |
20474abd BH |
310 | /* fallback if block size missing */ |
311 | if (lsizep == NULL) | |
dfbe93a2 AB |
312 | lsizep = of_get_property(np, |
313 | "d-cache-line-size", | |
314 | NULL); | |
40ef8cbc PM |
315 | if (lsizep != NULL) |
316 | lsize = *lsizep; | |
317 | if (sizep == 0 || lsizep == 0) | |
318 | DBG("Argh, can't find dcache properties ! " | |
319 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
320 | ||
a7f290da BH |
321 | ppc64_caches.dsize = size; |
322 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
323 | ppc64_caches.log_dline_size = __ilog2(lsize); |
324 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
325 | ||
326 | size = 0; | |
327 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 328 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc PM |
329 | if (sizep != NULL) |
330 | size = *sizep; | |
dfbe93a2 AB |
331 | lsizep = of_get_property(np, "i-cache-block-size", |
332 | NULL); | |
20474abd | 333 | if (lsizep == NULL) |
dfbe93a2 AB |
334 | lsizep = of_get_property(np, |
335 | "i-cache-line-size", | |
336 | NULL); | |
40ef8cbc PM |
337 | if (lsizep != NULL) |
338 | lsize = *lsizep; | |
339 | if (sizep == 0 || lsizep == 0) | |
340 | DBG("Argh, can't find icache properties ! " | |
341 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
342 | ||
a7f290da BH |
343 | ppc64_caches.isize = size; |
344 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
345 | ppc64_caches.log_iline_size = __ilog2(lsize); |
346 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
347 | } | |
348 | } | |
349 | ||
40ef8cbc PM |
350 | DBG(" <- initialize_cache_info()\n"); |
351 | } | |
352 | ||
40ef8cbc PM |
353 | |
354 | /* | |
355 | * Do some initial setup of the system. The parameters are those which | |
356 | * were passed in from the bootloader. | |
357 | */ | |
358 | void __init setup_system(void) | |
359 | { | |
360 | DBG(" -> setup_system()\n"); | |
361 | ||
826ea8f2 TB |
362 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
363 | * text (nop out sections not relevant to this CPU or this firmware) | |
42c4aaad | 364 | */ |
0909c8c2 | 365 | do_feature_fixups(cur_cpu_spec->cpu_features, |
42c4aaad | 366 | &__start___ftr_fixup, &__stop___ftr_fixup); |
7c03d653 BH |
367 | do_feature_fixups(cur_cpu_spec->mmu_features, |
368 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | |
826ea8f2 TB |
369 | do_feature_fixups(powerpc_firmware_features, |
370 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | |
2d1b2027 KG |
371 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
372 | &__start___lwsync_fixup, &__stop___lwsync_fixup); | |
d715e433 | 373 | do_final_fixups(); |
42c4aaad | 374 | |
40ef8cbc PM |
375 | /* |
376 | * Unflatten the device-tree passed by prom_init or kexec | |
377 | */ | |
378 | unflatten_device_tree(); | |
379 | ||
380 | /* | |
381 | * Fill the ppc64_caches & systemcfg structures with informations | |
0ebfff14 | 382 | * retrieved from the device-tree. |
40ef8cbc PM |
383 | */ |
384 | initialize_cache_info(); | |
385 | ||
386 | #ifdef CONFIG_PPC_RTAS | |
387 | /* | |
388 | * Initialize RTAS if available | |
389 | */ | |
390 | rtas_initialize(); | |
391 | #endif /* CONFIG_PPC_RTAS */ | |
40ef8cbc PM |
392 | |
393 | /* | |
394 | * Check if we have an initrd provided via the device-tree | |
395 | */ | |
396 | check_for_initrd(); | |
40ef8cbc PM |
397 | |
398 | /* | |
399 | * Do some platform specific early initializations, that includes | |
400 | * setting up the hash table pointers. It also sets up some interrupt-mapping | |
401 | * related options that will be used by finish_device_tree() | |
402 | */ | |
57744ea9 GL |
403 | if (ppc_md.init_early) |
404 | ppc_md.init_early(); | |
40ef8cbc | 405 | |
463ce0e1 BH |
406 | /* |
407 | * We can discover serial ports now since the above did setup the | |
408 | * hash table management for us, thus ioremap works. We do that early | |
409 | * so that further code can be debugged | |
410 | */ | |
463ce0e1 | 411 | find_legacy_serial_ports(); |
463ce0e1 | 412 | |
40ef8cbc PM |
413 | /* |
414 | * Register early console | |
415 | */ | |
416 | register_early_udbg_console(); | |
40ef8cbc | 417 | |
47679283 ME |
418 | /* |
419 | * Initialize xmon | |
420 | */ | |
421 | xmon_setup(); | |
480f6f35 | 422 | |
5ad57078 | 423 | smp_setup_cpu_maps(); |
954e6da5 | 424 | check_smt_enabled(); |
40ef8cbc | 425 | |
f018b36f | 426 | #ifdef CONFIG_SMP |
40ef8cbc PM |
427 | /* Release secondary cpus out of their spinloops at 0x60 now that |
428 | * we can map physical -> logical CPU ids | |
429 | */ | |
430 | smp_release_cpus(); | |
f018b36f | 431 | #endif |
40ef8cbc | 432 | |
96b644bd | 433 | printk("Starting Linux PPC64 %s\n", init_utsname()->version); |
40ef8cbc PM |
434 | |
435 | printk("-----------------------------------------------------\n"); | |
fe333321 | 436 | printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); |
95f72d1e | 437 | printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); |
9697add0 AB |
438 | if (ppc64_caches.dline_size != 0x80) |
439 | printk("ppc64_caches.dcache_line_size = 0x%x\n", | |
440 | ppc64_caches.dline_size); | |
441 | if (ppc64_caches.iline_size != 0x80) | |
442 | printk("ppc64_caches.icache_line_size = 0x%x\n", | |
443 | ppc64_caches.iline_size); | |
94491685 | 444 | #ifdef CONFIG_PPC_STD_MMU_64 |
9697add0 AB |
445 | if (htab_address) |
446 | printk("htab_address = 0x%p\n", htab_address); | |
40ef8cbc | 447 | printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
94491685 | 448 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
b160544c | 449 | if (PHYSICAL_START > 0) |
e468455e ME |
450 | printk("physical_start = 0x%llx\n", |
451 | (unsigned long long)PHYSICAL_START); | |
40ef8cbc | 452 | printk("-----------------------------------------------------\n"); |
40ef8cbc | 453 | |
40ef8cbc PM |
454 | DBG(" <- setup_system()\n"); |
455 | } | |
456 | ||
40bd587a BH |
457 | /* This returns the limit below which memory accesses to the linear |
458 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
459 | * used to allocate interrupt or emergency stacks for which our | |
460 | * exception entry path doesn't deal with being interrupted. | |
461 | */ | |
462 | static u64 safe_stack_limit(void) | |
095c7965 | 463 | { |
40bd587a BH |
464 | #ifdef CONFIG_PPC_BOOK3E |
465 | /* Freescale BookE bolts the entire linear mapping */ | |
466 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
467 | return linear_map_top; | |
468 | /* Other BookE, we assume the first GB is bolted */ | |
469 | return 1ul << 30; | |
470 | #else | |
471 | /* BookS, the first segment is bolted */ | |
472 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 473 | return 1UL << SID_SHIFT_1T; |
095c7965 | 474 | return 1UL << SID_SHIFT; |
40bd587a | 475 | #endif |
095c7965 AB |
476 | } |
477 | ||
40ef8cbc PM |
478 | static void __init irqstack_early_init(void) |
479 | { | |
40bd587a | 480 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
481 | unsigned int i; |
482 | ||
483 | /* | |
8f4da26e AB |
484 | * Interrupt stacks must be in the first segment since we |
485 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 486 | */ |
0e551954 | 487 | for_each_possible_cpu(i) { |
3c726f8d | 488 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 489 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 490 | THREAD_SIZE, limit)); |
3c726f8d | 491 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 492 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 493 | THREAD_SIZE, limit)); |
40ef8cbc PM |
494 | } |
495 | } | |
40ef8cbc | 496 | |
2d27cfd3 BH |
497 | #ifdef CONFIG_PPC_BOOK3E |
498 | static void __init exc_lvl_early_init(void) | |
499 | { | |
d36b4c4f KG |
500 | extern unsigned int interrupt_base_book3e; |
501 | extern unsigned int exc_debug_debug_book3e; | |
502 | ||
2d27cfd3 BH |
503 | unsigned int i; |
504 | ||
505 | for_each_possible_cpu(i) { | |
506 | critirq_ctx[i] = (struct thread_info *) | |
95f72d1e | 507 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 | 508 | dbgirq_ctx[i] = (struct thread_info *) |
95f72d1e | 509 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 | 510 | mcheckirq_ctx[i] = (struct thread_info *) |
95f72d1e | 511 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
2d27cfd3 | 512 | } |
d36b4c4f KG |
513 | |
514 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
515 | patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1, | |
516 | (unsigned long)&exc_debug_debug_book3e, 0); | |
2d27cfd3 BH |
517 | } |
518 | #else | |
519 | #define exc_lvl_early_init() | |
520 | #endif | |
521 | ||
40ef8cbc PM |
522 | /* |
523 | * Stack space used when we detect a bad kernel stack pointer, and | |
524 | * early in SMP boots before relocation is enabled. | |
525 | */ | |
526 | static void __init emergency_stack_init(void) | |
527 | { | |
095c7965 | 528 | u64 limit; |
40ef8cbc PM |
529 | unsigned int i; |
530 | ||
531 | /* | |
532 | * Emergency stacks must be under 256MB, we cannot afford to take | |
533 | * SLB misses on them. The ABI also requires them to be 128-byte | |
534 | * aligned. | |
535 | * | |
536 | * Since we use these as temporary stacks during secondary CPU | |
537 | * bringup, we need to get at them in real mode. This means they | |
538 | * must also be within the RMO region. | |
539 | */ | |
40bd587a | 540 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 541 | |
3243d874 ME |
542 | for_each_possible_cpu(i) { |
543 | unsigned long sp; | |
95f72d1e | 544 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
3243d874 ME |
545 | sp += THREAD_SIZE; |
546 | paca[i].emergency_sp = __va(sp); | |
547 | } | |
40ef8cbc PM |
548 | } |
549 | ||
40ef8cbc | 550 | /* |
0f6b77ca AIB |
551 | * Called into from start_kernel this initializes bootmem, which is used |
552 | * to manage page allocation until mem_init is called. | |
40ef8cbc PM |
553 | */ |
554 | void __init setup_arch(char **cmdline_p) | |
555 | { | |
40ef8cbc PM |
556 | ppc64_boot_msg(0x12, "Setup Arch"); |
557 | ||
558 | *cmdline_p = cmd_line; | |
559 | ||
560 | /* | |
561 | * Set cache line size based on type of cpu as a default. | |
562 | * Systems with OF can look in the properties on the cpu node(s) | |
563 | * for a possibly more accurate value. | |
564 | */ | |
565 | dcache_bsize = ppc64_caches.dline_size; | |
566 | icache_bsize = ppc64_caches.iline_size; | |
567 | ||
568 | /* reboot on panic */ | |
569 | panic_timeout = 180; | |
40ef8cbc PM |
570 | |
571 | if (ppc_md.panic) | |
7e990266 | 572 | setup_panic(); |
40ef8cbc | 573 | |
4846c5de | 574 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
575 | init_mm.end_code = (unsigned long) _etext; |
576 | init_mm.end_data = (unsigned long) _edata; | |
577 | init_mm.brk = klimit; | |
578 | ||
579 | irqstack_early_init(); | |
2d27cfd3 | 580 | exc_lvl_early_init(); |
40ef8cbc PM |
581 | emergency_stack_init(); |
582 | ||
94491685 | 583 | #ifdef CONFIG_PPC_STD_MMU_64 |
40ef8cbc | 584 | stabs_alloc(); |
94491685 | 585 | #endif |
40ef8cbc PM |
586 | /* set up the bootmem stuff with available memory */ |
587 | do_init_bootmem(); | |
588 | sparse_init(); | |
589 | ||
0458060c PM |
590 | #ifdef CONFIG_DUMMY_CONSOLE |
591 | conswitchp = &dummy_con; | |
592 | #endif | |
593 | ||
38db7e74 GL |
594 | if (ppc_md.setup_arch) |
595 | ppc_md.setup_arch(); | |
40ef8cbc | 596 | |
40ef8cbc | 597 | paging_init(); |
6f0ef0f5 BH |
598 | |
599 | /* Initialize the MMU context management stuff */ | |
600 | mmu_context_init(); | |
601 | ||
b4e70611 | 602 | kvm_linear_init(); |
aa04b4cc | 603 | |
61e2390e MN |
604 | /* Interrupt code needs to be 64K-aligned */ |
605 | if ((unsigned long)_stext & 0xffff) | |
606 | panic("Kernelbase not 64K-aligned (0x%lx)!\n", | |
607 | (unsigned long)_stext); | |
608 | ||
40ef8cbc PM |
609 | ppc64_boot_msg(0x15, "Setup Done"); |
610 | } | |
611 | ||
612 | ||
613 | /* ToDo: do something useful if ppc_md is not yet setup. */ | |
614 | #define PPC64_LINUX_FUNCTION 0x0f000000 | |
615 | #define PPC64_IPL_MESSAGE 0xc0000000 | |
616 | #define PPC64_TERM_MESSAGE 0xb0000000 | |
617 | ||
618 | static void ppc64_do_msg(unsigned int src, const char *msg) | |
619 | { | |
620 | if (ppc_md.progress) { | |
621 | char buf[128]; | |
622 | ||
623 | sprintf(buf, "%08X\n", src); | |
624 | ppc_md.progress(buf, 0); | |
625 | snprintf(buf, 128, "%s", msg); | |
626 | ppc_md.progress(buf, 0); | |
627 | } | |
628 | } | |
629 | ||
630 | /* Print a boot progress message. */ | |
631 | void ppc64_boot_msg(unsigned int src, const char *msg) | |
632 | { | |
633 | ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); | |
634 | printk("[boot]%04x %s\n", src, msg); | |
635 | } | |
636 | ||
7a0268fa | 637 | #ifdef CONFIG_SMP |
c2a7e818 TH |
638 | #define PCPU_DYN_SIZE () |
639 | ||
640 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 641 | { |
c2a7e818 TH |
642 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
643 | __pa(MAX_DMA_ADDRESS)); | |
644 | } | |
7a0268fa | 645 | |
c2a7e818 TH |
646 | static void __init pcpu_fc_free(void *ptr, size_t size) |
647 | { | |
648 | free_bootmem(__pa(ptr), size); | |
649 | } | |
7a0268fa | 650 | |
c2a7e818 TH |
651 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
652 | { | |
653 | if (cpu_to_node(from) == cpu_to_node(to)) | |
654 | return LOCAL_DISTANCE; | |
655 | else | |
656 | return REMOTE_DISTANCE; | |
657 | } | |
658 | ||
ae01f84b AB |
659 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
660 | EXPORT_SYMBOL(__per_cpu_offset); | |
661 | ||
c2a7e818 TH |
662 | void __init setup_per_cpu_areas(void) |
663 | { | |
664 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
665 | size_t atom_size; | |
666 | unsigned long delta; | |
667 | unsigned int cpu; | |
668 | int rc; | |
669 | ||
670 | /* | |
671 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
672 | * to group units. For larger mappings, use 1M atom which | |
673 | * should be large enough to contain a number of units. | |
674 | */ | |
675 | if (mmu_linear_psize == MMU_PAGE_4K) | |
676 | atom_size = PAGE_SIZE; | |
677 | else | |
678 | atom_size = 1 << 20; | |
679 | ||
680 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
681 | pcpu_fc_alloc, pcpu_fc_free); | |
682 | if (rc < 0) | |
683 | panic("cannot initialize percpu area (err=%d)", rc); | |
684 | ||
685 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
686 | for_each_possible_cpu(cpu) { |
687 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
688 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
689 | } | |
7a0268fa AB |
690 | } |
691 | #endif | |
4cb3cee0 BH |
692 | |
693 | ||
694 | #ifdef CONFIG_PPC_INDIRECT_IO | |
695 | struct ppc_pci_io ppc_pci_io; | |
696 | EXPORT_SYMBOL(ppc_pci_io); | |
697 | #endif /* CONFIG_PPC_INDIRECT_IO */ | |
698 |