Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * SMP support for ppc. | |
3 | * | |
4 | * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great | |
5 | * deal of code from the sparc and intel versions. | |
6 | * | |
7 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
8 | * | |
9 | * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and | |
10 | * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
16 | */ | |
17 | ||
18 | #undef DEBUG | |
19 | ||
1da177e4 | 20 | #include <linux/kernel.h> |
4b16f8e2 | 21 | #include <linux/export.h> |
1da177e4 LT |
22 | #include <linux/sched.h> |
23 | #include <linux/smp.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/cache.h> | |
29 | #include <linux/err.h> | |
8a25a2fd | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include <linux/cpu.h> |
32 | #include <linux/notifier.h> | |
4b703a23 | 33 | #include <linux/topology.h> |
1da177e4 LT |
34 | |
35 | #include <asm/ptrace.h> | |
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <asm/irq.h> |
1b67bee1 | 38 | #include <asm/hw_irq.h> |
441c19c8 | 39 | #include <asm/kvm_ppc.h> |
1da177e4 LT |
40 | #include <asm/page.h> |
41 | #include <asm/pgtable.h> | |
42 | #include <asm/prom.h> | |
43 | #include <asm/smp.h> | |
1da177e4 LT |
44 | #include <asm/time.h> |
45 | #include <asm/machdep.h> | |
e2075f79 | 46 | #include <asm/cputhreads.h> |
1da177e4 | 47 | #include <asm/cputable.h> |
bbeb3f4c | 48 | #include <asm/mpic.h> |
a7f290da | 49 | #include <asm/vdso_datapage.h> |
5ad57078 PM |
50 | #ifdef CONFIG_PPC64 |
51 | #include <asm/paca.h> | |
52 | #endif | |
18ad51dd | 53 | #include <asm/vdso.h> |
ae3a197e | 54 | #include <asm/debug.h> |
1217d34b | 55 | #include <asm/kexec.h> |
5ad57078 | 56 | |
1da177e4 | 57 | #ifdef DEBUG |
f9e4ec57 | 58 | #include <asm/udbg.h> |
1da177e4 LT |
59 | #define DBG(fmt...) udbg_printf(fmt) |
60 | #else | |
61 | #define DBG(fmt...) | |
62 | #endif | |
63 | ||
c56e5853 | 64 | #ifdef CONFIG_HOTPLUG_CPU |
fb82b839 BH |
65 | /* State of each CPU during hotplug phases */ |
66 | static DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
c56e5853 BH |
67 | #endif |
68 | ||
f9e4ec57 ME |
69 | struct thread_info *secondary_ti; |
70 | ||
cc1ba8ea AB |
71 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
72 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); | |
1da177e4 | 73 | |
d5a7430d | 74 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
440a0857 | 75 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
1da177e4 | 76 | |
5ad57078 | 77 | /* SMP operations for this machine */ |
1da177e4 LT |
78 | struct smp_ops_t *smp_ops; |
79 | ||
7ccbe504 BH |
80 | /* Can't be static due to PowerMac hackery */ |
81 | volatile unsigned int cpu_callin_map[NR_CPUS]; | |
1da177e4 | 82 | |
1da177e4 LT |
83 | int smt_enabled_at_boot = 1; |
84 | ||
cc532915 ME |
85 | static void (*crash_ipi_function_ptr)(struct pt_regs *) = NULL; |
86 | ||
3cd85250 AF |
87 | /* |
88 | * Returns 1 if the specified cpu should be brought up during boot. | |
89 | * Used to inhibit booting threads if they've been disabled or | |
90 | * limited on the command line | |
91 | */ | |
92 | int smp_generic_cpu_bootable(unsigned int nr) | |
93 | { | |
94 | /* Special case - we inhibit secondary thread startup | |
95 | * during boot if the user requests it. | |
96 | */ | |
97 | if (system_state == SYSTEM_BOOTING && cpu_has_feature(CPU_FTR_SMT)) { | |
98 | if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) | |
99 | return 0; | |
100 | if (smt_enabled_at_boot | |
101 | && cpu_thread_in_core(nr) >= smt_enabled_at_boot) | |
102 | return 0; | |
103 | } | |
104 | ||
105 | return 1; | |
106 | } | |
107 | ||
108 | ||
5ad57078 | 109 | #ifdef CONFIG_PPC64 |
cad5cef6 | 110 | int smp_generic_kick_cpu(int nr) |
1da177e4 LT |
111 | { |
112 | BUG_ON(nr < 0 || nr >= NR_CPUS); | |
113 | ||
114 | /* | |
115 | * The processor is currently spinning, waiting for the | |
116 | * cpu_start field to become non-zero After we set cpu_start, | |
117 | * the processor will continue on to secondary_start | |
118 | */ | |
fb82b839 BH |
119 | if (!paca[nr].cpu_start) { |
120 | paca[nr].cpu_start = 1; | |
121 | smp_mb(); | |
122 | return 0; | |
123 | } | |
124 | ||
125 | #ifdef CONFIG_HOTPLUG_CPU | |
126 | /* | |
127 | * Ok it's not there, so it might be soft-unplugged, let's | |
128 | * try to bring it back | |
129 | */ | |
ae5cab47 | 130 | generic_set_cpu_up(nr); |
fb82b839 BH |
131 | smp_wmb(); |
132 | smp_send_reschedule(nr); | |
133 | #endif /* CONFIG_HOTPLUG_CPU */ | |
de300974 ME |
134 | |
135 | return 0; | |
1da177e4 | 136 | } |
fb82b839 | 137 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 138 | |
25ddd738 MM |
139 | static irqreturn_t call_function_action(int irq, void *data) |
140 | { | |
141 | generic_smp_call_function_interrupt(); | |
142 | return IRQ_HANDLED; | |
143 | } | |
144 | ||
145 | static irqreturn_t reschedule_action(int irq, void *data) | |
146 | { | |
184748cc | 147 | scheduler_ipi(); |
25ddd738 MM |
148 | return IRQ_HANDLED; |
149 | } | |
150 | ||
1b67bee1 | 151 | static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) |
25ddd738 | 152 | { |
1b67bee1 | 153 | tick_broadcast_ipi_handler(); |
25ddd738 MM |
154 | return IRQ_HANDLED; |
155 | } | |
156 | ||
7ef71d75 | 157 | static irqreturn_t debug_ipi_action(int irq, void *data) |
25ddd738 | 158 | { |
23d72bfd MM |
159 | if (crash_ipi_function_ptr) { |
160 | crash_ipi_function_ptr(get_irq_regs()); | |
161 | return IRQ_HANDLED; | |
162 | } | |
163 | ||
164 | #ifdef CONFIG_DEBUGGER | |
165 | debugger_ipi(get_irq_regs()); | |
166 | #endif /* CONFIG_DEBUGGER */ | |
167 | ||
25ddd738 MM |
168 | return IRQ_HANDLED; |
169 | } | |
170 | ||
171 | static irq_handler_t smp_ipi_action[] = { | |
172 | [PPC_MSG_CALL_FUNCTION] = call_function_action, | |
173 | [PPC_MSG_RESCHEDULE] = reschedule_action, | |
1b67bee1 | 174 | [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, |
25ddd738 MM |
175 | [PPC_MSG_DEBUGGER_BREAK] = debug_ipi_action, |
176 | }; | |
177 | ||
178 | const char *smp_ipi_name[] = { | |
179 | [PPC_MSG_CALL_FUNCTION] = "ipi call function", | |
180 | [PPC_MSG_RESCHEDULE] = "ipi reschedule", | |
1b67bee1 | 181 | [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", |
25ddd738 MM |
182 | [PPC_MSG_DEBUGGER_BREAK] = "ipi debugger", |
183 | }; | |
184 | ||
185 | /* optional function to request ipi, for controllers with >= 4 ipis */ | |
186 | int smp_request_message_ipi(int virq, int msg) | |
187 | { | |
188 | int err; | |
189 | ||
190 | if (msg < 0 || msg > PPC_MSG_DEBUGGER_BREAK) { | |
191 | return -EINVAL; | |
192 | } | |
193 | #if !defined(CONFIG_DEBUGGER) && !defined(CONFIG_KEXEC) | |
194 | if (msg == PPC_MSG_DEBUGGER_BREAK) { | |
195 | return 1; | |
196 | } | |
197 | #endif | |
3b5e16d7 | 198 | err = request_irq(virq, smp_ipi_action[msg], |
e6651de9 | 199 | IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, |
b0d436c7 | 200 | smp_ipi_name[msg], NULL); |
25ddd738 MM |
201 | WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", |
202 | virq, smp_ipi_name[msg], err); | |
203 | ||
204 | return err; | |
205 | } | |
206 | ||
1ece355b | 207 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
23d72bfd | 208 | struct cpu_messages { |
bd7f561f | 209 | long messages; /* current messages */ |
23d72bfd MM |
210 | unsigned long data; /* data for cause ipi */ |
211 | }; | |
212 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); | |
213 | ||
214 | void smp_muxed_ipi_set_data(int cpu, unsigned long data) | |
215 | { | |
216 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
217 | ||
218 | info->data = data; | |
219 | } | |
220 | ||
31639c77 | 221 | void smp_muxed_ipi_set_message(int cpu, int msg) |
23d72bfd MM |
222 | { |
223 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
71454272 | 224 | char *message = (char *)&info->messages; |
23d72bfd | 225 | |
9fb1b36c PM |
226 | /* |
227 | * Order previous accesses before accesses in the IPI handler. | |
228 | */ | |
229 | smp_mb(); | |
71454272 | 230 | message[msg] = 1; |
31639c77 SW |
231 | } |
232 | ||
233 | void smp_muxed_ipi_message_pass(int cpu, int msg) | |
234 | { | |
235 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
236 | ||
237 | smp_muxed_ipi_set_message(cpu, msg); | |
9fb1b36c PM |
238 | /* |
239 | * cause_ipi functions are required to include a full barrier | |
240 | * before doing whatever causes the IPI. | |
241 | */ | |
23d72bfd MM |
242 | smp_ops->cause_ipi(cpu, info->data); |
243 | } | |
244 | ||
0654de1c | 245 | #ifdef __BIG_ENDIAN__ |
bd7f561f | 246 | #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A))) |
0654de1c | 247 | #else |
bd7f561f | 248 | #define IPI_MESSAGE(A) (1uL << (8 * (A))) |
0654de1c AB |
249 | #endif |
250 | ||
23d72bfd MM |
251 | irqreturn_t smp_ipi_demux(void) |
252 | { | |
69111bac | 253 | struct cpu_messages *info = this_cpu_ptr(&ipi_message); |
bd7f561f | 254 | unsigned long all; |
23d72bfd MM |
255 | |
256 | mb(); /* order any irq clear */ | |
71454272 MM |
257 | |
258 | do { | |
9fb1b36c | 259 | all = xchg(&info->messages, 0); |
e17769eb SW |
260 | #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) |
261 | /* | |
262 | * Must check for PPC_MSG_RM_HOST_ACTION messages | |
263 | * before PPC_MSG_CALL_FUNCTION messages because when | |
264 | * a VM is destroyed, we call kick_all_cpus_sync() | |
265 | * to ensure that any pending PPC_MSG_RM_HOST_ACTION | |
266 | * messages have completed before we free any VCPUs. | |
267 | */ | |
268 | if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION)) | |
269 | kvmppc_xics_ipi_action(); | |
270 | #endif | |
0654de1c | 271 | if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) |
23d72bfd | 272 | generic_smp_call_function_interrupt(); |
0654de1c | 273 | if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) |
880102e7 | 274 | scheduler_ipi(); |
1b67bee1 SB |
275 | if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) |
276 | tick_broadcast_ipi_handler(); | |
0654de1c | 277 | if (all & IPI_MESSAGE(PPC_MSG_DEBUGGER_BREAK)) |
23d72bfd | 278 | debug_ipi_action(0, NULL); |
71454272 MM |
279 | } while (info->messages); |
280 | ||
23d72bfd MM |
281 | return IRQ_HANDLED; |
282 | } | |
1ece355b | 283 | #endif /* CONFIG_PPC_SMP_MUXED_IPI */ |
23d72bfd | 284 | |
9ca980dc PM |
285 | static inline void do_message_pass(int cpu, int msg) |
286 | { | |
287 | if (smp_ops->message_pass) | |
288 | smp_ops->message_pass(cpu, msg); | |
289 | #ifdef CONFIG_PPC_SMP_MUXED_IPI | |
290 | else | |
291 | smp_muxed_ipi_message_pass(cpu, msg); | |
292 | #endif | |
293 | } | |
294 | ||
1da177e4 LT |
295 | void smp_send_reschedule(int cpu) |
296 | { | |
8cffc6ac | 297 | if (likely(smp_ops)) |
9ca980dc | 298 | do_message_pass(cpu, PPC_MSG_RESCHEDULE); |
1da177e4 | 299 | } |
de56a948 | 300 | EXPORT_SYMBOL_GPL(smp_send_reschedule); |
1da177e4 | 301 | |
b7d7a240 JA |
302 | void arch_send_call_function_single_ipi(int cpu) |
303 | { | |
402d9a1e | 304 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
305 | } |
306 | ||
f063ea02 | 307 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
b7d7a240 JA |
308 | { |
309 | unsigned int cpu; | |
310 | ||
f063ea02 | 311 | for_each_cpu(cpu, mask) |
9ca980dc | 312 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
313 | } |
314 | ||
1b67bee1 SB |
315 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
316 | void tick_broadcast(const struct cpumask *mask) | |
317 | { | |
318 | unsigned int cpu; | |
319 | ||
320 | for_each_cpu(cpu, mask) | |
321 | do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); | |
322 | } | |
323 | #endif | |
324 | ||
e0476371 MM |
325 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
326 | void smp_send_debugger_break(void) | |
1da177e4 | 327 | { |
e0476371 MM |
328 | int cpu; |
329 | int me = raw_smp_processor_id(); | |
330 | ||
331 | if (unlikely(!smp_ops)) | |
332 | return; | |
333 | ||
334 | for_each_online_cpu(cpu) | |
335 | if (cpu != me) | |
9ca980dc | 336 | do_message_pass(cpu, PPC_MSG_DEBUGGER_BREAK); |
1da177e4 LT |
337 | } |
338 | #endif | |
339 | ||
cc532915 ME |
340 | #ifdef CONFIG_KEXEC |
341 | void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) | |
342 | { | |
343 | crash_ipi_function_ptr = crash_ipi_callback; | |
e0476371 | 344 | if (crash_ipi_callback) { |
cc532915 | 345 | mb(); |
e0476371 | 346 | smp_send_debugger_break(); |
cc532915 ME |
347 | } |
348 | } | |
349 | #endif | |
350 | ||
1da177e4 LT |
351 | static void stop_this_cpu(void *dummy) |
352 | { | |
8389b37d VB |
353 | /* Remove this CPU */ |
354 | set_cpu_online(smp_processor_id(), false); | |
355 | ||
1da177e4 LT |
356 | local_irq_disable(); |
357 | while (1) | |
358 | ; | |
359 | } | |
360 | ||
8fd7675c SS |
361 | void smp_send_stop(void) |
362 | { | |
8691e5a8 | 363 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
364 | } |
365 | ||
1da177e4 LT |
366 | struct thread_info *current_set[NR_CPUS]; |
367 | ||
cad5cef6 | 368 | static void smp_store_cpu_info(int id) |
1da177e4 | 369 | { |
6b7487fc | 370 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); |
3160b097 BB |
371 | #ifdef CONFIG_PPC_FSL_BOOK3E |
372 | per_cpu(next_tlbcam_idx, id) | |
373 | = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; | |
374 | #endif | |
1da177e4 LT |
375 | } |
376 | ||
1da177e4 LT |
377 | void __init smp_prepare_cpus(unsigned int max_cpus) |
378 | { | |
379 | unsigned int cpu; | |
380 | ||
381 | DBG("smp_prepare_cpus\n"); | |
382 | ||
383 | /* | |
384 | * setup_cpu may need to be called on the boot cpu. We havent | |
385 | * spun any cpus up but lets be paranoid. | |
386 | */ | |
387 | BUG_ON(boot_cpuid != smp_processor_id()); | |
388 | ||
389 | /* Fixup boot cpu */ | |
390 | smp_store_cpu_info(boot_cpuid); | |
391 | cpu_callin_map[boot_cpuid] = 1; | |
392 | ||
cc1ba8ea AB |
393 | for_each_possible_cpu(cpu) { |
394 | zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), | |
395 | GFP_KERNEL, cpu_to_node(cpu)); | |
396 | zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), | |
397 | GFP_KERNEL, cpu_to_node(cpu)); | |
2fabf084 NA |
398 | /* |
399 | * numa_node_id() works after this. | |
400 | */ | |
bc3c4327 LZ |
401 | if (cpu_present(cpu)) { |
402 | set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]); | |
403 | set_cpu_numa_mem(cpu, | |
404 | local_memory_node(numa_cpu_lookup_table[cpu])); | |
405 | } | |
cc1ba8ea AB |
406 | } |
407 | ||
408 | cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); | |
409 | cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid)); | |
410 | ||
dfee0efe CG |
411 | if (smp_ops && smp_ops->probe) |
412 | smp_ops->probe(); | |
1da177e4 LT |
413 | } |
414 | ||
cad5cef6 | 415 | void smp_prepare_boot_cpu(void) |
1da177e4 LT |
416 | { |
417 | BUG_ON(smp_processor_id() != boot_cpuid); | |
5ad57078 | 418 | #ifdef CONFIG_PPC64 |
1da177e4 | 419 | paca[boot_cpuid].__current = current; |
5ad57078 | 420 | #endif |
8c272261 | 421 | set_numa_node(numa_cpu_lookup_table[boot_cpuid]); |
b5e2fc1c | 422 | current_set[boot_cpuid] = task_thread_info(current); |
1da177e4 LT |
423 | } |
424 | ||
425 | #ifdef CONFIG_HOTPLUG_CPU | |
1da177e4 LT |
426 | |
427 | int generic_cpu_disable(void) | |
428 | { | |
429 | unsigned int cpu = smp_processor_id(); | |
430 | ||
431 | if (cpu == boot_cpuid) | |
432 | return -EBUSY; | |
433 | ||
ea0f1cab | 434 | set_cpu_online(cpu, false); |
799d6046 | 435 | #ifdef CONFIG_PPC64 |
a7f290da | 436 | vdso_data->processorCount--; |
094fe2e7 | 437 | #endif |
1c91cc57 | 438 | migrate_irqs(); |
1da177e4 LT |
439 | return 0; |
440 | } | |
441 | ||
1da177e4 LT |
442 | void generic_cpu_die(unsigned int cpu) |
443 | { | |
444 | int i; | |
445 | ||
446 | for (i = 0; i < 100; i++) { | |
0d8d4d42 | 447 | smp_rmb(); |
2f4f1f81 | 448 | if (is_cpu_dead(cpu)) |
1da177e4 LT |
449 | return; |
450 | msleep(100); | |
451 | } | |
452 | printk(KERN_ERR "CPU%d didn't die...\n", cpu); | |
453 | } | |
454 | ||
105765f4 BH |
455 | void generic_set_cpu_dead(unsigned int cpu) |
456 | { | |
457 | per_cpu(cpu_state, cpu) = CPU_DEAD; | |
458 | } | |
fb82b839 | 459 | |
ae5cab47 ZC |
460 | /* |
461 | * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise | |
462 | * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), | |
463 | * which makes the delay in generic_cpu_die() not happen. | |
464 | */ | |
465 | void generic_set_cpu_up(unsigned int cpu) | |
466 | { | |
467 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
468 | } | |
469 | ||
fb82b839 BH |
470 | int generic_check_cpu_restart(unsigned int cpu) |
471 | { | |
472 | return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; | |
473 | } | |
512691d4 | 474 | |
2f4f1f81 | 475 | int is_cpu_dead(unsigned int cpu) |
476 | { | |
477 | return per_cpu(cpu_state, cpu) == CPU_DEAD; | |
478 | } | |
479 | ||
441c19c8 | 480 | static bool secondaries_inhibited(void) |
512691d4 | 481 | { |
441c19c8 | 482 | return kvm_hv_mode_active(); |
512691d4 PM |
483 | } |
484 | ||
485 | #else /* HOTPLUG_CPU */ | |
486 | ||
487 | #define secondaries_inhibited() 0 | |
488 | ||
1da177e4 LT |
489 | #endif |
490 | ||
17e32eac | 491 | static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) |
c56e5853 | 492 | { |
17e32eac | 493 | struct thread_info *ti = task_thread_info(idle); |
c56e5853 BH |
494 | |
495 | #ifdef CONFIG_PPC64 | |
17e32eac | 496 | paca[cpu].__current = idle; |
c56e5853 BH |
497 | paca[cpu].kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD; |
498 | #endif | |
499 | ti->cpu = cpu; | |
17e32eac | 500 | secondary_ti = current_set[cpu] = ti; |
c56e5853 BH |
501 | } |
502 | ||
061d19f2 | 503 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 504 | { |
c56e5853 | 505 | int rc, c; |
1da177e4 | 506 | |
512691d4 PM |
507 | /* |
508 | * Don't allow secondary threads to come online if inhibited | |
509 | */ | |
510 | if (threads_per_core > 1 && secondaries_inhibited() && | |
6f5e40a3 | 511 | cpu_thread_in_subcore(cpu)) |
512691d4 PM |
512 | return -EBUSY; |
513 | ||
8cffc6ac BH |
514 | if (smp_ops == NULL || |
515 | (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) | |
1da177e4 LT |
516 | return -EINVAL; |
517 | ||
17e32eac | 518 | cpu_idle_thread_init(cpu, tidle); |
c560bbce | 519 | |
1da177e4 LT |
520 | /* Make sure callin-map entry is 0 (can be leftover a CPU |
521 | * hotplug | |
522 | */ | |
523 | cpu_callin_map[cpu] = 0; | |
524 | ||
525 | /* The information for processor bringup must | |
526 | * be written out to main store before we release | |
527 | * the processor. | |
528 | */ | |
0d8d4d42 | 529 | smp_mb(); |
1da177e4 LT |
530 | |
531 | /* wake up cpus */ | |
532 | DBG("smp: kicking cpu %d\n", cpu); | |
de300974 ME |
533 | rc = smp_ops->kick_cpu(cpu); |
534 | if (rc) { | |
535 | pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); | |
536 | return rc; | |
537 | } | |
1da177e4 LT |
538 | |
539 | /* | |
540 | * wait to see if the cpu made a callin (is actually up). | |
541 | * use this value that I found through experimentation. | |
542 | * -- Cort | |
543 | */ | |
544 | if (system_state < SYSTEM_RUNNING) | |
ee0339f2 | 545 | for (c = 50000; c && !cpu_callin_map[cpu]; c--) |
1da177e4 LT |
546 | udelay(100); |
547 | #ifdef CONFIG_HOTPLUG_CPU | |
548 | else | |
549 | /* | |
550 | * CPUs can take much longer to come up in the | |
551 | * hotplug case. Wait five seconds. | |
552 | */ | |
67764263 GS |
553 | for (c = 5000; c && !cpu_callin_map[cpu]; c--) |
554 | msleep(1); | |
1da177e4 LT |
555 | #endif |
556 | ||
557 | if (!cpu_callin_map[cpu]) { | |
6685a477 | 558 | printk(KERN_ERR "Processor %u is stuck.\n", cpu); |
1da177e4 LT |
559 | return -ENOENT; |
560 | } | |
561 | ||
6685a477 | 562 | DBG("Processor %u found.\n", cpu); |
1da177e4 LT |
563 | |
564 | if (smp_ops->give_timebase) | |
565 | smp_ops->give_timebase(); | |
566 | ||
875ebe94 | 567 | /* Wait until cpu puts itself in the online & active maps */ |
e9d867a6 | 568 | while (!cpu_online(cpu)) |
1da177e4 LT |
569 | cpu_relax(); |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
e9efed3b NL |
574 | /* Return the value of the reg property corresponding to the given |
575 | * logical cpu. | |
576 | */ | |
577 | int cpu_to_core_id(int cpu) | |
578 | { | |
579 | struct device_node *np; | |
f8a1883a | 580 | const __be32 *reg; |
e9efed3b NL |
581 | int id = -1; |
582 | ||
583 | np = of_get_cpu_node(cpu, NULL); | |
584 | if (!np) | |
585 | goto out; | |
586 | ||
587 | reg = of_get_property(np, "reg", NULL); | |
588 | if (!reg) | |
589 | goto out; | |
590 | ||
f8a1883a | 591 | id = be32_to_cpup(reg); |
e9efed3b NL |
592 | out: |
593 | of_node_put(np); | |
594 | return id; | |
595 | } | |
596 | ||
99d86705 VS |
597 | /* Helper routines for cpu to core mapping */ |
598 | int cpu_core_index_of_thread(int cpu) | |
599 | { | |
600 | return cpu >> threads_shift; | |
601 | } | |
602 | EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); | |
603 | ||
604 | int cpu_first_thread_of_core(int core) | |
605 | { | |
606 | return core << threads_shift; | |
607 | } | |
608 | EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); | |
609 | ||
256f2d4b PM |
610 | static void traverse_siblings_chip_id(int cpu, bool add, int chipid) |
611 | { | |
612 | const struct cpumask *mask; | |
613 | struct device_node *np; | |
614 | int i, plen; | |
615 | const __be32 *prop; | |
616 | ||
617 | mask = add ? cpu_online_mask : cpu_present_mask; | |
618 | for_each_cpu(i, mask) { | |
619 | np = of_get_cpu_node(i, NULL); | |
620 | if (!np) | |
621 | continue; | |
622 | prop = of_get_property(np, "ibm,chip-id", &plen); | |
623 | if (prop && plen == sizeof(int) && | |
624 | of_read_number(prop, 1) == chipid) { | |
625 | if (add) { | |
626 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
627 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
628 | } else { | |
629 | cpumask_clear_cpu(cpu, cpu_core_mask(i)); | |
630 | cpumask_clear_cpu(i, cpu_core_mask(cpu)); | |
631 | } | |
632 | } | |
633 | of_node_put(np); | |
634 | } | |
635 | } | |
636 | ||
104699c0 | 637 | /* Must be called when no change can occur to cpu_present_mask, |
440a0857 NL |
638 | * i.e. during cpu online or offline. |
639 | */ | |
640 | static struct device_node *cpu_to_l2cache(int cpu) | |
641 | { | |
642 | struct device_node *np; | |
b2ea25b9 | 643 | struct device_node *cache; |
440a0857 NL |
644 | |
645 | if (!cpu_present(cpu)) | |
646 | return NULL; | |
647 | ||
648 | np = of_get_cpu_node(cpu, NULL); | |
649 | if (np == NULL) | |
650 | return NULL; | |
651 | ||
b2ea25b9 NL |
652 | cache = of_find_next_cache_node(np); |
653 | ||
440a0857 NL |
654 | of_node_put(np); |
655 | ||
b2ea25b9 | 656 | return cache; |
440a0857 | 657 | } |
1da177e4 | 658 | |
a8a5356c PM |
659 | static void traverse_core_siblings(int cpu, bool add) |
660 | { | |
256f2d4b | 661 | struct device_node *l2_cache, *np; |
a8a5356c | 662 | const struct cpumask *mask; |
256f2d4b PM |
663 | int i, chip, plen; |
664 | const __be32 *prop; | |
665 | ||
666 | /* First see if we have ibm,chip-id properties in cpu nodes */ | |
667 | np = of_get_cpu_node(cpu, NULL); | |
668 | if (np) { | |
669 | chip = -1; | |
670 | prop = of_get_property(np, "ibm,chip-id", &plen); | |
671 | if (prop && plen == sizeof(int)) | |
672 | chip = of_read_number(prop, 1); | |
673 | of_node_put(np); | |
674 | if (chip >= 0) { | |
675 | traverse_siblings_chip_id(cpu, add, chip); | |
676 | return; | |
677 | } | |
678 | } | |
a8a5356c PM |
679 | |
680 | l2_cache = cpu_to_l2cache(cpu); | |
681 | mask = add ? cpu_online_mask : cpu_present_mask; | |
682 | for_each_cpu(i, mask) { | |
256f2d4b | 683 | np = cpu_to_l2cache(i); |
a8a5356c PM |
684 | if (!np) |
685 | continue; | |
686 | if (np == l2_cache) { | |
687 | if (add) { | |
688 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
689 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
690 | } else { | |
691 | cpumask_clear_cpu(cpu, cpu_core_mask(i)); | |
692 | cpumask_clear_cpu(i, cpu_core_mask(cpu)); | |
693 | } | |
694 | } | |
695 | of_node_put(np); | |
696 | } | |
697 | of_node_put(l2_cache); | |
698 | } | |
699 | ||
1da177e4 | 700 | /* Activate a secondary processor. */ |
061d19f2 | 701 | void start_secondary(void *unused) |
1da177e4 LT |
702 | { |
703 | unsigned int cpu = smp_processor_id(); | |
e2075f79 | 704 | int i, base; |
1da177e4 LT |
705 | |
706 | atomic_inc(&init_mm.mm_count); | |
707 | current->active_mm = &init_mm; | |
708 | ||
709 | smp_store_cpu_info(cpu); | |
5ad57078 | 710 | set_dec(tb_ticks_per_jiffy); |
e4d76e1c | 711 | preempt_disable(); |
1be6f10f | 712 | cpu_callin_map[cpu] = 1; |
1da177e4 | 713 | |
757cbd46 KG |
714 | if (smp_ops->setup_cpu) |
715 | smp_ops->setup_cpu(cpu); | |
1da177e4 LT |
716 | if (smp_ops->take_timebase) |
717 | smp_ops->take_timebase(); | |
718 | ||
d831d0b8 TB |
719 | secondary_cpu_time_init(); |
720 | ||
aeeafbfa BH |
721 | #ifdef CONFIG_PPC64 |
722 | if (system_state == SYSTEM_RUNNING) | |
723 | vdso_data->processorCount++; | |
18ad51dd AB |
724 | |
725 | vdso_getcpu_init(); | |
aeeafbfa | 726 | #endif |
e2075f79 | 727 | /* Update sibling maps */ |
99d86705 | 728 | base = cpu_first_thread_sibling(cpu); |
e2075f79 | 729 | for (i = 0; i < threads_per_core; i++) { |
cce606fe | 730 | if (cpu_is_offline(base + i) && (cpu != base + i)) |
e2075f79 | 731 | continue; |
cc1ba8ea AB |
732 | cpumask_set_cpu(cpu, cpu_sibling_mask(base + i)); |
733 | cpumask_set_cpu(base + i, cpu_sibling_mask(cpu)); | |
440a0857 NL |
734 | |
735 | /* cpu_core_map should be a superset of | |
736 | * cpu_sibling_map even if we don't have cache | |
737 | * information, so update the former here, too. | |
738 | */ | |
cc1ba8ea AB |
739 | cpumask_set_cpu(cpu, cpu_core_mask(base + i)); |
740 | cpumask_set_cpu(base + i, cpu_core_mask(cpu)); | |
e2075f79 | 741 | } |
a8a5356c | 742 | traverse_core_siblings(cpu, true); |
1da177e4 | 743 | |
bc3c4327 LZ |
744 | set_numa_node(numa_cpu_lookup_table[cpu]); |
745 | set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); | |
746 | ||
cce606fe LZ |
747 | smp_wmb(); |
748 | notify_cpu_starting(cpu); | |
749 | set_cpu_online(cpu, true); | |
750 | ||
1da177e4 LT |
751 | local_irq_enable(); |
752 | ||
fc6d73d6 | 753 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
fa3f82c8 BH |
754 | |
755 | BUG(); | |
1da177e4 LT |
756 | } |
757 | ||
758 | int setup_profiling_timer(unsigned int multiplier) | |
759 | { | |
760 | return 0; | |
761 | } | |
762 | ||
607b45e9 VG |
763 | #ifdef CONFIG_SCHED_SMT |
764 | /* cpumask of CPUs with asymetric SMT dependancy */ | |
b6220ad6 | 765 | static int powerpc_smt_flags(void) |
607b45e9 | 766 | { |
5d4dfddd | 767 | int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; |
607b45e9 VG |
768 | |
769 | if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { | |
770 | printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); | |
771 | flags |= SD_ASYM_PACKING; | |
772 | } | |
773 | return flags; | |
774 | } | |
775 | #endif | |
776 | ||
777 | static struct sched_domain_topology_level powerpc_topology[] = { | |
778 | #ifdef CONFIG_SCHED_SMT | |
779 | { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, | |
780 | #endif | |
781 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
782 | { NULL, }, | |
783 | }; | |
784 | ||
1da177e4 LT |
785 | void __init smp_cpus_done(unsigned int max_cpus) |
786 | { | |
bfb9126d | 787 | cpumask_var_t old_mask; |
1da177e4 LT |
788 | |
789 | /* We want the setup_cpu() here to be called from CPU 0, but our | |
790 | * init thread may have been "borrowed" by another CPU in the meantime | |
791 | * se we pin us down to CPU 0 for a short while | |
792 | */ | |
bfb9126d | 793 | alloc_cpumask_var(&old_mask, GFP_NOWAIT); |
104699c0 | 794 | cpumask_copy(old_mask, tsk_cpus_allowed(current)); |
21dbeb91 | 795 | set_cpus_allowed_ptr(current, cpumask_of(boot_cpuid)); |
1da177e4 | 796 | |
757cbd46 | 797 | if (smp_ops && smp_ops->setup_cpu) |
8cffc6ac | 798 | smp_ops->setup_cpu(boot_cpuid); |
1da177e4 | 799 | |
bfb9126d AB |
800 | set_cpus_allowed_ptr(current, old_mask); |
801 | ||
802 | free_cpumask_var(old_mask); | |
4b703a23 | 803 | |
d7294445 BH |
804 | if (smp_ops && smp_ops->bringup_done) |
805 | smp_ops->bringup_done(); | |
806 | ||
4b703a23 | 807 | dump_numa_cpu_topology(); |
d7294445 | 808 | |
607b45e9 | 809 | set_sched_topology(powerpc_topology); |
1da177e4 | 810 | |
e1f0ece1 MN |
811 | } |
812 | ||
1da177e4 LT |
813 | #ifdef CONFIG_HOTPLUG_CPU |
814 | int __cpu_disable(void) | |
815 | { | |
e2075f79 NL |
816 | int cpu = smp_processor_id(); |
817 | int base, i; | |
818 | int err; | |
1da177e4 | 819 | |
e2075f79 NL |
820 | if (!smp_ops->cpu_disable) |
821 | return -ENOSYS; | |
822 | ||
823 | err = smp_ops->cpu_disable(); | |
824 | if (err) | |
825 | return err; | |
826 | ||
827 | /* Update sibling maps */ | |
99d86705 | 828 | base = cpu_first_thread_sibling(cpu); |
e2075f79 | 829 | for (i = 0; i < threads_per_core; i++) { |
cc1ba8ea AB |
830 | cpumask_clear_cpu(cpu, cpu_sibling_mask(base + i)); |
831 | cpumask_clear_cpu(base + i, cpu_sibling_mask(cpu)); | |
832 | cpumask_clear_cpu(cpu, cpu_core_mask(base + i)); | |
833 | cpumask_clear_cpu(base + i, cpu_core_mask(cpu)); | |
440a0857 | 834 | } |
a8a5356c | 835 | traverse_core_siblings(cpu, false); |
e2075f79 NL |
836 | |
837 | return 0; | |
1da177e4 LT |
838 | } |
839 | ||
840 | void __cpu_die(unsigned int cpu) | |
841 | { | |
842 | if (smp_ops->cpu_die) | |
843 | smp_ops->cpu_die(cpu); | |
844 | } | |
d0174c72 | 845 | |
abb17f9c MM |
846 | void cpu_die(void) |
847 | { | |
848 | if (ppc_md.cpu_die) | |
849 | ppc_md.cpu_die(); | |
fa3f82c8 BH |
850 | |
851 | /* If we return, we re-enter start_secondary */ | |
852 | start_secondary_resume(); | |
abb17f9c | 853 | } |
fa3f82c8 | 854 | |
1da177e4 | 855 | #endif |