Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * SMP support for ppc. | |
3 | * | |
4 | * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great | |
5 | * deal of code from the sparc and intel versions. | |
6 | * | |
7 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
8 | * | |
9 | * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and | |
10 | * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
16 | */ | |
17 | ||
18 | #undef DEBUG | |
19 | ||
1da177e4 | 20 | #include <linux/kernel.h> |
4b16f8e2 | 21 | #include <linux/export.h> |
1da177e4 LT |
22 | #include <linux/sched.h> |
23 | #include <linux/smp.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/cache.h> | |
29 | #include <linux/err.h> | |
8a25a2fd | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include <linux/cpu.h> |
32 | #include <linux/notifier.h> | |
4b703a23 | 33 | #include <linux/topology.h> |
1da177e4 LT |
34 | |
35 | #include <asm/ptrace.h> | |
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <asm/irq.h> |
1b67bee1 | 38 | #include <asm/hw_irq.h> |
441c19c8 | 39 | #include <asm/kvm_ppc.h> |
1da177e4 LT |
40 | #include <asm/page.h> |
41 | #include <asm/pgtable.h> | |
42 | #include <asm/prom.h> | |
43 | #include <asm/smp.h> | |
1da177e4 LT |
44 | #include <asm/time.h> |
45 | #include <asm/machdep.h> | |
e2075f79 | 46 | #include <asm/cputhreads.h> |
1da177e4 | 47 | #include <asm/cputable.h> |
bbeb3f4c | 48 | #include <asm/mpic.h> |
a7f290da | 49 | #include <asm/vdso_datapage.h> |
5ad57078 PM |
50 | #ifdef CONFIG_PPC64 |
51 | #include <asm/paca.h> | |
52 | #endif | |
18ad51dd | 53 | #include <asm/vdso.h> |
ae3a197e | 54 | #include <asm/debug.h> |
1217d34b | 55 | #include <asm/kexec.h> |
5ad57078 | 56 | |
1da177e4 | 57 | #ifdef DEBUG |
f9e4ec57 | 58 | #include <asm/udbg.h> |
1da177e4 LT |
59 | #define DBG(fmt...) udbg_printf(fmt) |
60 | #else | |
61 | #define DBG(fmt...) | |
62 | #endif | |
63 | ||
c56e5853 | 64 | #ifdef CONFIG_HOTPLUG_CPU |
fb82b839 BH |
65 | /* State of each CPU during hotplug phases */ |
66 | static DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
c56e5853 BH |
67 | #endif |
68 | ||
f9e4ec57 ME |
69 | struct thread_info *secondary_ti; |
70 | ||
cc1ba8ea AB |
71 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
72 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); | |
1da177e4 | 73 | |
d5a7430d | 74 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
440a0857 | 75 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
1da177e4 | 76 | |
5ad57078 | 77 | /* SMP operations for this machine */ |
1da177e4 LT |
78 | struct smp_ops_t *smp_ops; |
79 | ||
7ccbe504 BH |
80 | /* Can't be static due to PowerMac hackery */ |
81 | volatile unsigned int cpu_callin_map[NR_CPUS]; | |
1da177e4 | 82 | |
1da177e4 LT |
83 | int smt_enabled_at_boot = 1; |
84 | ||
cc532915 ME |
85 | static void (*crash_ipi_function_ptr)(struct pt_regs *) = NULL; |
86 | ||
3cd85250 AF |
87 | /* |
88 | * Returns 1 if the specified cpu should be brought up during boot. | |
89 | * Used to inhibit booting threads if they've been disabled or | |
90 | * limited on the command line | |
91 | */ | |
92 | int smp_generic_cpu_bootable(unsigned int nr) | |
93 | { | |
94 | /* Special case - we inhibit secondary thread startup | |
95 | * during boot if the user requests it. | |
96 | */ | |
97 | if (system_state == SYSTEM_BOOTING && cpu_has_feature(CPU_FTR_SMT)) { | |
98 | if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) | |
99 | return 0; | |
100 | if (smt_enabled_at_boot | |
101 | && cpu_thread_in_core(nr) >= smt_enabled_at_boot) | |
102 | return 0; | |
103 | } | |
104 | ||
105 | return 1; | |
106 | } | |
107 | ||
108 | ||
5ad57078 | 109 | #ifdef CONFIG_PPC64 |
cad5cef6 | 110 | int smp_generic_kick_cpu(int nr) |
1da177e4 LT |
111 | { |
112 | BUG_ON(nr < 0 || nr >= NR_CPUS); | |
113 | ||
114 | /* | |
115 | * The processor is currently spinning, waiting for the | |
116 | * cpu_start field to become non-zero After we set cpu_start, | |
117 | * the processor will continue on to secondary_start | |
118 | */ | |
fb82b839 BH |
119 | if (!paca[nr].cpu_start) { |
120 | paca[nr].cpu_start = 1; | |
121 | smp_mb(); | |
122 | return 0; | |
123 | } | |
124 | ||
125 | #ifdef CONFIG_HOTPLUG_CPU | |
126 | /* | |
127 | * Ok it's not there, so it might be soft-unplugged, let's | |
128 | * try to bring it back | |
129 | */ | |
ae5cab47 | 130 | generic_set_cpu_up(nr); |
fb82b839 BH |
131 | smp_wmb(); |
132 | smp_send_reschedule(nr); | |
133 | #endif /* CONFIG_HOTPLUG_CPU */ | |
de300974 ME |
134 | |
135 | return 0; | |
1da177e4 | 136 | } |
fb82b839 | 137 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 138 | |
25ddd738 MM |
139 | static irqreturn_t call_function_action(int irq, void *data) |
140 | { | |
141 | generic_smp_call_function_interrupt(); | |
142 | return IRQ_HANDLED; | |
143 | } | |
144 | ||
145 | static irqreturn_t reschedule_action(int irq, void *data) | |
146 | { | |
184748cc | 147 | scheduler_ipi(); |
25ddd738 MM |
148 | return IRQ_HANDLED; |
149 | } | |
150 | ||
1b67bee1 | 151 | static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) |
25ddd738 | 152 | { |
1b67bee1 | 153 | tick_broadcast_ipi_handler(); |
25ddd738 MM |
154 | return IRQ_HANDLED; |
155 | } | |
156 | ||
7ef71d75 | 157 | static irqreturn_t debug_ipi_action(int irq, void *data) |
25ddd738 | 158 | { |
23d72bfd MM |
159 | if (crash_ipi_function_ptr) { |
160 | crash_ipi_function_ptr(get_irq_regs()); | |
161 | return IRQ_HANDLED; | |
162 | } | |
163 | ||
164 | #ifdef CONFIG_DEBUGGER | |
165 | debugger_ipi(get_irq_regs()); | |
166 | #endif /* CONFIG_DEBUGGER */ | |
167 | ||
25ddd738 MM |
168 | return IRQ_HANDLED; |
169 | } | |
170 | ||
171 | static irq_handler_t smp_ipi_action[] = { | |
172 | [PPC_MSG_CALL_FUNCTION] = call_function_action, | |
173 | [PPC_MSG_RESCHEDULE] = reschedule_action, | |
1b67bee1 | 174 | [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, |
25ddd738 MM |
175 | [PPC_MSG_DEBUGGER_BREAK] = debug_ipi_action, |
176 | }; | |
177 | ||
178 | const char *smp_ipi_name[] = { | |
179 | [PPC_MSG_CALL_FUNCTION] = "ipi call function", | |
180 | [PPC_MSG_RESCHEDULE] = "ipi reschedule", | |
1b67bee1 | 181 | [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", |
25ddd738 MM |
182 | [PPC_MSG_DEBUGGER_BREAK] = "ipi debugger", |
183 | }; | |
184 | ||
185 | /* optional function to request ipi, for controllers with >= 4 ipis */ | |
186 | int smp_request_message_ipi(int virq, int msg) | |
187 | { | |
188 | int err; | |
189 | ||
190 | if (msg < 0 || msg > PPC_MSG_DEBUGGER_BREAK) { | |
191 | return -EINVAL; | |
192 | } | |
193 | #if !defined(CONFIG_DEBUGGER) && !defined(CONFIG_KEXEC) | |
194 | if (msg == PPC_MSG_DEBUGGER_BREAK) { | |
195 | return 1; | |
196 | } | |
197 | #endif | |
3b5e16d7 | 198 | err = request_irq(virq, smp_ipi_action[msg], |
e6651de9 | 199 | IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, |
b0d436c7 | 200 | smp_ipi_name[msg], NULL); |
25ddd738 MM |
201 | WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", |
202 | virq, smp_ipi_name[msg], err); | |
203 | ||
204 | return err; | |
205 | } | |
206 | ||
1ece355b | 207 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
23d72bfd | 208 | struct cpu_messages { |
bd7f561f | 209 | long messages; /* current messages */ |
23d72bfd MM |
210 | unsigned long data; /* data for cause ipi */ |
211 | }; | |
212 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); | |
213 | ||
214 | void smp_muxed_ipi_set_data(int cpu, unsigned long data) | |
215 | { | |
216 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
217 | ||
218 | info->data = data; | |
219 | } | |
220 | ||
31639c77 | 221 | void smp_muxed_ipi_set_message(int cpu, int msg) |
23d72bfd MM |
222 | { |
223 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
71454272 | 224 | char *message = (char *)&info->messages; |
23d72bfd | 225 | |
9fb1b36c PM |
226 | /* |
227 | * Order previous accesses before accesses in the IPI handler. | |
228 | */ | |
229 | smp_mb(); | |
71454272 | 230 | message[msg] = 1; |
31639c77 SW |
231 | } |
232 | ||
233 | void smp_muxed_ipi_message_pass(int cpu, int msg) | |
234 | { | |
235 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
236 | ||
237 | smp_muxed_ipi_set_message(cpu, msg); | |
9fb1b36c PM |
238 | /* |
239 | * cause_ipi functions are required to include a full barrier | |
240 | * before doing whatever causes the IPI. | |
241 | */ | |
23d72bfd MM |
242 | smp_ops->cause_ipi(cpu, info->data); |
243 | } | |
244 | ||
0654de1c | 245 | #ifdef __BIG_ENDIAN__ |
bd7f561f | 246 | #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A))) |
0654de1c | 247 | #else |
bd7f561f | 248 | #define IPI_MESSAGE(A) (1uL << (8 * (A))) |
0654de1c AB |
249 | #endif |
250 | ||
23d72bfd MM |
251 | irqreturn_t smp_ipi_demux(void) |
252 | { | |
69111bac | 253 | struct cpu_messages *info = this_cpu_ptr(&ipi_message); |
bd7f561f | 254 | unsigned long all; |
23d72bfd MM |
255 | |
256 | mb(); /* order any irq clear */ | |
71454272 MM |
257 | |
258 | do { | |
9fb1b36c | 259 | all = xchg(&info->messages, 0); |
0654de1c | 260 | if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) |
23d72bfd | 261 | generic_smp_call_function_interrupt(); |
0654de1c | 262 | if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) |
880102e7 | 263 | scheduler_ipi(); |
1b67bee1 SB |
264 | if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) |
265 | tick_broadcast_ipi_handler(); | |
0654de1c | 266 | if (all & IPI_MESSAGE(PPC_MSG_DEBUGGER_BREAK)) |
23d72bfd | 267 | debug_ipi_action(0, NULL); |
71454272 MM |
268 | } while (info->messages); |
269 | ||
23d72bfd MM |
270 | return IRQ_HANDLED; |
271 | } | |
1ece355b | 272 | #endif /* CONFIG_PPC_SMP_MUXED_IPI */ |
23d72bfd | 273 | |
9ca980dc PM |
274 | static inline void do_message_pass(int cpu, int msg) |
275 | { | |
276 | if (smp_ops->message_pass) | |
277 | smp_ops->message_pass(cpu, msg); | |
278 | #ifdef CONFIG_PPC_SMP_MUXED_IPI | |
279 | else | |
280 | smp_muxed_ipi_message_pass(cpu, msg); | |
281 | #endif | |
282 | } | |
283 | ||
1da177e4 LT |
284 | void smp_send_reschedule(int cpu) |
285 | { | |
8cffc6ac | 286 | if (likely(smp_ops)) |
9ca980dc | 287 | do_message_pass(cpu, PPC_MSG_RESCHEDULE); |
1da177e4 | 288 | } |
de56a948 | 289 | EXPORT_SYMBOL_GPL(smp_send_reschedule); |
1da177e4 | 290 | |
b7d7a240 JA |
291 | void arch_send_call_function_single_ipi(int cpu) |
292 | { | |
402d9a1e | 293 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
294 | } |
295 | ||
f063ea02 | 296 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
b7d7a240 JA |
297 | { |
298 | unsigned int cpu; | |
299 | ||
f063ea02 | 300 | for_each_cpu(cpu, mask) |
9ca980dc | 301 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
302 | } |
303 | ||
1b67bee1 SB |
304 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
305 | void tick_broadcast(const struct cpumask *mask) | |
306 | { | |
307 | unsigned int cpu; | |
308 | ||
309 | for_each_cpu(cpu, mask) | |
310 | do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); | |
311 | } | |
312 | #endif | |
313 | ||
e0476371 MM |
314 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
315 | void smp_send_debugger_break(void) | |
1da177e4 | 316 | { |
e0476371 MM |
317 | int cpu; |
318 | int me = raw_smp_processor_id(); | |
319 | ||
320 | if (unlikely(!smp_ops)) | |
321 | return; | |
322 | ||
323 | for_each_online_cpu(cpu) | |
324 | if (cpu != me) | |
9ca980dc | 325 | do_message_pass(cpu, PPC_MSG_DEBUGGER_BREAK); |
1da177e4 LT |
326 | } |
327 | #endif | |
328 | ||
cc532915 ME |
329 | #ifdef CONFIG_KEXEC |
330 | void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) | |
331 | { | |
332 | crash_ipi_function_ptr = crash_ipi_callback; | |
e0476371 | 333 | if (crash_ipi_callback) { |
cc532915 | 334 | mb(); |
e0476371 | 335 | smp_send_debugger_break(); |
cc532915 ME |
336 | } |
337 | } | |
338 | #endif | |
339 | ||
1da177e4 LT |
340 | static void stop_this_cpu(void *dummy) |
341 | { | |
8389b37d VB |
342 | /* Remove this CPU */ |
343 | set_cpu_online(smp_processor_id(), false); | |
344 | ||
1da177e4 LT |
345 | local_irq_disable(); |
346 | while (1) | |
347 | ; | |
348 | } | |
349 | ||
8fd7675c SS |
350 | void smp_send_stop(void) |
351 | { | |
8691e5a8 | 352 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
353 | } |
354 | ||
1da177e4 LT |
355 | struct thread_info *current_set[NR_CPUS]; |
356 | ||
cad5cef6 | 357 | static void smp_store_cpu_info(int id) |
1da177e4 | 358 | { |
6b7487fc | 359 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); |
3160b097 BB |
360 | #ifdef CONFIG_PPC_FSL_BOOK3E |
361 | per_cpu(next_tlbcam_idx, id) | |
362 | = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; | |
363 | #endif | |
1da177e4 LT |
364 | } |
365 | ||
1da177e4 LT |
366 | void __init smp_prepare_cpus(unsigned int max_cpus) |
367 | { | |
368 | unsigned int cpu; | |
369 | ||
370 | DBG("smp_prepare_cpus\n"); | |
371 | ||
372 | /* | |
373 | * setup_cpu may need to be called on the boot cpu. We havent | |
374 | * spun any cpus up but lets be paranoid. | |
375 | */ | |
376 | BUG_ON(boot_cpuid != smp_processor_id()); | |
377 | ||
378 | /* Fixup boot cpu */ | |
379 | smp_store_cpu_info(boot_cpuid); | |
380 | cpu_callin_map[boot_cpuid] = 1; | |
381 | ||
cc1ba8ea AB |
382 | for_each_possible_cpu(cpu) { |
383 | zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), | |
384 | GFP_KERNEL, cpu_to_node(cpu)); | |
385 | zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), | |
386 | GFP_KERNEL, cpu_to_node(cpu)); | |
2fabf084 NA |
387 | /* |
388 | * numa_node_id() works after this. | |
389 | */ | |
bc3c4327 LZ |
390 | if (cpu_present(cpu)) { |
391 | set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]); | |
392 | set_cpu_numa_mem(cpu, | |
393 | local_memory_node(numa_cpu_lookup_table[cpu])); | |
394 | } | |
cc1ba8ea AB |
395 | } |
396 | ||
397 | cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); | |
398 | cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid)); | |
399 | ||
dfee0efe CG |
400 | if (smp_ops && smp_ops->probe) |
401 | smp_ops->probe(); | |
1da177e4 LT |
402 | } |
403 | ||
cad5cef6 | 404 | void smp_prepare_boot_cpu(void) |
1da177e4 LT |
405 | { |
406 | BUG_ON(smp_processor_id() != boot_cpuid); | |
5ad57078 | 407 | #ifdef CONFIG_PPC64 |
1da177e4 | 408 | paca[boot_cpuid].__current = current; |
5ad57078 | 409 | #endif |
8c272261 | 410 | set_numa_node(numa_cpu_lookup_table[boot_cpuid]); |
b5e2fc1c | 411 | current_set[boot_cpuid] = task_thread_info(current); |
1da177e4 LT |
412 | } |
413 | ||
414 | #ifdef CONFIG_HOTPLUG_CPU | |
1da177e4 LT |
415 | |
416 | int generic_cpu_disable(void) | |
417 | { | |
418 | unsigned int cpu = smp_processor_id(); | |
419 | ||
420 | if (cpu == boot_cpuid) | |
421 | return -EBUSY; | |
422 | ||
ea0f1cab | 423 | set_cpu_online(cpu, false); |
799d6046 | 424 | #ifdef CONFIG_PPC64 |
a7f290da | 425 | vdso_data->processorCount--; |
094fe2e7 | 426 | #endif |
1c91cc57 | 427 | migrate_irqs(); |
1da177e4 LT |
428 | return 0; |
429 | } | |
430 | ||
1da177e4 LT |
431 | void generic_cpu_die(unsigned int cpu) |
432 | { | |
433 | int i; | |
434 | ||
435 | for (i = 0; i < 100; i++) { | |
0d8d4d42 | 436 | smp_rmb(); |
1da177e4 LT |
437 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) |
438 | return; | |
439 | msleep(100); | |
440 | } | |
441 | printk(KERN_ERR "CPU%d didn't die...\n", cpu); | |
442 | } | |
443 | ||
105765f4 BH |
444 | void generic_set_cpu_dead(unsigned int cpu) |
445 | { | |
446 | per_cpu(cpu_state, cpu) = CPU_DEAD; | |
447 | } | |
fb82b839 | 448 | |
ae5cab47 ZC |
449 | /* |
450 | * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise | |
451 | * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), | |
452 | * which makes the delay in generic_cpu_die() not happen. | |
453 | */ | |
454 | void generic_set_cpu_up(unsigned int cpu) | |
455 | { | |
456 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
457 | } | |
458 | ||
fb82b839 BH |
459 | int generic_check_cpu_restart(unsigned int cpu) |
460 | { | |
461 | return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; | |
462 | } | |
512691d4 | 463 | |
441c19c8 | 464 | static bool secondaries_inhibited(void) |
512691d4 | 465 | { |
441c19c8 | 466 | return kvm_hv_mode_active(); |
512691d4 PM |
467 | } |
468 | ||
469 | #else /* HOTPLUG_CPU */ | |
470 | ||
471 | #define secondaries_inhibited() 0 | |
472 | ||
1da177e4 LT |
473 | #endif |
474 | ||
17e32eac | 475 | static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) |
c56e5853 | 476 | { |
17e32eac | 477 | struct thread_info *ti = task_thread_info(idle); |
c56e5853 BH |
478 | |
479 | #ifdef CONFIG_PPC64 | |
17e32eac | 480 | paca[cpu].__current = idle; |
c56e5853 BH |
481 | paca[cpu].kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD; |
482 | #endif | |
483 | ti->cpu = cpu; | |
17e32eac | 484 | secondary_ti = current_set[cpu] = ti; |
c56e5853 BH |
485 | } |
486 | ||
061d19f2 | 487 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 488 | { |
c56e5853 | 489 | int rc, c; |
1da177e4 | 490 | |
512691d4 PM |
491 | /* |
492 | * Don't allow secondary threads to come online if inhibited | |
493 | */ | |
494 | if (threads_per_core > 1 && secondaries_inhibited() && | |
6f5e40a3 | 495 | cpu_thread_in_subcore(cpu)) |
512691d4 PM |
496 | return -EBUSY; |
497 | ||
8cffc6ac BH |
498 | if (smp_ops == NULL || |
499 | (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) | |
1da177e4 LT |
500 | return -EINVAL; |
501 | ||
17e32eac | 502 | cpu_idle_thread_init(cpu, tidle); |
c560bbce | 503 | |
1da177e4 LT |
504 | /* Make sure callin-map entry is 0 (can be leftover a CPU |
505 | * hotplug | |
506 | */ | |
507 | cpu_callin_map[cpu] = 0; | |
508 | ||
509 | /* The information for processor bringup must | |
510 | * be written out to main store before we release | |
511 | * the processor. | |
512 | */ | |
0d8d4d42 | 513 | smp_mb(); |
1da177e4 LT |
514 | |
515 | /* wake up cpus */ | |
516 | DBG("smp: kicking cpu %d\n", cpu); | |
de300974 ME |
517 | rc = smp_ops->kick_cpu(cpu); |
518 | if (rc) { | |
519 | pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); | |
520 | return rc; | |
521 | } | |
1da177e4 LT |
522 | |
523 | /* | |
524 | * wait to see if the cpu made a callin (is actually up). | |
525 | * use this value that I found through experimentation. | |
526 | * -- Cort | |
527 | */ | |
528 | if (system_state < SYSTEM_RUNNING) | |
ee0339f2 | 529 | for (c = 50000; c && !cpu_callin_map[cpu]; c--) |
1da177e4 LT |
530 | udelay(100); |
531 | #ifdef CONFIG_HOTPLUG_CPU | |
532 | else | |
533 | /* | |
534 | * CPUs can take much longer to come up in the | |
535 | * hotplug case. Wait five seconds. | |
536 | */ | |
67764263 GS |
537 | for (c = 5000; c && !cpu_callin_map[cpu]; c--) |
538 | msleep(1); | |
1da177e4 LT |
539 | #endif |
540 | ||
541 | if (!cpu_callin_map[cpu]) { | |
6685a477 | 542 | printk(KERN_ERR "Processor %u is stuck.\n", cpu); |
1da177e4 LT |
543 | return -ENOENT; |
544 | } | |
545 | ||
6685a477 | 546 | DBG("Processor %u found.\n", cpu); |
1da177e4 LT |
547 | |
548 | if (smp_ops->give_timebase) | |
549 | smp_ops->give_timebase(); | |
550 | ||
875ebe94 ME |
551 | /* Wait until cpu puts itself in the online & active maps */ |
552 | while (!cpu_online(cpu) || !cpu_active(cpu)) | |
1da177e4 LT |
553 | cpu_relax(); |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
e9efed3b NL |
558 | /* Return the value of the reg property corresponding to the given |
559 | * logical cpu. | |
560 | */ | |
561 | int cpu_to_core_id(int cpu) | |
562 | { | |
563 | struct device_node *np; | |
f8a1883a | 564 | const __be32 *reg; |
e9efed3b NL |
565 | int id = -1; |
566 | ||
567 | np = of_get_cpu_node(cpu, NULL); | |
568 | if (!np) | |
569 | goto out; | |
570 | ||
571 | reg = of_get_property(np, "reg", NULL); | |
572 | if (!reg) | |
573 | goto out; | |
574 | ||
f8a1883a | 575 | id = be32_to_cpup(reg); |
e9efed3b NL |
576 | out: |
577 | of_node_put(np); | |
578 | return id; | |
579 | } | |
580 | ||
99d86705 VS |
581 | /* Helper routines for cpu to core mapping */ |
582 | int cpu_core_index_of_thread(int cpu) | |
583 | { | |
584 | return cpu >> threads_shift; | |
585 | } | |
586 | EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); | |
587 | ||
588 | int cpu_first_thread_of_core(int core) | |
589 | { | |
590 | return core << threads_shift; | |
591 | } | |
592 | EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); | |
593 | ||
256f2d4b PM |
594 | static void traverse_siblings_chip_id(int cpu, bool add, int chipid) |
595 | { | |
596 | const struct cpumask *mask; | |
597 | struct device_node *np; | |
598 | int i, plen; | |
599 | const __be32 *prop; | |
600 | ||
601 | mask = add ? cpu_online_mask : cpu_present_mask; | |
602 | for_each_cpu(i, mask) { | |
603 | np = of_get_cpu_node(i, NULL); | |
604 | if (!np) | |
605 | continue; | |
606 | prop = of_get_property(np, "ibm,chip-id", &plen); | |
607 | if (prop && plen == sizeof(int) && | |
608 | of_read_number(prop, 1) == chipid) { | |
609 | if (add) { | |
610 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
611 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
612 | } else { | |
613 | cpumask_clear_cpu(cpu, cpu_core_mask(i)); | |
614 | cpumask_clear_cpu(i, cpu_core_mask(cpu)); | |
615 | } | |
616 | } | |
617 | of_node_put(np); | |
618 | } | |
619 | } | |
620 | ||
104699c0 | 621 | /* Must be called when no change can occur to cpu_present_mask, |
440a0857 NL |
622 | * i.e. during cpu online or offline. |
623 | */ | |
624 | static struct device_node *cpu_to_l2cache(int cpu) | |
625 | { | |
626 | struct device_node *np; | |
b2ea25b9 | 627 | struct device_node *cache; |
440a0857 NL |
628 | |
629 | if (!cpu_present(cpu)) | |
630 | return NULL; | |
631 | ||
632 | np = of_get_cpu_node(cpu, NULL); | |
633 | if (np == NULL) | |
634 | return NULL; | |
635 | ||
b2ea25b9 NL |
636 | cache = of_find_next_cache_node(np); |
637 | ||
440a0857 NL |
638 | of_node_put(np); |
639 | ||
b2ea25b9 | 640 | return cache; |
440a0857 | 641 | } |
1da177e4 | 642 | |
a8a5356c PM |
643 | static void traverse_core_siblings(int cpu, bool add) |
644 | { | |
256f2d4b | 645 | struct device_node *l2_cache, *np; |
a8a5356c | 646 | const struct cpumask *mask; |
256f2d4b PM |
647 | int i, chip, plen; |
648 | const __be32 *prop; | |
649 | ||
650 | /* First see if we have ibm,chip-id properties in cpu nodes */ | |
651 | np = of_get_cpu_node(cpu, NULL); | |
652 | if (np) { | |
653 | chip = -1; | |
654 | prop = of_get_property(np, "ibm,chip-id", &plen); | |
655 | if (prop && plen == sizeof(int)) | |
656 | chip = of_read_number(prop, 1); | |
657 | of_node_put(np); | |
658 | if (chip >= 0) { | |
659 | traverse_siblings_chip_id(cpu, add, chip); | |
660 | return; | |
661 | } | |
662 | } | |
a8a5356c PM |
663 | |
664 | l2_cache = cpu_to_l2cache(cpu); | |
665 | mask = add ? cpu_online_mask : cpu_present_mask; | |
666 | for_each_cpu(i, mask) { | |
256f2d4b | 667 | np = cpu_to_l2cache(i); |
a8a5356c PM |
668 | if (!np) |
669 | continue; | |
670 | if (np == l2_cache) { | |
671 | if (add) { | |
672 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
673 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
674 | } else { | |
675 | cpumask_clear_cpu(cpu, cpu_core_mask(i)); | |
676 | cpumask_clear_cpu(i, cpu_core_mask(cpu)); | |
677 | } | |
678 | } | |
679 | of_node_put(np); | |
680 | } | |
681 | of_node_put(l2_cache); | |
682 | } | |
683 | ||
1da177e4 | 684 | /* Activate a secondary processor. */ |
061d19f2 | 685 | void start_secondary(void *unused) |
1da177e4 LT |
686 | { |
687 | unsigned int cpu = smp_processor_id(); | |
e2075f79 | 688 | int i, base; |
1da177e4 LT |
689 | |
690 | atomic_inc(&init_mm.mm_count); | |
691 | current->active_mm = &init_mm; | |
692 | ||
693 | smp_store_cpu_info(cpu); | |
5ad57078 | 694 | set_dec(tb_ticks_per_jiffy); |
e4d76e1c | 695 | preempt_disable(); |
1be6f10f | 696 | cpu_callin_map[cpu] = 1; |
1da177e4 | 697 | |
757cbd46 KG |
698 | if (smp_ops->setup_cpu) |
699 | smp_ops->setup_cpu(cpu); | |
1da177e4 LT |
700 | if (smp_ops->take_timebase) |
701 | smp_ops->take_timebase(); | |
702 | ||
d831d0b8 TB |
703 | secondary_cpu_time_init(); |
704 | ||
aeeafbfa BH |
705 | #ifdef CONFIG_PPC64 |
706 | if (system_state == SYSTEM_RUNNING) | |
707 | vdso_data->processorCount++; | |
18ad51dd AB |
708 | |
709 | vdso_getcpu_init(); | |
aeeafbfa | 710 | #endif |
e2075f79 | 711 | /* Update sibling maps */ |
99d86705 | 712 | base = cpu_first_thread_sibling(cpu); |
e2075f79 | 713 | for (i = 0; i < threads_per_core; i++) { |
cce606fe | 714 | if (cpu_is_offline(base + i) && (cpu != base + i)) |
e2075f79 | 715 | continue; |
cc1ba8ea AB |
716 | cpumask_set_cpu(cpu, cpu_sibling_mask(base + i)); |
717 | cpumask_set_cpu(base + i, cpu_sibling_mask(cpu)); | |
440a0857 NL |
718 | |
719 | /* cpu_core_map should be a superset of | |
720 | * cpu_sibling_map even if we don't have cache | |
721 | * information, so update the former here, too. | |
722 | */ | |
cc1ba8ea AB |
723 | cpumask_set_cpu(cpu, cpu_core_mask(base + i)); |
724 | cpumask_set_cpu(base + i, cpu_core_mask(cpu)); | |
e2075f79 | 725 | } |
a8a5356c | 726 | traverse_core_siblings(cpu, true); |
1da177e4 | 727 | |
bc3c4327 LZ |
728 | set_numa_node(numa_cpu_lookup_table[cpu]); |
729 | set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); | |
730 | ||
cce606fe LZ |
731 | smp_wmb(); |
732 | notify_cpu_starting(cpu); | |
733 | set_cpu_online(cpu, true); | |
734 | ||
1da177e4 LT |
735 | local_irq_enable(); |
736 | ||
799fef06 | 737 | cpu_startup_entry(CPUHP_ONLINE); |
fa3f82c8 BH |
738 | |
739 | BUG(); | |
1da177e4 LT |
740 | } |
741 | ||
742 | int setup_profiling_timer(unsigned int multiplier) | |
743 | { | |
744 | return 0; | |
745 | } | |
746 | ||
607b45e9 VG |
747 | #ifdef CONFIG_SCHED_SMT |
748 | /* cpumask of CPUs with asymetric SMT dependancy */ | |
b6220ad6 | 749 | static int powerpc_smt_flags(void) |
607b45e9 | 750 | { |
5d4dfddd | 751 | int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; |
607b45e9 VG |
752 | |
753 | if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { | |
754 | printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); | |
755 | flags |= SD_ASYM_PACKING; | |
756 | } | |
757 | return flags; | |
758 | } | |
759 | #endif | |
760 | ||
761 | static struct sched_domain_topology_level powerpc_topology[] = { | |
762 | #ifdef CONFIG_SCHED_SMT | |
763 | { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, | |
764 | #endif | |
765 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
766 | { NULL, }, | |
767 | }; | |
768 | ||
1da177e4 LT |
769 | void __init smp_cpus_done(unsigned int max_cpus) |
770 | { | |
bfb9126d | 771 | cpumask_var_t old_mask; |
1da177e4 LT |
772 | |
773 | /* We want the setup_cpu() here to be called from CPU 0, but our | |
774 | * init thread may have been "borrowed" by another CPU in the meantime | |
775 | * se we pin us down to CPU 0 for a short while | |
776 | */ | |
bfb9126d | 777 | alloc_cpumask_var(&old_mask, GFP_NOWAIT); |
104699c0 | 778 | cpumask_copy(old_mask, tsk_cpus_allowed(current)); |
21dbeb91 | 779 | set_cpus_allowed_ptr(current, cpumask_of(boot_cpuid)); |
1da177e4 | 780 | |
757cbd46 | 781 | if (smp_ops && smp_ops->setup_cpu) |
8cffc6ac | 782 | smp_ops->setup_cpu(boot_cpuid); |
1da177e4 | 783 | |
bfb9126d AB |
784 | set_cpus_allowed_ptr(current, old_mask); |
785 | ||
786 | free_cpumask_var(old_mask); | |
4b703a23 | 787 | |
d7294445 BH |
788 | if (smp_ops && smp_ops->bringup_done) |
789 | smp_ops->bringup_done(); | |
790 | ||
4b703a23 | 791 | dump_numa_cpu_topology(); |
d7294445 | 792 | |
607b45e9 | 793 | set_sched_topology(powerpc_topology); |
1da177e4 | 794 | |
e1f0ece1 MN |
795 | } |
796 | ||
1da177e4 LT |
797 | #ifdef CONFIG_HOTPLUG_CPU |
798 | int __cpu_disable(void) | |
799 | { | |
e2075f79 NL |
800 | int cpu = smp_processor_id(); |
801 | int base, i; | |
802 | int err; | |
1da177e4 | 803 | |
e2075f79 NL |
804 | if (!smp_ops->cpu_disable) |
805 | return -ENOSYS; | |
806 | ||
807 | err = smp_ops->cpu_disable(); | |
808 | if (err) | |
809 | return err; | |
810 | ||
811 | /* Update sibling maps */ | |
99d86705 | 812 | base = cpu_first_thread_sibling(cpu); |
e2075f79 | 813 | for (i = 0; i < threads_per_core; i++) { |
cc1ba8ea AB |
814 | cpumask_clear_cpu(cpu, cpu_sibling_mask(base + i)); |
815 | cpumask_clear_cpu(base + i, cpu_sibling_mask(cpu)); | |
816 | cpumask_clear_cpu(cpu, cpu_core_mask(base + i)); | |
817 | cpumask_clear_cpu(base + i, cpu_core_mask(cpu)); | |
440a0857 | 818 | } |
a8a5356c | 819 | traverse_core_siblings(cpu, false); |
e2075f79 NL |
820 | |
821 | return 0; | |
1da177e4 LT |
822 | } |
823 | ||
824 | void __cpu_die(unsigned int cpu) | |
825 | { | |
826 | if (smp_ops->cpu_die) | |
827 | smp_ops->cpu_die(cpu); | |
828 | } | |
d0174c72 | 829 | |
abb17f9c MM |
830 | void cpu_die(void) |
831 | { | |
832 | if (ppc_md.cpu_die) | |
833 | ppc_md.cpu_die(); | |
fa3f82c8 BH |
834 | |
835 | /* If we return, we re-enter start_secondary */ | |
836 | start_secondary_resume(); | |
abb17f9c | 837 | } |
fa3f82c8 | 838 | |
1da177e4 | 839 | #endif |