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arch: powerpc/fadump: Cleaning up inconsistent NULL checks
[deliverable/linux.git] / arch / powerpc / kernel / sysfs.c
CommitLineData
8a25a2fd 1#include <linux/device.h>
1da177e4
LT		 2#include <linux/cpu.h>
3#include <linux/smp.h>
4#include <linux/percpu.h>
5#include <linux/init.h>
6#include <linux/sched.h>
4b16f8e2 7#include <linux/export.h>
1da177e4
LT		 8#include <linux/nodemask.h>
9#include <linux/cpumask.h>
10#include <linux/notifier.h>
11
12#include <asm/current.h>
13#include <asm/processor.h>
14#include <asm/cputable.h>
15#include <asm/hvcall.h>
16#include <asm/prom.h>
1da177e4 17#include <asm/machdep.h>
2249ca9d 18#include <asm/smp.h>
a6dbf93a 19#include <asm/pmc.h>
d1211af3 20#include <asm/firmware.h>
1da177e4 21
93197a36
NL		 22#include "cacheinfo.h"
23
b950bdd0
BH		 24#ifdef CONFIG_PPC64
25#include <asm/paca.h>
26#include <asm/lppaca.h>
27#endif
28
1da177e4
LT		 29static DEFINE_PER_CPU(struct cpu, cpu_devices);
30
b950bdd0
BH		 31/*
32 * SMT snooze delay stuff, 64-bit only for now
33 */
34
35#ifdef CONFIG_PPC64
1da177e4 36
0ddd3e7d 37/* Time in microseconds we delay before sleeping in the idle loop */
b878dc00 38DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
1da177e4 39
8a25a2fd
KS		 40static ssize_t store_smt_snooze_delay(struct device *dev,
41 struct device_attribute *attr,
4a0b2b4d 42 const char *buf,
1da177e4
LT		 43 size_t count)
44{
8a25a2fd 45 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 46 ssize_t ret;
b878dc00 47 long snooze;
1da177e4 48
b878dc00 49 ret = sscanf(buf, "%ld", &snooze);
1da177e4
LT		 50 if (ret != 1)
51 return -EINVAL;
52
8a25a2fd 53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
1da177e4
LT		 54 return count;
55}
56
8a25a2fd
KS		 57static ssize_t show_smt_snooze_delay(struct device *dev,
58 struct device_attribute *attr,
4a0b2b4d 59 char *buf)
1da177e4 60{
8a25a2fd 61 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 62
8a25a2fd 63 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
1da177e4
LT		 64}
65
8a25a2fd 66static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
1da177e4
LT		 67 store_smt_snooze_delay);
68
1da177e4
LT		 69static int __init setup_smt_snooze_delay(char *str)
70{
71 unsigned int cpu;
b878dc00 72 long snooze;
1da177e4
LT		 73
74 if (!cpu_has_feature(CPU_FTR_SMT))
75 return 1;
76
b878dc00
AB		 77 snooze = simple_strtol(str, NULL, 10);
78 for_each_possible_cpu(cpu)
79 per_cpu(smt_snooze_delay, cpu) = snooze;
1da177e4
LT		 80
81 return 1;
82}
83__setup("smt-snooze-delay=", setup_smt_snooze_delay);
84
b950bdd0 85#endif /* CONFIG_PPC64 */
180a3362 86
a7189483
WD		 87#ifdef CONFIG_PPC_FSL_BOOK3E
88#define MAX_BIT 63
89
90static u64 pw20_wt;
91static u64 altivec_idle_wt;
92
93static unsigned int get_idle_ticks_bit(u64 ns)
94{
95 u64 cycle;
96
97 if (ns >= 10000)
98 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
99 else
100 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
101
102 if (!cycle)
103 return 0;
104
105 return ilog2(cycle);
106}
107
108static void do_show_pwrmgtcr0(void *val)
109{
110 u32 *value = val;
111
112 *value = mfspr(SPRN_PWRMGTCR0);
113}
114
115static ssize_t show_pw20_state(struct device *dev,
116 struct device_attribute *attr, char *buf)
117{
118 u32 value;
119 unsigned int cpu = dev->id;
120
121 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
122
123 value &= PWRMGTCR0_PW20_WAIT;
124
125 return sprintf(buf, "%u\n", value ? 1 : 0);
126}
127
128static void do_store_pw20_state(void *val)
129{
130 u32 *value = val;
131 u32 pw20_state;
132
133 pw20_state = mfspr(SPRN_PWRMGTCR0);
134
135 if (*value)
136 pw20_state |= PWRMGTCR0_PW20_WAIT;
137 else
138 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
139
140 mtspr(SPRN_PWRMGTCR0, pw20_state);
141}
142
143static ssize_t store_pw20_state(struct device *dev,
144 struct device_attribute *attr,
145 const char *buf, size_t count)
146{
147 u32 value;
148 unsigned int cpu = dev->id;
149
150 if (kstrtou32(buf, 0, &value))
151 return -EINVAL;
152
153 if (value > 1)
154 return -EINVAL;
155
156 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
157
158 return count;
159}
160
161static ssize_t show_pw20_wait_time(struct device *dev,
162 struct device_attribute *attr, char *buf)
163{
164 u32 value;
165 u64 tb_cycle = 1;
166 u64 time;
167
168 unsigned int cpu = dev->id;
169
170 if (!pw20_wt) {
171 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
172 value = (value & PWRMGTCR0_PW20_ENT) >>
173 PWRMGTCR0_PW20_ENT_SHIFT;
174
175 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
176 /* convert ms to ns */
177 if (tb_ticks_per_usec > 1000) {
178 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
179 } else {
180 u32 rem_us;
181
182 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
183 &rem_us);
184 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
185 }
186 } else {
187 time = pw20_wt;
188 }
189
190 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
191}
192
193static void set_pw20_wait_entry_bit(void *val)
194{
195 u32 *value = val;
196 u32 pw20_idle;
197
198 pw20_idle = mfspr(SPRN_PWRMGTCR0);
199
200 /* Set Automatic PW20 Core Idle Count */
201 /* clear count */
202 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
203
204 /* set count */
205 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
206
207 mtspr(SPRN_PWRMGTCR0, pw20_idle);
208}
209
210static ssize_t store_pw20_wait_time(struct device *dev,
211 struct device_attribute *attr,
212 const char *buf, size_t count)
213{
214 u32 entry_bit;
215 u64 value;
216
217 unsigned int cpu = dev->id;
218
219 if (kstrtou64(buf, 0, &value))
220 return -EINVAL;
221
222 if (!value)
223 return -EINVAL;
224
225 entry_bit = get_idle_ticks_bit(value);
226 if (entry_bit > MAX_BIT)
227 return -EINVAL;
228
229 pw20_wt = value;
230
231 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
232 &entry_bit, 1);
233
234 return count;
235}
236
237static ssize_t show_altivec_idle(struct device *dev,
238 struct device_attribute *attr, char *buf)
239{
240 u32 value;
241 unsigned int cpu = dev->id;
242
243 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
244
245 value &= PWRMGTCR0_AV_IDLE_PD_EN;
246
247 return sprintf(buf, "%u\n", value ? 1 : 0);
248}
249
250static void do_store_altivec_idle(void *val)
251{
252 u32 *value = val;
253 u32 altivec_idle;
254
255 altivec_idle = mfspr(SPRN_PWRMGTCR0);
256
257 if (*value)
258 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
259 else
260 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
261
262 mtspr(SPRN_PWRMGTCR0, altivec_idle);
263}
264
265static ssize_t store_altivec_idle(struct device *dev,
266 struct device_attribute *attr,
267 const char *buf, size_t count)
268{
269 u32 value;
270 unsigned int cpu = dev->id;
271
272 if (kstrtou32(buf, 0, &value))
273 return -EINVAL;
274
275 if (value > 1)
276 return -EINVAL;
277
278 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
279
280 return count;
281}
282
283static ssize_t show_altivec_idle_wait_time(struct device *dev,
284 struct device_attribute *attr, char *buf)
285{
286 u32 value;
287 u64 tb_cycle = 1;
288 u64 time;
289
290 unsigned int cpu = dev->id;
291
292 if (!altivec_idle_wt) {
293 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
294 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
295 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
296
297 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
298 /* convert ms to ns */
299 if (tb_ticks_per_usec > 1000) {
300 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
301 } else {
302 u32 rem_us;
303
304 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
305 &rem_us);
306 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
307 }
308 } else {
309 time = altivec_idle_wt;
310 }
311
312 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
313}
314
315static void set_altivec_idle_wait_entry_bit(void *val)
316{
317 u32 *value = val;
318 u32 altivec_idle;
319
320 altivec_idle = mfspr(SPRN_PWRMGTCR0);
321
322 /* Set Automatic AltiVec Idle Count */
323 /* clear count */
324 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
325
326 /* set count */
327 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
328
329 mtspr(SPRN_PWRMGTCR0, altivec_idle);
330}
331
332static ssize_t store_altivec_idle_wait_time(struct device *dev,
333 struct device_attribute *attr,
334 const char *buf, size_t count)
335{
336 u32 entry_bit;
337 u64 value;
338
339 unsigned int cpu = dev->id;
340
341 if (kstrtou64(buf, 0, &value))
342 return -EINVAL;
343
344 if (!value)
345 return -EINVAL;
346
347 entry_bit = get_idle_ticks_bit(value);
348 if (entry_bit > MAX_BIT)
349 return -EINVAL;
350
351 altivec_idle_wt = value;
352
353 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
354 &entry_bit, 1);
355
356 return count;
357}
358
359/*
360 * Enable/Disable interface:
361 * 0, disable. 1, enable.
362 */
363static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
364static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
365
366/*
367 * Set wait time interface:(Nanosecond)
368 * Example: Base on TBfreq is 41MHZ.
369 * 1~48(ns): TB[63]
370 * 49~97(ns): TB[62]
371 * 98~195(ns): TB[61]
372 * 196~390(ns): TB[60]
373 * 391~780(ns): TB[59]
374 * 781~1560(ns): TB[58]
375 * ...
376 */
377static DEVICE_ATTR(pw20_wait_time, 0600,
378 show_pw20_wait_time,
379 store_pw20_wait_time);
380static DEVICE_ATTR(altivec_idle_wait_time, 0600,
381 show_altivec_idle_wait_time,
382 store_altivec_idle_wait_time);
383#endif
384
1da177e4
LT		 385/*
386 * Enabling PMCs will slow partition context switch times so we only do
387 * it the first time we write to the PMCs.
388 */
389
390static DEFINE_PER_CPU(char, pmcs_enabled);
391
b950bdd0 392void ppc_enable_pmcs(void)
1da177e4 393{
a6dbf93a
PM		 394 ppc_set_pmu_inuse(1);
395
1da177e4
LT		 396 /* Only need to enable them once */
397 if (__get_cpu_var(pmcs_enabled))
398 return;
399
400 __get_cpu_var(pmcs_enabled) = 1;
401
180a3362
ME		 402 if (ppc_md.enable_pmcs)
403 ppc_md.enable_pmcs();
1da177e4 404}
b950bdd0 405EXPORT_SYMBOL(ppc_enable_pmcs);
1da177e4 406
fd7e4296 407#define __SYSFS_SPRSETUP(NAME, ADDRESS, EXTRA) \
9a371934 408static void read_##NAME(void *val) \
1da177e4 409{ \
ec78c8ac 410 *(unsigned long *)val = mfspr(ADDRESS); \
1da177e4 411} \
ec78c8ac 412static void write_##NAME(void *val) \
1da177e4 413{ \
fd7e4296 414 EXTRA; \
9a371934 415 mtspr(ADDRESS, *(unsigned long *)val); \
1da177e4 416} \
8a25a2fd
KS		 417static ssize_t show_##NAME(struct device *dev, \
418 struct device_attribute *attr, \
4a0b2b4d 419 char *buf) \
1da177e4 420{ \
8a25a2fd 421 struct cpu *cpu = container_of(dev, struct cpu, dev); \
9a371934 422 unsigned long val; \
8a25a2fd 423 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
1da177e4
LT		 424 return sprintf(buf, "%lx\n", val); \
425} \
3ff6eecc 426static ssize_t __used \
8a25a2fd 427 store_##NAME(struct device *dev, struct device_attribute *attr, \
4a0b2b4d 428 const char *buf, size_t count) \
1da177e4 429{ \
8a25a2fd 430 struct cpu *cpu = container_of(dev, struct cpu, dev); \
1da177e4
LT		 431 unsigned long val; \
432 int ret = sscanf(buf, "%lx", &val); \
433 if (ret != 1) \
434 return -EINVAL; \
8a25a2fd 435 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
1da177e4
LT		 436 return count; \
437}
438
fd7e4296
MS		 439#define SYSFS_PMCSETUP(NAME, ADDRESS) \
440 __SYSFS_SPRSETUP(NAME, ADDRESS, ppc_enable_pmcs())
441#define SYSFS_SPRSETUP(NAME, ADDRESS) \
442 __SYSFS_SPRSETUP(NAME, ADDRESS, )
6529c13d
OJ		 443
444/* Let's define all possible registers, we'll only hook up the ones
445 * that are implemented on the current processor
446 */
447
33a7f122 448#if defined(CONFIG_PPC64)
b950bdd0
BH		 449#define HAS_PPC_PMC_CLASSIC 1
450#define HAS_PPC_PMC_IBM 1
451#define HAS_PPC_PMC_PA6T 1
33a7f122 452#elif defined(CONFIG_6xx)
b950bdd0
BH		 453#define HAS_PPC_PMC_CLASSIC 1
454#define HAS_PPC_PMC_IBM 1
455#define HAS_PPC_PMC_G4 1
456#endif
457
458
459#ifdef HAS_PPC_PMC_CLASSIC
1da177e4
LT		 460SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
461SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
1da177e4
LT		 462SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
463SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
464SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
465SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
466SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
467SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
b950bdd0
BH		 468
469#ifdef HAS_PPC_PMC_G4
470SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
471#endif
472
473#ifdef CONFIG_PPC64
1da177e4
LT		 474SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
475SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
b950bdd0
BH		 476
477SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
fd7e4296
MS		 478SYSFS_SPRSETUP(purr, SPRN_PURR);
479SYSFS_SPRSETUP(spurr, SPRN_SPURR);
480SYSFS_SPRSETUP(dscr, SPRN_DSCR);
481SYSFS_SPRSETUP(pir, SPRN_PIR);
1da177e4 482
d1211af3
MS		 483/*
484 Lets only enable read for phyp resources and
485 enable write when needed with a separate function.
486 Lets be conservative and default to pseries.
487*/
8a25a2fd 488static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
d5dae721 489static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
8a25a2fd 490static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
d1211af3 491static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
7affca35 492static DEVICE_ATTR(pir, 0400, show_pir, NULL);
efcac658
AK		 493
494unsigned long dscr_default = 0;
495EXPORT_SYMBOL(dscr_default);
496
d1211af3
MS		 497static void add_write_permission_dev_attr(struct device_attribute *attr)
498{
499 attr->attr.mode |= 0200;
500}
501
8a25a2fd
KS		 502static ssize_t show_dscr_default(struct device *dev,
503 struct device_attribute *attr, char *buf)
efcac658
AK		 504{
505 return sprintf(buf, "%lx\n", dscr_default);
506}
507
1b6ca2a6
AB		 508static void update_dscr(void *dummy)
509{
00ca0de0
AB		 510 if (!current->thread.dscr_inherit) {
511 current->thread.dscr = dscr_default;
1b6ca2a6 512 mtspr(SPRN_DSCR, dscr_default);
00ca0de0 513 }
1b6ca2a6
AB		 514}
515
8a25a2fd
KS		 516static ssize_t __used store_dscr_default(struct device *dev,
517 struct device_attribute *attr, const char *buf,
efcac658
AK		 518 size_t count)
519{
520 unsigned long val;
521 int ret = 0;
522
523 ret = sscanf(buf, "%lx", &val);
524 if (ret != 1)
525 return -EINVAL;
526 dscr_default = val;
527
1b6ca2a6
AB		 528 on_each_cpu(update_dscr, NULL, 1);
529
efcac658
AK		 530 return count;
531}
532
8a25a2fd 533static DEVICE_ATTR(dscr_default, 0600,
efcac658
AK		 534 show_dscr_default, store_dscr_default);
535
536static void sysfs_create_dscr_default(void)
537{
538 int err = 0;
539 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 540 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
efcac658 541}
b950bdd0
BH		 542#endif /* CONFIG_PPC64 */
543
544#ifdef HAS_PPC_PMC_PA6T
25fc530e
OJ		 545SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
546SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
547SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
548SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
549SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
550SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
2e1957fd 551#ifdef CONFIG_DEBUG_KERNEL
fd7e4296
MS		 552SYSFS_SPRSETUP(hid0, SPRN_HID0);
553SYSFS_SPRSETUP(hid1, SPRN_HID1);
554SYSFS_SPRSETUP(hid4, SPRN_HID4);
555SYSFS_SPRSETUP(hid5, SPRN_HID5);
556SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
557SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
558SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
559SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
560SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
561SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
562SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
563SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
564SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
565SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
566SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
567SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
568SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
569SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
570SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
571SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
572SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
573SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
574SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
575SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
576SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
577SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
578SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
579SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
2e1957fd 580#endif /* CONFIG_DEBUG_KERNEL */
b950bdd0 581#endif /* HAS_PPC_PMC_PA6T */
6529c13d 582
b950bdd0 583#ifdef HAS_PPC_PMC_IBM
8a25a2fd
KS		 584static struct device_attribute ibm_common_attrs[] = {
585 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
586 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
6529c13d 587};
b950bdd0
BH		 588#endif /* HAS_PPC_PMC_G4 */
589
590#ifdef HAS_PPC_PMC_G4
8a25a2fd
KS		 591static struct device_attribute g4_common_attrs[] = {
592 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
593 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
594 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
b950bdd0
BH		 595};
596#endif /* HAS_PPC_PMC_G4 */
6529c13d 597
8a25a2fd
KS		 598static struct device_attribute classic_pmc_attrs[] = {
599 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
600 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
601 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
602 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
603 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
604 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
b950bdd0 605#ifdef CONFIG_PPC64
8a25a2fd
KS		 606 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
607 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
b950bdd0 608#endif
6529c13d
OJ		 609};
610
b950bdd0 611#ifdef HAS_PPC_PMC_PA6T
8a25a2fd
KS		 612static struct device_attribute pa6t_attrs[] = {
613 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
614 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
615 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
616 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
617 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
618 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
619 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
620 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
2e1957fd 621#ifdef CONFIG_DEBUG_KERNEL
8a25a2fd
KS		 622 __ATTR(hid0, 0600, show_hid0, store_hid0),
623 __ATTR(hid1, 0600, show_hid1, store_hid1),
624 __ATTR(hid4, 0600, show_hid4, store_hid4),
625 __ATTR(hid5, 0600, show_hid5, store_hid5),
626 __ATTR(ima0, 0600, show_ima0, store_ima0),
627 __ATTR(ima1, 0600, show_ima1, store_ima1),
628 __ATTR(ima2, 0600, show_ima2, store_ima2),
629 __ATTR(ima3, 0600, show_ima3, store_ima3),
630 __ATTR(ima4, 0600, show_ima4, store_ima4),
631 __ATTR(ima5, 0600, show_ima5, store_ima5),
632 __ATTR(ima6, 0600, show_ima6, store_ima6),
633 __ATTR(ima7, 0600, show_ima7, store_ima7),
634 __ATTR(ima8, 0600, show_ima8, store_ima8),
635 __ATTR(ima9, 0600, show_ima9, store_ima9),
636 __ATTR(imaat, 0600, show_imaat, store_imaat),
637 __ATTR(btcr, 0600, show_btcr, store_btcr),
638 __ATTR(pccr, 0600, show_pccr, store_pccr),
639 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
640 __ATTR(der, 0600, show_der, store_der),
641 __ATTR(mer, 0600, show_mer, store_mer),
642 __ATTR(ber, 0600, show_ber, store_ber),
643 __ATTR(ier, 0600, show_ier, store_ier),
644 __ATTR(sier, 0600, show_sier, store_sier),
645 __ATTR(siar, 0600, show_siar, store_siar),
646 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
647 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
648 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
649 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
2e1957fd 650#endif /* CONFIG_DEBUG_KERNEL */
6529c13d 651};
b950bdd0
BH		 652#endif /* HAS_PPC_PMC_PA6T */
653#endif /* HAS_PPC_PMC_CLASSIC */
6529c13d 654
061d19f2 655static void register_cpu_online(unsigned int cpu)
1da177e4
LT		 656{
657 struct cpu *c = &per_cpu(cpu_devices, cpu);
8a25a2fd
KS		 658 struct device *s = &c->dev;
659 struct device_attribute *attrs, *pmc_attrs;
6529c13d 660 int i, nattrs;
1da177e4 661
b950bdd0 662#ifdef CONFIG_PPC64
f5339277 663 if (cpu_has_feature(CPU_FTR_SMT))
8a25a2fd 664 device_create_file(s, &dev_attr_smt_snooze_delay);
b950bdd0 665#endif
1da177e4
LT		 666
667 /* PMC stuff */
6529c13d 668 switch (cur_cpu_spec->pmc_type) {
b950bdd0 669#ifdef HAS_PPC_PMC_IBM
6529c13d
OJ		 670 case PPC_PMC_IBM:
671 attrs = ibm_common_attrs;
8a25a2fd 672 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
b950bdd0 673 pmc_attrs = classic_pmc_attrs;
6529c13d 674 break;
b950bdd0
BH		 675#endif /* HAS_PPC_PMC_IBM */
676#ifdef HAS_PPC_PMC_G4
677 case PPC_PMC_G4:
678 attrs = g4_common_attrs;
8a25a2fd 679 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
b950bdd0
BH		 680 pmc_attrs = classic_pmc_attrs;
681 break;
682#endif /* HAS_PPC_PMC_G4 */
683#ifdef HAS_PPC_PMC_PA6T
6529c13d
OJ		 684 case PPC_PMC_PA6T:
685 /* PA Semi starts counting at PMC0 */
686 attrs = pa6t_attrs;
8a25a2fd 687 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
6529c13d
OJ		 688 pmc_attrs = NULL;
689 break;
b950bdd0 690#endif /* HAS_PPC_PMC_PA6T */
6529c13d
OJ		 691 default:
692 attrs = NULL;
693 nattrs = 0;
694 pmc_attrs = NULL;
695 }
696
697 for (i = 0; i < nattrs; i++)
8a25a2fd 698 device_create_file(s, &attrs[i]);
1da177e4 699
6529c13d
OJ		 700 if (pmc_attrs)
701 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
8a25a2fd 702 device_create_file(s, &pmc_attrs[i]);
1da177e4 703
b950bdd0 704#ifdef CONFIG_PPC64
1da177e4 705 if (cpu_has_feature(CPU_FTR_MMCRA))
8a25a2fd 706 device_create_file(s, &dev_attr_mmcra);
1da177e4 707
d1211af3
MS		 708 if (cpu_has_feature(CPU_FTR_PURR)) {
709 if (!firmware_has_feature(FW_FEATURE_LPAR))
710 add_write_permission_dev_attr(&dev_attr_purr);
8a25a2fd 711 device_create_file(s, &dev_attr_purr);
d1211af3 712 }
4c198557 713
f050982a 714 if (cpu_has_feature(CPU_FTR_SPURR))
8a25a2fd 715 device_create_file(s, &dev_attr_spurr);
f050982a 716
4c198557 717 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 718 device_create_file(s, &dev_attr_dscr);
595fe914
AM		 719
720 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
7affca35 721 device_create_file(s, &dev_attr_pir);
b950bdd0 722#endif /* CONFIG_PPC64 */
124c27d3 723
a7189483
WD		 724#ifdef CONFIG_PPC_FSL_BOOK3E
725 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
726 device_create_file(s, &dev_attr_pw20_state);
727 device_create_file(s, &dev_attr_pw20_wait_time);
728
729 device_create_file(s, &dev_attr_altivec_idle);
730 device_create_file(s, &dev_attr_altivec_idle_wait_time);
731 }
732#endif
93197a36 733 cacheinfo_cpu_online(cpu);
1da177e4
LT		 734}
735
736#ifdef CONFIG_HOTPLUG_CPU
737static void unregister_cpu_online(unsigned int cpu)
738{
739 struct cpu *c = &per_cpu(cpu_devices, cpu);
8a25a2fd
KS		 740 struct device *s = &c->dev;
741 struct device_attribute *attrs, *pmc_attrs;
6529c13d 742 int i, nattrs;
1da177e4 743
72486f1f 744 BUG_ON(!c->hotpluggable);
1da177e4 745
a1e0eb10 746#ifdef CONFIG_PPC64
f5339277 747 if (cpu_has_feature(CPU_FTR_SMT))
8a25a2fd 748 device_remove_file(s, &dev_attr_smt_snooze_delay);
a1e0eb10 749#endif
1da177e4
LT		 750
751 /* PMC stuff */
6529c13d 752 switch (cur_cpu_spec->pmc_type) {
b950bdd0 753#ifdef HAS_PPC_PMC_IBM
6529c13d
OJ		 754 case PPC_PMC_IBM:
755 attrs = ibm_common_attrs;
8a25a2fd 756 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
b950bdd0
BH		 757 pmc_attrs = classic_pmc_attrs;
758 break;
759#endif /* HAS_PPC_PMC_IBM */
760#ifdef HAS_PPC_PMC_G4
761 case PPC_PMC_G4:
762 attrs = g4_common_attrs;
8a25a2fd 763 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
b950bdd0 764 pmc_attrs = classic_pmc_attrs;
6529c13d 765 break;
b950bdd0
BH		 766#endif /* HAS_PPC_PMC_G4 */
767#ifdef HAS_PPC_PMC_PA6T
6529c13d
OJ		 768 case PPC_PMC_PA6T:
769 /* PA Semi starts counting at PMC0 */
770 attrs = pa6t_attrs;
8a25a2fd 771 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
6529c13d
OJ		 772 pmc_attrs = NULL;
773 break;
b950bdd0 774#endif /* HAS_PPC_PMC_PA6T */
6529c13d
OJ		 775 default:
776 attrs = NULL;
777 nattrs = 0;
778 pmc_attrs = NULL;
779 }
1da177e4 780
6529c13d 781 for (i = 0; i < nattrs; i++)
8a25a2fd 782 device_remove_file(s, &attrs[i]);
6529c13d
OJ		 783
784 if (pmc_attrs)
785 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
8a25a2fd 786 device_remove_file(s, &pmc_attrs[i]);
1da177e4 787
b950bdd0 788#ifdef CONFIG_PPC64
1da177e4 789 if (cpu_has_feature(CPU_FTR_MMCRA))
8a25a2fd 790 device_remove_file(s, &dev_attr_mmcra);
1da177e4 791
afd05423 792 if (cpu_has_feature(CPU_FTR_PURR))
8a25a2fd 793 device_remove_file(s, &dev_attr_purr);
4c198557 794
f050982a 795 if (cpu_has_feature(CPU_FTR_SPURR))
8a25a2fd 796 device_remove_file(s, &dev_attr_spurr);
f050982a 797
4c198557 798 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 799 device_remove_file(s, &dev_attr_dscr);
595fe914
AM		 800
801 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
7affca35 802 device_remove_file(s, &dev_attr_pir);
b950bdd0 803#endif /* CONFIG_PPC64 */
124c27d3 804
a7189483
WD		 805#ifdef CONFIG_PPC_FSL_BOOK3E
806 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
807 device_remove_file(s, &dev_attr_pw20_state);
808 device_remove_file(s, &dev_attr_pw20_wait_time);
809
810 device_remove_file(s, &dev_attr_altivec_idle);
811 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
812 }
813#endif
93197a36 814 cacheinfo_cpu_offline(cpu);
1da177e4 815}
12633e80
NF		 816
817#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
818ssize_t arch_cpu_probe(const char *buf, size_t count)
819{
820 if (ppc_md.cpu_probe)
821 return ppc_md.cpu_probe(buf, count);
822
823 return -EINVAL;
824}
825
826ssize_t arch_cpu_release(const char *buf, size_t count)
827{
828 if (ppc_md.cpu_release)
829 return ppc_md.cpu_release(buf, count);
830
831 return -EINVAL;
832}
833#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
834
1da177e4
LT		 835#endif /* CONFIG_HOTPLUG_CPU */
836
061d19f2 837static int sysfs_cpu_notify(struct notifier_block *self,
1da177e4
LT		 838 unsigned long action, void *hcpu)
839{
840 unsigned int cpu = (unsigned int)(long)hcpu;
841
842 switch (action) {
843 case CPU_ONLINE:
8bb78442 844 case CPU_ONLINE_FROZEN:
1da177e4
LT		 845 register_cpu_online(cpu);
846 break;
847#ifdef CONFIG_HOTPLUG_CPU
848 case CPU_DEAD:
8bb78442 849 case CPU_DEAD_FROZEN:
1da177e4
LT		 850 unregister_cpu_online(cpu);
851 break;
852#endif
853 }
854 return NOTIFY_OK;
855}
856
061d19f2 857static struct notifier_block sysfs_cpu_nb = {
1da177e4
LT		 858 .notifier_call = sysfs_cpu_notify,
859};
860
0344c6c5
CK		 861static DEFINE_MUTEX(cpu_mutex);
862
8a25a2fd 863int cpu_add_dev_attr(struct device_attribute *attr)
0344c6c5
CK		 864{
865 int cpu;
866
867 mutex_lock(&cpu_mutex);
868
869 for_each_possible_cpu(cpu) {
8a25a2fd 870 device_create_file(get_cpu_device(cpu), attr);
0344c6c5
CK		 871 }
872
873 mutex_unlock(&cpu_mutex);
874 return 0;
875}
8a25a2fd 876EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
0344c6c5 877
8a25a2fd 878int cpu_add_dev_attr_group(struct attribute_group *attrs)
0344c6c5
CK		 879{
880 int cpu;
8a25a2fd 881 struct device *dev;
6bcc4c01 882 int ret;
0344c6c5
CK		 883
884 mutex_lock(&cpu_mutex);
885
886 for_each_possible_cpu(cpu) {
8a25a2fd
KS		 887 dev = get_cpu_device(cpu);
888 ret = sysfs_create_group(&dev->kobj, attrs);
6bcc4c01 889 WARN_ON(ret != 0);
0344c6c5
CK		 890 }
891
892 mutex_unlock(&cpu_mutex);
893 return 0;
894}
8a25a2fd 895EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
0344c6c5
CK		 896
897
8a25a2fd 898void cpu_remove_dev_attr(struct device_attribute *attr)
0344c6c5
CK		 899{
900 int cpu;
901
902 mutex_lock(&cpu_mutex);
903
904 for_each_possible_cpu(cpu) {
8a25a2fd 905 device_remove_file(get_cpu_device(cpu), attr);
0344c6c5
CK		 906 }
907
908 mutex_unlock(&cpu_mutex);
909}
8a25a2fd 910EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
0344c6c5 911
8a25a2fd 912void cpu_remove_dev_attr_group(struct attribute_group *attrs)
0344c6c5
CK		 913{
914 int cpu;
8a25a2fd 915 struct device *dev;
0344c6c5
CK		 916
917 mutex_lock(&cpu_mutex);
918
919 for_each_possible_cpu(cpu) {
8a25a2fd
KS		 920 dev = get_cpu_device(cpu);
921 sysfs_remove_group(&dev->kobj, attrs);
0344c6c5
CK		 922 }
923
924 mutex_unlock(&cpu_mutex);
925}
8a25a2fd 926EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
0344c6c5
CK		 927
928
1da177e4
LT		 929/* NUMA stuff */
930
931#ifdef CONFIG_NUMA
1da177e4
LT		 932static void register_nodes(void)
933{
934 int i;
935
0fc44159
YG		 936 for (i = 0; i < MAX_NUMNODES; i++)
937 register_one_node(i);
1da177e4 938}
953039c8 939
8a25a2fd 940int sysfs_add_device_to_node(struct device *dev, int nid)
953039c8 941{
8732794b 942 struct node *node = node_devices[nid];
10fbcf4c 943 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
953039c8
JK		 944 kobject_name(&dev->kobj));
945}
12654f77 946EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
953039c8 947
8a25a2fd 948void sysfs_remove_device_from_node(struct device *dev, int nid)
953039c8 949{
8732794b 950 struct node *node = node_devices[nid];
10fbcf4c 951 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
953039c8 952}
12654f77 953EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
953039c8 954
1da177e4
LT		 955#else
956static void register_nodes(void)
957{
958 return;
959}
953039c8 960
1da177e4
LT		 961#endif
962
963/* Only valid if CPU is present. */
8a25a2fd
KS		 964static ssize_t show_physical_id(struct device *dev,
965 struct device_attribute *attr, char *buf)
1da177e4 966{
8a25a2fd 967 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 968
8a25a2fd 969 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1da177e4 970}
8a25a2fd 971static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1da177e4
LT		 972
973static int __init topology_init(void)
974{
975 int cpu;
1da177e4
LT		 976
977 register_nodes();
d1a55113
SB		 978
979 cpu_notifier_register_begin();
1da177e4 980
0e551954 981 for_each_possible_cpu(cpu) {
1da177e4
LT		 982 struct cpu *c = &per_cpu(cpu_devices, cpu);
983
1da177e4
LT		 984 /*
985 * For now, we just see if the system supports making
986 * the RTAS calls for CPU hotplug. But, there may be a
987 * more comprehensive way to do this for an individual
988 * CPU. For instance, the boot cpu might never be valid
989 * for hotplugging.
990 */
72486f1f
SS		 991 if (ppc_md.cpu_die)
992 c->hotpluggable = 1;
1da177e4 993
72486f1f 994 if (cpu_online(cpu) || c->hotpluggable) {
76b67ed9 995 register_cpu(c, cpu);
1da177e4 996
8a25a2fd 997 device_create_file(&c->dev, &dev_attr_physical_id);
1da177e4
LT		 998 }
999
1000 if (cpu_online(cpu))
1001 register_cpu_online(cpu);
1002 }
d1a55113
SB		 1003
1004 __register_cpu_notifier(&sysfs_cpu_nb);
1005
1006 cpu_notifier_register_done();
1007
efcac658
AK		 1008#ifdef CONFIG_PPC64
1009 sysfs_create_dscr_default();
1010#endif /* CONFIG_PPC64 */
1da177e4
LT		 1011
1012 return 0;
1013}
e9e77ce8 1014subsys_initcall(topology_init);
Linux kernel - Deliverables
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