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14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@samba.org) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/stddef.h> | |
23 | #include <linux/unistd.h> | |
8dad3f92 | 24 | #include <linux/ptrace.h> |
14cf11af PM |
25 | #include <linux/slab.h> |
26 | #include <linux/user.h> | |
27 | #include <linux/a.out.h> | |
28 | #include <linux/interrupt.h> | |
14cf11af PM |
29 | #include <linux/init.h> |
30 | #include <linux/module.h> | |
8dad3f92 | 31 | #include <linux/prctl.h> |
14cf11af PM |
32 | #include <linux/delay.h> |
33 | #include <linux/kprobes.h> | |
14cf11af | 34 | |
86417780 | 35 | #include <asm/kdebug.h> |
14cf11af PM |
36 | #include <asm/pgtable.h> |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/system.h> | |
39 | #include <asm/io.h> | |
86417780 PM |
40 | #include <asm/machdep.h> |
41 | #include <asm/rtas.h> | |
42 | #include <asm/xmon.h> | |
f7f6f4fe | 43 | #include <asm/pmc.h> |
dc1c1ca3 | 44 | #ifdef CONFIG_PPC32 |
14cf11af | 45 | #include <asm/reg.h> |
86417780 | 46 | #endif |
14cf11af PM |
47 | #ifdef CONFIG_PMAC_BACKLIGHT |
48 | #include <asm/backlight.h> | |
49 | #endif | |
dc1c1ca3 | 50 | #ifdef CONFIG_PPC64 |
86417780 | 51 | #include <asm/firmware.h> |
dc1c1ca3 | 52 | #include <asm/processor.h> |
dc1c1ca3 | 53 | #include <asm/systemcfg.h> |
dc1c1ca3 SR |
54 | #endif |
55 | ||
86417780 PM |
56 | #ifdef CONFIG_PPC64 /* XXX */ |
57 | #define _IO_BASE pci_io_base | |
58 | #endif | |
59 | ||
14cf11af PM |
60 | #ifdef CONFIG_DEBUGGER |
61 | int (*__debugger)(struct pt_regs *regs); | |
62 | int (*__debugger_ipi)(struct pt_regs *regs); | |
63 | int (*__debugger_bpt)(struct pt_regs *regs); | |
64 | int (*__debugger_sstep)(struct pt_regs *regs); | |
65 | int (*__debugger_iabr_match)(struct pt_regs *regs); | |
66 | int (*__debugger_dabr_match)(struct pt_regs *regs); | |
67 | int (*__debugger_fault_handler)(struct pt_regs *regs); | |
68 | ||
69 | EXPORT_SYMBOL(__debugger); | |
70 | EXPORT_SYMBOL(__debugger_ipi); | |
71 | EXPORT_SYMBOL(__debugger_bpt); | |
72 | EXPORT_SYMBOL(__debugger_sstep); | |
73 | EXPORT_SYMBOL(__debugger_iabr_match); | |
74 | EXPORT_SYMBOL(__debugger_dabr_match); | |
75 | EXPORT_SYMBOL(__debugger_fault_handler); | |
76 | #endif | |
77 | ||
78 | struct notifier_block *powerpc_die_chain; | |
79 | static DEFINE_SPINLOCK(die_notifier_lock); | |
80 | ||
81 | int register_die_notifier(struct notifier_block *nb) | |
82 | { | |
83 | int err = 0; | |
84 | unsigned long flags; | |
85 | ||
86 | spin_lock_irqsave(&die_notifier_lock, flags); | |
87 | err = notifier_chain_register(&powerpc_die_chain, nb); | |
88 | spin_unlock_irqrestore(&die_notifier_lock, flags); | |
89 | return err; | |
90 | } | |
91 | ||
92 | /* | |
93 | * Trap & Exception support | |
94 | */ | |
95 | ||
96 | static DEFINE_SPINLOCK(die_lock); | |
97 | ||
98 | int die(const char *str, struct pt_regs *regs, long err) | |
99 | { | |
100 | static int die_counter; | |
101 | int nl = 0; | |
102 | ||
103 | if (debugger(regs)) | |
104 | return 1; | |
105 | ||
106 | console_verbose(); | |
107 | spin_lock_irq(&die_lock); | |
108 | bust_spinlocks(1); | |
8dad3f92 | 109 | #ifdef CONFIG_PMAC_BACKLIGHT |
14cf11af PM |
110 | if (_machine == _MACH_Pmac) { |
111 | set_backlight_enable(1); | |
112 | set_backlight_level(BACKLIGHT_MAX); | |
113 | } | |
114 | #endif | |
115 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
116 | #ifdef CONFIG_PREEMPT | |
117 | printk("PREEMPT "); | |
118 | nl = 1; | |
119 | #endif | |
120 | #ifdef CONFIG_SMP | |
121 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
122 | nl = 1; | |
123 | #endif | |
124 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
125 | printk("DEBUG_PAGEALLOC "); | |
126 | nl = 1; | |
127 | #endif | |
128 | #ifdef CONFIG_NUMA | |
129 | printk("NUMA "); | |
130 | nl = 1; | |
131 | #endif | |
132 | #ifdef CONFIG_PPC64 | |
133 | switch (systemcfg->platform) { | |
134 | case PLATFORM_PSERIES: | |
135 | printk("PSERIES "); | |
136 | nl = 1; | |
137 | break; | |
138 | case PLATFORM_PSERIES_LPAR: | |
139 | printk("PSERIES LPAR "); | |
140 | nl = 1; | |
141 | break; | |
142 | case PLATFORM_ISERIES_LPAR: | |
143 | printk("ISERIES LPAR "); | |
144 | nl = 1; | |
145 | break; | |
146 | case PLATFORM_POWERMAC: | |
147 | printk("POWERMAC "); | |
148 | nl = 1; | |
149 | break; | |
150 | case PLATFORM_BPA: | |
151 | printk("BPA "); | |
152 | nl = 1; | |
153 | break; | |
154 | } | |
155 | #endif | |
156 | if (nl) | |
157 | printk("\n"); | |
158 | print_modules(); | |
159 | show_regs(regs); | |
160 | bust_spinlocks(0); | |
161 | spin_unlock_irq(&die_lock); | |
162 | ||
163 | if (in_interrupt()) | |
164 | panic("Fatal exception in interrupt"); | |
165 | ||
166 | if (panic_on_oops) { | |
dc1c1ca3 SR |
167 | #ifdef CONFIG_PPC64 |
168 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | |
169 | ssleep(5); | |
170 | #endif | |
14cf11af PM |
171 | panic("Fatal exception"); |
172 | } | |
173 | do_exit(err); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
178 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) | |
179 | { | |
180 | siginfo_t info; | |
181 | ||
182 | if (!user_mode(regs)) { | |
183 | if (die("Exception in kernel mode", regs, signr)) | |
184 | return; | |
185 | } | |
186 | ||
187 | memset(&info, 0, sizeof(info)); | |
188 | info.si_signo = signr; | |
189 | info.si_code = code; | |
190 | info.si_addr = (void __user *) addr; | |
191 | force_sig_info(signr, &info, current); | |
192 | ||
193 | /* | |
194 | * Init gets no signals that it doesn't have a handler for. | |
195 | * That's all very well, but if it has caused a synchronous | |
196 | * exception and we ignore the resulting signal, it will just | |
197 | * generate the same exception over and over again and we get | |
198 | * nowhere. Better to kill it and let the kernel panic. | |
199 | */ | |
200 | if (current->pid == 1) { | |
201 | __sighandler_t handler; | |
202 | ||
203 | spin_lock_irq(¤t->sighand->siglock); | |
204 | handler = current->sighand->action[signr-1].sa.sa_handler; | |
205 | spin_unlock_irq(¤t->sighand->siglock); | |
206 | if (handler == SIG_DFL) { | |
207 | /* init has generated a synchronous exception | |
208 | and it doesn't have a handler for the signal */ | |
209 | printk(KERN_CRIT "init has generated signal %d " | |
210 | "but has no handler for it\n", signr); | |
211 | do_exit(signr); | |
212 | } | |
213 | } | |
214 | } | |
215 | ||
216 | #ifdef CONFIG_PPC64 | |
217 | void system_reset_exception(struct pt_regs *regs) | |
218 | { | |
219 | /* See if any machine dependent calls */ | |
220 | if (ppc_md.system_reset_exception) | |
221 | ppc_md.system_reset_exception(regs); | |
222 | ||
8dad3f92 | 223 | die("System Reset", regs, SIGABRT); |
14cf11af PM |
224 | |
225 | /* Must die if the interrupt is not recoverable */ | |
226 | if (!(regs->msr & MSR_RI)) | |
227 | panic("Unrecoverable System Reset"); | |
228 | ||
229 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
230 | } | |
231 | #endif | |
232 | ||
233 | /* | |
234 | * I/O accesses can cause machine checks on powermacs. | |
235 | * Check if the NIP corresponds to the address of a sync | |
236 | * instruction for which there is an entry in the exception | |
237 | * table. | |
238 | * Note that the 601 only takes a machine check on TEA | |
239 | * (transfer error ack) signal assertion, and does not | |
240 | * set any of the top 16 bits of SRR1. | |
241 | * -- paulus. | |
242 | */ | |
243 | static inline int check_io_access(struct pt_regs *regs) | |
244 | { | |
245 | #ifdef CONFIG_PPC_PMAC | |
246 | unsigned long msr = regs->msr; | |
247 | const struct exception_table_entry *entry; | |
248 | unsigned int *nip = (unsigned int *)regs->nip; | |
249 | ||
250 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
251 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
252 | /* | |
253 | * Check that it's a sync instruction, or somewhere | |
254 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
255 | * As the address is in the exception table | |
256 | * we should be able to read the instr there. | |
257 | * For the debug message, we look at the preceding | |
258 | * load or store. | |
259 | */ | |
260 | if (*nip == 0x60000000) /* nop */ | |
261 | nip -= 2; | |
262 | else if (*nip == 0x4c00012c) /* isync */ | |
263 | --nip; | |
264 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
265 | /* sync or twi */ | |
266 | unsigned int rb; | |
267 | ||
268 | --nip; | |
269 | rb = (*nip >> 11) & 0x1f; | |
270 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
271 | (*nip & 0x100)? "OUT to": "IN from", | |
272 | regs->gpr[rb] - _IO_BASE, nip); | |
273 | regs->msr |= MSR_RI; | |
274 | regs->nip = entry->fixup; | |
275 | return 1; | |
276 | } | |
277 | } | |
278 | #endif /* CONFIG_PPC_PMAC */ | |
279 | return 0; | |
280 | } | |
281 | ||
282 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
283 | /* On 4xx, the reason for the machine check or program exception | |
284 | is in the ESR. */ | |
285 | #define get_reason(regs) ((regs)->dsisr) | |
286 | #ifndef CONFIG_FSL_BOOKE | |
287 | #define get_mc_reason(regs) ((regs)->dsisr) | |
288 | #else | |
289 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) | |
290 | #endif | |
291 | #define REASON_FP ESR_FP | |
292 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
293 | #define REASON_PRIVILEGED ESR_PPR | |
294 | #define REASON_TRAP ESR_PTR | |
295 | ||
296 | /* single-step stuff */ | |
297 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
298 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
299 | ||
300 | #else | |
301 | /* On non-4xx, the reason for the machine check or program | |
302 | exception is in the MSR. */ | |
303 | #define get_reason(regs) ((regs)->msr) | |
304 | #define get_mc_reason(regs) ((regs)->msr) | |
305 | #define REASON_FP 0x100000 | |
306 | #define REASON_ILLEGAL 0x80000 | |
307 | #define REASON_PRIVILEGED 0x40000 | |
308 | #define REASON_TRAP 0x20000 | |
309 | ||
310 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
311 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
312 | #endif | |
313 | ||
314 | /* | |
315 | * This is "fall-back" implementation for configurations | |
316 | * which don't provide platform-specific machine check info | |
317 | */ | |
318 | void __attribute__ ((weak)) | |
319 | platform_machine_check(struct pt_regs *regs) | |
320 | { | |
321 | } | |
322 | ||
dc1c1ca3 | 323 | void machine_check_exception(struct pt_regs *regs) |
14cf11af PM |
324 | { |
325 | #ifdef CONFIG_PPC64 | |
326 | int recover = 0; | |
327 | ||
328 | /* See if any machine dependent calls */ | |
329 | if (ppc_md.machine_check_exception) | |
330 | recover = ppc_md.machine_check_exception(regs); | |
331 | ||
332 | if (recover) | |
333 | return; | |
334 | #else | |
335 | unsigned long reason = get_mc_reason(regs); | |
336 | ||
337 | if (user_mode(regs)) { | |
338 | regs->msr |= MSR_RI; | |
339 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
340 | return; | |
341 | } | |
342 | ||
343 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
344 | /* the qspan pci read routines can cause machine checks -- Cort */ | |
345 | bad_page_fault(regs, regs->dar, SIGBUS); | |
346 | return; | |
347 | #endif | |
348 | ||
349 | if (debugger_fault_handler(regs)) { | |
350 | regs->msr |= MSR_RI; | |
351 | return; | |
352 | } | |
353 | ||
354 | if (check_io_access(regs)) | |
355 | return; | |
356 | ||
357 | #if defined(CONFIG_4xx) && !defined(CONFIG_440A) | |
358 | if (reason & ESR_IMCP) { | |
359 | printk("Instruction"); | |
360 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
361 | } else | |
362 | printk("Data"); | |
363 | printk(" machine check in kernel mode.\n"); | |
364 | #elif defined(CONFIG_440A) | |
365 | printk("Machine check in kernel mode.\n"); | |
366 | if (reason & ESR_IMCP){ | |
367 | printk("Instruction Synchronous Machine Check exception\n"); | |
368 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
369 | } | |
370 | else { | |
371 | u32 mcsr = mfspr(SPRN_MCSR); | |
372 | if (mcsr & MCSR_IB) | |
373 | printk("Instruction Read PLB Error\n"); | |
374 | if (mcsr & MCSR_DRB) | |
375 | printk("Data Read PLB Error\n"); | |
376 | if (mcsr & MCSR_DWB) | |
377 | printk("Data Write PLB Error\n"); | |
378 | if (mcsr & MCSR_TLBP) | |
379 | printk("TLB Parity Error\n"); | |
380 | if (mcsr & MCSR_ICP){ | |
381 | flush_instruction_cache(); | |
382 | printk("I-Cache Parity Error\n"); | |
383 | } | |
384 | if (mcsr & MCSR_DCSP) | |
385 | printk("D-Cache Search Parity Error\n"); | |
386 | if (mcsr & MCSR_DCFP) | |
387 | printk("D-Cache Flush Parity Error\n"); | |
388 | if (mcsr & MCSR_IMPE) | |
389 | printk("Machine Check exception is imprecise\n"); | |
390 | ||
391 | /* Clear MCSR */ | |
392 | mtspr(SPRN_MCSR, mcsr); | |
393 | } | |
394 | #elif defined (CONFIG_E500) | |
395 | printk("Machine check in kernel mode.\n"); | |
396 | printk("Caused by (from MCSR=%lx): ", reason); | |
397 | ||
398 | if (reason & MCSR_MCP) | |
399 | printk("Machine Check Signal\n"); | |
400 | if (reason & MCSR_ICPERR) | |
401 | printk("Instruction Cache Parity Error\n"); | |
402 | if (reason & MCSR_DCP_PERR) | |
403 | printk("Data Cache Push Parity Error\n"); | |
404 | if (reason & MCSR_DCPERR) | |
405 | printk("Data Cache Parity Error\n"); | |
406 | if (reason & MCSR_GL_CI) | |
407 | printk("Guarded Load or Cache-Inhibited stwcx.\n"); | |
408 | if (reason & MCSR_BUS_IAERR) | |
409 | printk("Bus - Instruction Address Error\n"); | |
410 | if (reason & MCSR_BUS_RAERR) | |
411 | printk("Bus - Read Address Error\n"); | |
412 | if (reason & MCSR_BUS_WAERR) | |
413 | printk("Bus - Write Address Error\n"); | |
414 | if (reason & MCSR_BUS_IBERR) | |
415 | printk("Bus - Instruction Data Error\n"); | |
416 | if (reason & MCSR_BUS_RBERR) | |
417 | printk("Bus - Read Data Bus Error\n"); | |
418 | if (reason & MCSR_BUS_WBERR) | |
419 | printk("Bus - Read Data Bus Error\n"); | |
420 | if (reason & MCSR_BUS_IPERR) | |
421 | printk("Bus - Instruction Parity Error\n"); | |
422 | if (reason & MCSR_BUS_RPERR) | |
423 | printk("Bus - Read Parity Error\n"); | |
424 | #elif defined (CONFIG_E200) | |
425 | printk("Machine check in kernel mode.\n"); | |
426 | printk("Caused by (from MCSR=%lx): ", reason); | |
427 | ||
428 | if (reason & MCSR_MCP) | |
429 | printk("Machine Check Signal\n"); | |
430 | if (reason & MCSR_CP_PERR) | |
431 | printk("Cache Push Parity Error\n"); | |
432 | if (reason & MCSR_CPERR) | |
433 | printk("Cache Parity Error\n"); | |
434 | if (reason & MCSR_EXCP_ERR) | |
435 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
436 | if (reason & MCSR_BUS_IRERR) | |
437 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
438 | if (reason & MCSR_BUS_DRERR) | |
439 | printk("Bus - Read Bus Error on data load\n"); | |
440 | if (reason & MCSR_BUS_WRERR) | |
441 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
442 | #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ | |
443 | printk("Machine check in kernel mode.\n"); | |
444 | printk("Caused by (from SRR1=%lx): ", reason); | |
445 | switch (reason & 0x601F0000) { | |
446 | case 0x80000: | |
447 | printk("Machine check signal\n"); | |
448 | break; | |
449 | case 0: /* for 601 */ | |
450 | case 0x40000: | |
451 | case 0x140000: /* 7450 MSS error and TEA */ | |
452 | printk("Transfer error ack signal\n"); | |
453 | break; | |
454 | case 0x20000: | |
455 | printk("Data parity error signal\n"); | |
456 | break; | |
457 | case 0x10000: | |
458 | printk("Address parity error signal\n"); | |
459 | break; | |
460 | case 0x20000000: | |
461 | printk("L1 Data Cache error\n"); | |
462 | break; | |
463 | case 0x40000000: | |
464 | printk("L1 Instruction Cache error\n"); | |
465 | break; | |
466 | case 0x00100000: | |
467 | printk("L2 data cache parity error\n"); | |
468 | break; | |
469 | default: | |
470 | printk("Unknown values in msr\n"); | |
471 | } | |
472 | #endif /* CONFIG_4xx */ | |
473 | ||
474 | /* | |
475 | * Optional platform-provided routine to print out | |
476 | * additional info, e.g. bus error registers. | |
477 | */ | |
478 | platform_machine_check(regs); | |
86417780 | 479 | #endif /* CONFIG_PPC64 */ |
14cf11af PM |
480 | |
481 | if (debugger_fault_handler(regs)) | |
482 | return; | |
8dad3f92 | 483 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
484 | |
485 | /* Must die if the interrupt is not recoverable */ | |
486 | if (!(regs->msr & MSR_RI)) | |
487 | panic("Unrecoverable Machine check"); | |
488 | } | |
489 | ||
490 | void SMIException(struct pt_regs *regs) | |
491 | { | |
492 | die("System Management Interrupt", regs, SIGABRT); | |
493 | } | |
494 | ||
dc1c1ca3 | 495 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
496 | { |
497 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
498 | regs->nip, regs->msr, regs->trap); | |
499 | ||
500 | _exception(SIGTRAP, regs, 0, 0); | |
501 | } | |
502 | ||
dc1c1ca3 | 503 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
504 | { |
505 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
506 | 5, SIGTRAP) == NOTIFY_STOP) | |
507 | return; | |
508 | if (debugger_iabr_match(regs)) | |
509 | return; | |
510 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
511 | } | |
512 | ||
513 | void RunModeException(struct pt_regs *regs) | |
514 | { | |
515 | _exception(SIGTRAP, regs, 0, 0); | |
516 | } | |
517 | ||
8dad3f92 | 518 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af PM |
519 | { |
520 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
521 | ||
522 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
523 | 5, SIGTRAP) == NOTIFY_STOP) | |
524 | return; | |
525 | if (debugger_sstep(regs)) | |
526 | return; | |
527 | ||
528 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
529 | } | |
530 | ||
531 | /* | |
532 | * After we have successfully emulated an instruction, we have to | |
533 | * check if the instruction was being single-stepped, and if so, | |
534 | * pretend we got a single-step exception. This was pointed out | |
535 | * by Kumar Gala. -- paulus | |
536 | */ | |
8dad3f92 | 537 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af PM |
538 | { |
539 | if (single_stepping(regs)) { | |
540 | clear_single_step(regs); | |
541 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
542 | } | |
543 | } | |
544 | ||
dc1c1ca3 SR |
545 | static void parse_fpe(struct pt_regs *regs) |
546 | { | |
547 | int code = 0; | |
548 | unsigned long fpscr; | |
549 | ||
dc1c1ca3 | 550 | flush_fp_to_thread(current); |
dc1c1ca3 SR |
551 | |
552 | fpscr = current->thread.fpscr; | |
553 | ||
554 | /* Invalid operation */ | |
555 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
556 | code = FPE_FLTINV; | |
557 | ||
558 | /* Overflow */ | |
559 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
560 | code = FPE_FLTOVF; | |
561 | ||
562 | /* Underflow */ | |
563 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
564 | code = FPE_FLTUND; | |
565 | ||
566 | /* Divide by zero */ | |
567 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
568 | code = FPE_FLTDIV; | |
569 | ||
570 | /* Inexact result */ | |
571 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
572 | code = FPE_FLTRES; | |
573 | ||
574 | _exception(SIGFPE, regs, code, regs->nip); | |
575 | } | |
576 | ||
577 | /* | |
578 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
579 | * provide the PVR to user applications using the mfspr rd, PVR. |
580 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
581 | * memory access caused an access fault. Return zero on success. | |
582 | * | |
583 | * There are a couple of ways to do this, either "decode" the instruction | |
584 | * or directly match lots of bits. In this case, matching lots of | |
585 | * bits is faster and easier. | |
86417780 | 586 | * |
14cf11af PM |
587 | */ |
588 | #define INST_MFSPR_PVR 0x7c1f42a6 | |
589 | #define INST_MFSPR_PVR_MASK 0xfc1fffff | |
590 | ||
591 | #define INST_DCBA 0x7c0005ec | |
592 | #define INST_DCBA_MASK 0x7c0007fe | |
593 | ||
594 | #define INST_MCRXR 0x7c000400 | |
595 | #define INST_MCRXR_MASK 0x7c0007fe | |
596 | ||
597 | #define INST_STRING 0x7c00042a | |
598 | #define INST_STRING_MASK 0x7c0007fe | |
599 | #define INST_STRING_GEN_MASK 0x7c00067e | |
600 | #define INST_LSWI 0x7c0004aa | |
601 | #define INST_LSWX 0x7c00042a | |
602 | #define INST_STSWI 0x7c0005aa | |
603 | #define INST_STSWX 0x7c00052a | |
604 | ||
605 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) | |
606 | { | |
607 | u8 rT = (instword >> 21) & 0x1f; | |
608 | u8 rA = (instword >> 16) & 0x1f; | |
609 | u8 NB_RB = (instword >> 11) & 0x1f; | |
610 | u32 num_bytes; | |
611 | unsigned long EA; | |
612 | int pos = 0; | |
613 | ||
614 | /* Early out if we are an invalid form of lswx */ | |
615 | if ((instword & INST_STRING_MASK) == INST_LSWX) | |
616 | if ((rT == rA) || (rT == NB_RB)) | |
617 | return -EINVAL; | |
618 | ||
619 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
620 | ||
621 | switch (instword & INST_STRING_MASK) { | |
622 | case INST_LSWX: | |
623 | case INST_STSWX: | |
624 | EA += NB_RB; | |
625 | num_bytes = regs->xer & 0x7f; | |
626 | break; | |
627 | case INST_LSWI: | |
628 | case INST_STSWI: | |
629 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; | |
630 | break; | |
631 | default: | |
632 | return -EINVAL; | |
633 | } | |
634 | ||
635 | while (num_bytes != 0) | |
636 | { | |
637 | u8 val; | |
638 | u32 shift = 8 * (3 - (pos & 0x3)); | |
639 | ||
640 | switch ((instword & INST_STRING_MASK)) { | |
641 | case INST_LSWX: | |
642 | case INST_LSWI: | |
643 | if (get_user(val, (u8 __user *)EA)) | |
644 | return -EFAULT; | |
645 | /* first time updating this reg, | |
646 | * zero it out */ | |
647 | if (pos == 0) | |
648 | regs->gpr[rT] = 0; | |
649 | regs->gpr[rT] |= val << shift; | |
650 | break; | |
651 | case INST_STSWI: | |
652 | case INST_STSWX: | |
653 | val = regs->gpr[rT] >> shift; | |
654 | if (put_user(val, (u8 __user *)EA)) | |
655 | return -EFAULT; | |
656 | break; | |
657 | } | |
658 | /* move EA to next address */ | |
659 | EA += 1; | |
660 | num_bytes--; | |
661 | ||
662 | /* manage our position within the register */ | |
663 | if (++pos == 4) { | |
664 | pos = 0; | |
665 | if (++rT == 32) | |
666 | rT = 0; | |
667 | } | |
668 | } | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | static int emulate_instruction(struct pt_regs *regs) | |
674 | { | |
675 | u32 instword; | |
676 | u32 rd; | |
677 | ||
678 | if (!user_mode(regs)) | |
679 | return -EINVAL; | |
680 | CHECK_FULL_REGS(regs); | |
681 | ||
682 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
683 | return -EFAULT; | |
684 | ||
685 | /* Emulate the mfspr rD, PVR. */ | |
686 | if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { | |
687 | rd = (instword >> 21) & 0x1f; | |
688 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
689 | return 0; | |
690 | } | |
691 | ||
692 | /* Emulating the dcba insn is just a no-op. */ | |
8dad3f92 | 693 | if ((instword & INST_DCBA_MASK) == INST_DCBA) |
14cf11af PM |
694 | return 0; |
695 | ||
696 | /* Emulate the mcrxr insn. */ | |
697 | if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { | |
86417780 | 698 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
699 | unsigned long msk = 0xf0000000UL >> shift; |
700 | ||
701 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); | |
702 | regs->xer &= ~0xf0000000UL; | |
703 | return 0; | |
704 | } | |
705 | ||
706 | /* Emulate load/store string insn. */ | |
707 | if ((instword & INST_STRING_GEN_MASK) == INST_STRING) | |
708 | return emulate_string_inst(regs, instword); | |
709 | ||
710 | return -EINVAL; | |
711 | } | |
712 | ||
713 | /* | |
714 | * Look through the list of trap instructions that are used for BUG(), | |
715 | * BUG_ON() and WARN_ON() and see if we hit one. At this point we know | |
716 | * that the exception was caused by a trap instruction of some kind. | |
717 | * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0 | |
718 | * otherwise. | |
719 | */ | |
720 | extern struct bug_entry __start___bug_table[], __stop___bug_table[]; | |
721 | ||
722 | #ifndef CONFIG_MODULES | |
723 | #define module_find_bug(x) NULL | |
724 | #endif | |
725 | ||
726 | struct bug_entry *find_bug(unsigned long bugaddr) | |
727 | { | |
728 | struct bug_entry *bug; | |
729 | ||
730 | for (bug = __start___bug_table; bug < __stop___bug_table; ++bug) | |
731 | if (bugaddr == bug->bug_addr) | |
732 | return bug; | |
733 | return module_find_bug(bugaddr); | |
734 | } | |
735 | ||
dc1c1ca3 | 736 | static int check_bug_trap(struct pt_regs *regs) |
14cf11af PM |
737 | { |
738 | struct bug_entry *bug; | |
739 | unsigned long addr; | |
740 | ||
741 | if (regs->msr & MSR_PR) | |
742 | return 0; /* not in kernel */ | |
743 | addr = regs->nip; /* address of trap instruction */ | |
744 | if (addr < PAGE_OFFSET) | |
745 | return 0; | |
746 | bug = find_bug(regs->nip); | |
747 | if (bug == NULL) | |
748 | return 0; | |
749 | if (bug->line & BUG_WARNING_TRAP) { | |
750 | /* this is a WARN_ON rather than BUG/BUG_ON */ | |
8dad3f92 | 751 | #ifdef CONFIG_XMON |
14cf11af PM |
752 | xmon_printf(KERN_ERR "Badness in %s at %s:%d\n", |
753 | bug->function, bug->file, | |
754 | bug->line & ~BUG_WARNING_TRAP); | |
86417780 | 755 | #endif /* CONFIG_XMON */ |
14cf11af PM |
756 | printk(KERN_ERR "Badness in %s at %s:%d\n", |
757 | bug->function, bug->file, | |
758 | bug->line & ~BUG_WARNING_TRAP); | |
759 | dump_stack(); | |
760 | return 1; | |
761 | } | |
86417780 | 762 | #ifdef CONFIG_XMON |
14cf11af PM |
763 | xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n", |
764 | bug->function, bug->file, bug->line); | |
765 | xmon(regs); | |
86417780 | 766 | #endif /* CONFIG_XMON */ |
14cf11af PM |
767 | printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n", |
768 | bug->function, bug->file, bug->line); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
8dad3f92 | 773 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
774 | { |
775 | unsigned int reason = get_reason(regs); | |
776 | extern int do_mathemu(struct pt_regs *regs); | |
777 | ||
8dad3f92 | 778 | #ifdef CONFIG_MATH_EMULATION |
14cf11af PM |
779 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
780 | * but there seems to be a hardware bug on the 405GP (RevD) | |
781 | * that means ESR is sometimes set incorrectly - either to | |
782 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
783 | * hardware people - not sure if it can happen on any illegal | |
784 | * instruction or only on FP instructions, whether there is a | |
785 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
786 | if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { | |
787 | emulate_single_step(regs); | |
788 | return; | |
789 | } | |
8dad3f92 | 790 | #endif /* CONFIG_MATH_EMULATION */ |
14cf11af | 791 | |
dc1c1ca3 SR |
792 | if (reason & REASON_FP) { |
793 | /* IEEE FP exception */ | |
794 | parse_fpe(regs); | |
8dad3f92 PM |
795 | return; |
796 | } | |
797 | if (reason & REASON_TRAP) { | |
14cf11af | 798 | /* trap exception */ |
dc1c1ca3 SR |
799 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
800 | == NOTIFY_STOP) | |
801 | return; | |
14cf11af PM |
802 | if (debugger_bpt(regs)) |
803 | return; | |
804 | if (check_bug_trap(regs)) { | |
805 | regs->nip += 4; | |
806 | return; | |
807 | } | |
8dad3f92 PM |
808 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
809 | return; | |
810 | } | |
811 | ||
812 | /* Try to emulate it if we should. */ | |
813 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
814 | switch (emulate_instruction(regs)) { |
815 | case 0: | |
816 | regs->nip += 4; | |
817 | emulate_single_step(regs); | |
8dad3f92 | 818 | return; |
14cf11af PM |
819 | case -EFAULT: |
820 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 821 | return; |
14cf11af PM |
822 | } |
823 | } | |
8dad3f92 PM |
824 | |
825 | if (reason & REASON_PRIVILEGED) | |
826 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
827 | else | |
828 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
829 | } |
830 | ||
dc1c1ca3 | 831 | void alignment_exception(struct pt_regs *regs) |
14cf11af PM |
832 | { |
833 | int fixed; | |
834 | ||
835 | fixed = fix_alignment(regs); | |
836 | ||
837 | if (fixed == 1) { | |
838 | regs->nip += 4; /* skip over emulated instruction */ | |
839 | emulate_single_step(regs); | |
840 | return; | |
841 | } | |
842 | ||
dc1c1ca3 | 843 | /* Operand address was bad */ |
14cf11af PM |
844 | if (fixed == -EFAULT) { |
845 | if (user_mode(regs)) | |
8dad3f92 | 846 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar); |
14cf11af PM |
847 | else |
848 | /* Search exception table */ | |
849 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
850 | return; | |
851 | } | |
8dad3f92 | 852 | _exception(SIGBUS, regs, BUS_ADRALN, regs->dar); |
14cf11af PM |
853 | } |
854 | ||
855 | void StackOverflow(struct pt_regs *regs) | |
856 | { | |
857 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
858 | current, regs->gpr[1]); | |
859 | debugger(regs); | |
860 | show_regs(regs); | |
861 | panic("kernel stack overflow"); | |
862 | } | |
863 | ||
864 | void nonrecoverable_exception(struct pt_regs *regs) | |
865 | { | |
866 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
867 | regs->nip, regs->msr); | |
868 | debugger(regs); | |
869 | die("nonrecoverable exception", regs, SIGKILL); | |
870 | } | |
871 | ||
872 | void trace_syscall(struct pt_regs *regs) | |
873 | { | |
874 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
875 | current, current->pid, regs->nip, regs->link, regs->gpr[0], | |
876 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); | |
877 | } | |
dc1c1ca3 | 878 | |
dc1c1ca3 SR |
879 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
880 | { | |
881 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
882 | "%lx at %lx\n", regs->trap, regs->nip); | |
883 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
884 | } | |
dc1c1ca3 SR |
885 | |
886 | void altivec_unavailable_exception(struct pt_regs *regs) | |
887 | { | |
8dad3f92 | 888 | #if !defined(CONFIG_ALTIVEC) |
dc1c1ca3 SR |
889 | if (user_mode(regs)) { |
890 | /* A user program has executed an altivec instruction, | |
891 | but this kernel doesn't support altivec. */ | |
892 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
893 | return; | |
894 | } | |
895 | #endif | |
dc1c1ca3 SR |
896 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
897 | "%lx at %lx\n", regs->trap, regs->nip); | |
898 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
899 | } |
900 | ||
901 | #ifdef CONFIG_PPC64 | |
902 | extern perf_irq_t perf_irq; | |
903 | #endif | |
904 | ||
905 | #if defined(CONFIG_PPC64) || defined(CONFIG_E500) | |
906 | void performance_monitor_exception(struct pt_regs *regs) | |
907 | { | |
908 | perf_irq(regs); | |
909 | } | |
910 | #endif | |
911 | ||
8dad3f92 | 912 | #ifdef CONFIG_8xx |
14cf11af PM |
913 | void SoftwareEmulation(struct pt_regs *regs) |
914 | { | |
915 | extern int do_mathemu(struct pt_regs *); | |
916 | extern int Soft_emulate_8xx(struct pt_regs *); | |
917 | int errcode; | |
918 | ||
919 | CHECK_FULL_REGS(regs); | |
920 | ||
921 | if (!user_mode(regs)) { | |
922 | debugger(regs); | |
923 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
924 | } | |
925 | ||
926 | #ifdef CONFIG_MATH_EMULATION | |
927 | errcode = do_mathemu(regs); | |
928 | #else | |
929 | errcode = Soft_emulate_8xx(regs); | |
930 | #endif | |
931 | if (errcode) { | |
932 | if (errcode > 0) | |
933 | _exception(SIGFPE, regs, 0, 0); | |
934 | else if (errcode == -EFAULT) | |
935 | _exception(SIGSEGV, regs, 0, 0); | |
936 | else | |
937 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
938 | } else | |
939 | emulate_single_step(regs); | |
940 | } | |
8dad3f92 | 941 | #endif /* CONFIG_8xx */ |
14cf11af PM |
942 | |
943 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
944 | ||
945 | void DebugException(struct pt_regs *regs, unsigned long debug_status) | |
946 | { | |
947 | if (debug_status & DBSR_IC) { /* instruction completion */ | |
948 | regs->msr &= ~MSR_DE; | |
949 | if (user_mode(regs)) { | |
950 | current->thread.dbcr0 &= ~DBCR0_IC; | |
951 | } else { | |
952 | /* Disable instruction completion */ | |
953 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
954 | /* Clear the instruction completion event */ | |
955 | mtspr(SPRN_DBSR, DBSR_IC); | |
956 | if (debugger_sstep(regs)) | |
957 | return; | |
958 | } | |
959 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
960 | } | |
961 | } | |
962 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
963 | ||
964 | #if !defined(CONFIG_TAU_INT) | |
965 | void TAUException(struct pt_regs *regs) | |
966 | { | |
967 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
968 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
969 | } | |
970 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
971 | |
972 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 973 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
974 | { |
975 | int err; | |
976 | ||
14cf11af PM |
977 | if (!user_mode(regs)) { |
978 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
979 | " at %lx\n", regs->nip); | |
8dad3f92 | 980 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
981 | } |
982 | ||
dc1c1ca3 | 983 | flush_altivec_to_thread(current); |
dc1c1ca3 | 984 | |
14cf11af PM |
985 | err = emulate_altivec(regs); |
986 | if (err == 0) { | |
987 | regs->nip += 4; /* skip emulated instruction */ | |
988 | emulate_single_step(regs); | |
989 | return; | |
990 | } | |
991 | ||
992 | if (err == -EFAULT) { | |
993 | /* got an error reading the instruction */ | |
994 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
995 | } else { | |
996 | /* didn't recognize the instruction */ | |
997 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
998 | if (printk_ratelimit()) | |
999 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1000 | "in %s at %lx\n", current->comm, regs->nip); | |
1001 | current->thread.vscr.u[3] |= 0x10000; | |
1002 | } | |
1003 | } | |
1004 | #endif /* CONFIG_ALTIVEC */ | |
1005 | ||
14cf11af PM |
1006 | #ifdef CONFIG_FSL_BOOKE |
1007 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1008 | unsigned long error_code) | |
1009 | { | |
1010 | /* We treat cache locking instructions from the user | |
1011 | * as priv ops, in the future we could try to do | |
1012 | * something smarter | |
1013 | */ | |
1014 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1015 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1016 | return; | |
1017 | } | |
1018 | #endif /* CONFIG_FSL_BOOKE */ | |
1019 | ||
1020 | #ifdef CONFIG_SPE | |
1021 | void SPEFloatingPointException(struct pt_regs *regs) | |
1022 | { | |
1023 | unsigned long spefscr; | |
1024 | int fpexc_mode; | |
1025 | int code = 0; | |
1026 | ||
1027 | spefscr = current->thread.spefscr; | |
1028 | fpexc_mode = current->thread.fpexc_mode; | |
1029 | ||
1030 | /* Hardware does not neccessarily set sticky | |
1031 | * underflow/overflow/invalid flags */ | |
1032 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { | |
1033 | code = FPE_FLTOVF; | |
1034 | spefscr |= SPEFSCR_FOVFS; | |
1035 | } | |
1036 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1037 | code = FPE_FLTUND; | |
1038 | spefscr |= SPEFSCR_FUNFS; | |
1039 | } | |
1040 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1041 | code = FPE_FLTDIV; | |
1042 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1043 | code = FPE_FLTINV; | |
1044 | spefscr |= SPEFSCR_FINVS; | |
1045 | } | |
1046 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1047 | code = FPE_FLTRES; | |
1048 | ||
1049 | current->thread.spefscr = spefscr; | |
1050 | ||
1051 | _exception(SIGFPE, regs, code, regs->nip); | |
1052 | return; | |
1053 | } | |
1054 | #endif | |
1055 | ||
dc1c1ca3 SR |
1056 | /* |
1057 | * We enter here if we get an unrecoverable exception, that is, one | |
1058 | * that happened at a point where the RI (recoverable interrupt) bit | |
1059 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1060 | * we therefore lost state by taking this exception. | |
1061 | */ | |
1062 | void unrecoverable_exception(struct pt_regs *regs) | |
1063 | { | |
1064 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1065 | regs->trap, regs->nip); | |
1066 | die("Unrecoverable exception", regs, SIGABRT); | |
1067 | } | |
dc1c1ca3 | 1068 | |
14cf11af PM |
1069 | #ifdef CONFIG_BOOKE_WDT |
1070 | /* | |
1071 | * Default handler for a Watchdog exception, | |
1072 | * spins until a reboot occurs | |
1073 | */ | |
1074 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1075 | { | |
1076 | /* Generic WatchdogHandler, implement your own */ | |
1077 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1078 | return; | |
1079 | } | |
1080 | ||
1081 | void WatchdogException(struct pt_regs *regs) | |
1082 | { | |
1083 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1084 | WatchdogHandler(regs); | |
1085 | } | |
1086 | #endif | |
dc1c1ca3 | 1087 | |
dc1c1ca3 SR |
1088 | /* |
1089 | * We enter here if we discover during exception entry that we are | |
1090 | * running in supervisor mode with a userspace value in the stack pointer. | |
1091 | */ | |
1092 | void kernel_bad_stack(struct pt_regs *regs) | |
1093 | { | |
1094 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1095 | regs->gpr[1], regs->nip); | |
1096 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1097 | } | |
14cf11af PM |
1098 | |
1099 | void __init trap_init(void) | |
1100 | { | |
1101 | } |