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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
f0888f70 | 29 | #include <asm/kvm_book3s_asm.h> |
b4072df4 | 30 | #include <asm/mmu-hash64.h> |
de56a948 | 31 | |
7ffcf8ec AB |
32 | #ifdef __LITTLE_ENDIAN__ |
33 | #error Need to fix lppaca and SLB shadow accesses in little endian mode | |
34 | #endif | |
35 | ||
e0b7ec05 PM |
36 | /* Values in HSTATE_NAPPING(r13) */ |
37 | #define NAPPING_CEDE 1 | |
38 | #define NAPPING_NOVCPU 2 | |
39 | ||
de56a948 | 40 | /* |
19ccb76a | 41 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
42 | * Must be called with interrupts hard-disabled. |
43 | * | |
44 | * Input Registers: | |
45 | * | |
46 | * LR = return address to continue at after eventually re-enabling MMU | |
47 | */ | |
48 | _GLOBAL(kvmppc_hv_entry_trampoline) | |
218309b7 PM |
49 | mflr r0 |
50 | std r0, PPC_LR_STKOFF(r1) | |
51 | stdu r1, -112(r1) | |
de56a948 | 52 | mfmsr r10 |
218309b7 | 53 | LOAD_REG_ADDR(r5, kvmppc_call_hv_entry) |
de56a948 PM |
54 | li r0,MSR_RI |
55 | andc r0,r10,r0 | |
56 | li r6,MSR_IR | MSR_DR | |
57 | andc r6,r10,r6 | |
58 | mtmsrd r0,1 /* clear RI in MSR */ | |
59 | mtsrr0 r5 | |
60 | mtsrr1 r6 | |
61 | RFI | |
62 | ||
218309b7 | 63 | kvmppc_call_hv_entry: |
e0b7ec05 | 64 | ld r4, HSTATE_KVM_VCPU(r13) |
218309b7 PM |
65 | bl kvmppc_hv_entry |
66 | ||
67 | /* Back from guest - restore host state and return to caller */ | |
68 | ||
eee7ff9d | 69 | BEGIN_FTR_SECTION |
218309b7 PM |
70 | /* Restore host DABR and DABRX */ |
71 | ld r5,HSTATE_DABR(r13) | |
72 | li r6,7 | |
73 | mtspr SPRN_DABR,r5 | |
74 | mtspr SPRN_DABRX,r6 | |
eee7ff9d | 75 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
218309b7 PM |
76 | |
77 | /* Restore SPRG3 */ | |
78 | ld r3,PACA_SPRG3(r13) | |
79 | mtspr SPRN_SPRG3,r3 | |
80 | ||
218309b7 PM |
81 | /* Reload the host's PMU registers */ |
82 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
83 | lbz r4, LPPACA_PMCINUSE(r3) | |
84 | cmpwi r4, 0 | |
85 | beq 23f /* skip if not */ | |
86 | lwz r3, HSTATE_PMC(r13) | |
87 | lwz r4, HSTATE_PMC + 4(r13) | |
88 | lwz r5, HSTATE_PMC + 8(r13) | |
89 | lwz r6, HSTATE_PMC + 12(r13) | |
90 | lwz r8, HSTATE_PMC + 16(r13) | |
91 | lwz r9, HSTATE_PMC + 20(r13) | |
92 | BEGIN_FTR_SECTION | |
93 | lwz r10, HSTATE_PMC + 24(r13) | |
94 | lwz r11, HSTATE_PMC + 28(r13) | |
95 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
96 | mtspr SPRN_PMC1, r3 | |
97 | mtspr SPRN_PMC2, r4 | |
98 | mtspr SPRN_PMC3, r5 | |
99 | mtspr SPRN_PMC4, r6 | |
100 | mtspr SPRN_PMC5, r8 | |
101 | mtspr SPRN_PMC6, r9 | |
102 | BEGIN_FTR_SECTION | |
103 | mtspr SPRN_PMC7, r10 | |
104 | mtspr SPRN_PMC8, r11 | |
105 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
106 | ld r3, HSTATE_MMCR(r13) | |
107 | ld r4, HSTATE_MMCR + 8(r13) | |
108 | ld r5, HSTATE_MMCR + 16(r13) | |
109 | mtspr SPRN_MMCR1, r4 | |
110 | mtspr SPRN_MMCRA, r5 | |
111 | mtspr SPRN_MMCR0, r3 | |
112 | isync | |
113 | 23: | |
114 | ||
e0b7ec05 PM |
115 | /* |
116 | * Reload DEC. HDEC interrupts were disabled when | |
117 | * we reloaded the host's LPCR value. | |
118 | */ | |
119 | ld r3, HSTATE_DECEXP(r13) | |
120 | mftb r4 | |
121 | subf r4, r4, r3 | |
122 | mtspr SPRN_DEC, r4 | |
123 | ||
218309b7 PM |
124 | /* |
125 | * For external and machine check interrupts, we need | |
126 | * to call the Linux handler to process the interrupt. | |
127 | * We do that by jumping to absolute address 0x500 for | |
128 | * external interrupts, or the machine_check_fwnmi label | |
129 | * for machine checks (since firmware might have patched | |
130 | * the vector area at 0x200). The [h]rfid at the end of the | |
131 | * handler will return to the book3s_hv_interrupts.S code. | |
132 | * For other interrupts we do the rfid to get back | |
133 | * to the book3s_hv_interrupts.S code here. | |
134 | */ | |
135 | ld r8, 112+PPC_LR_STKOFF(r1) | |
136 | addi r1, r1, 112 | |
137 | ld r7, HSTATE_HOST_MSR(r13) | |
138 | ||
139 | cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
140 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
141 | BEGIN_FTR_SECTION | |
142 | beq 11f | |
143 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
144 | ||
145 | /* RFI into the highmem handler, or branch to interrupt handler */ | |
146 | mfmsr r6 | |
147 | li r0, MSR_RI | |
148 | andc r6, r6, r0 | |
149 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
150 | mtsrr0 r8 | |
151 | mtsrr1 r7 | |
152 | beqa 0x500 /* external interrupt (PPC970) */ | |
153 | beq cr1, 13f /* machine check */ | |
154 | RFI | |
155 | ||
156 | /* On POWER7, we have external interrupts set to use HSRR0/1 */ | |
157 | 11: mtspr SPRN_HSRR0, r8 | |
158 | mtspr SPRN_HSRR1, r7 | |
159 | ba 0x500 | |
160 | ||
161 | 13: b machine_check_fwnmi | |
162 | ||
de56a948 | 163 | |
e0b7ec05 PM |
164 | kvmppc_primary_no_guest: |
165 | /* We handle this much like a ceded vcpu */ | |
166 | /* set our bit in napping_threads */ | |
167 | ld r5, HSTATE_KVM_VCORE(r13) | |
168 | lbz r7, HSTATE_PTID(r13) | |
169 | li r0, 1 | |
170 | sld r0, r0, r7 | |
171 | addi r6, r5, VCORE_NAPPING_THREADS | |
172 | 1: lwarx r3, 0, r6 | |
173 | or r3, r3, r0 | |
174 | stwcx. r3, 0, r6 | |
175 | bne 1b | |
176 | /* order napping_threads update vs testing entry_exit_count */ | |
177 | isync | |
178 | li r12, 0 | |
179 | lwz r7, VCORE_ENTRY_EXIT(r5) | |
180 | cmpwi r7, 0x100 | |
181 | bge kvm_novcpu_exit /* another thread already exiting */ | |
182 | li r3, NAPPING_NOVCPU | |
183 | stb r3, HSTATE_NAPPING(r13) | |
184 | li r3, 1 | |
185 | stb r3, HSTATE_HWTHREAD_REQ(r13) | |
186 | ||
187 | b kvm_do_nap | |
188 | ||
189 | kvm_novcpu_wakeup: | |
190 | ld r1, HSTATE_HOST_R1(r13) | |
191 | ld r5, HSTATE_KVM_VCORE(r13) | |
192 | li r0, 0 | |
193 | stb r0, HSTATE_NAPPING(r13) | |
194 | stb r0, HSTATE_HWTHREAD_REQ(r13) | |
195 | ||
e3bbbbfa PM |
196 | /* check the wake reason */ |
197 | bl kvmppc_check_wake_reason | |
198 | ||
e0b7ec05 | 199 | /* see if any other thread is already exiting */ |
e0b7ec05 PM |
200 | lwz r0, VCORE_ENTRY_EXIT(r5) |
201 | cmpwi r0, 0x100 | |
202 | bge kvm_novcpu_exit | |
203 | ||
204 | /* clear our bit in napping_threads */ | |
205 | lbz r7, HSTATE_PTID(r13) | |
206 | li r0, 1 | |
207 | sld r0, r0, r7 | |
208 | addi r6, r5, VCORE_NAPPING_THREADS | |
e3bbbbfa PM |
209 | 4: lwarx r7, 0, r6 |
210 | andc r7, r7, r0 | |
211 | stwcx. r7, 0, r6 | |
e0b7ec05 PM |
212 | bne 4b |
213 | ||
e3bbbbfa | 214 | /* See if the wake reason means we need to exit */ |
e0b7ec05 PM |
215 | cmpdi r3, 0 |
216 | bge kvm_novcpu_exit | |
e0b7ec05 PM |
217 | |
218 | /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */ | |
219 | ld r4, HSTATE_KVM_VCPU(r13) | |
220 | cmpdi r4, 0 | |
221 | bne kvmppc_got_guest | |
222 | ||
223 | kvm_novcpu_exit: | |
224 | b hdec_soon | |
225 | ||
371fefd6 | 226 | /* |
e0b7ec05 | 227 | * We come in here when wakened from nap mode. |
371fefd6 PM |
228 | * Relocation is off and most register values are lost. |
229 | * r13 points to the PACA. | |
230 | */ | |
231 | .globl kvm_start_guest | |
232 | kvm_start_guest: | |
19ccb76a PM |
233 | ld r2,PACATOC(r13) |
234 | ||
f0888f70 PM |
235 | li r0,KVM_HWTHREAD_IN_KVM |
236 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
371fefd6 | 237 | |
f0888f70 PM |
238 | /* NV GPR values from power7_idle() will no longer be valid */ |
239 | li r0,1 | |
240 | stb r0,PACA_NAPSTATELOST(r13) | |
371fefd6 | 241 | |
4619ac88 PM |
242 | /* were we napping due to cede? */ |
243 | lbz r0,HSTATE_NAPPING(r13) | |
e0b7ec05 PM |
244 | cmpwi r0,NAPPING_CEDE |
245 | beq kvm_end_cede | |
246 | cmpwi r0,NAPPING_NOVCPU | |
247 | beq kvm_novcpu_wakeup | |
248 | ||
249 | ld r1,PACAEMERGSP(r13) | |
250 | subi r1,r1,STACK_FRAME_OVERHEAD | |
4619ac88 PM |
251 | |
252 | /* | |
253 | * We weren't napping due to cede, so this must be a secondary | |
254 | * thread being woken up to run a guest, or being woken up due | |
255 | * to a stray IPI. (Or due to some machine check or hypervisor | |
256 | * maintenance interrupt while the core is in KVM.) | |
257 | */ | |
f0888f70 PM |
258 | |
259 | /* Check the wake reason in SRR1 to see why we got here */ | |
e3bbbbfa PM |
260 | bl kvmppc_check_wake_reason |
261 | cmpdi r3, 0 | |
262 | bge kvm_no_guest | |
371fefd6 | 263 | |
4619ac88 | 264 | /* get vcpu pointer, NULL if we have no vcpu to run */ |
7b444c67 PM |
265 | ld r4,HSTATE_KVM_VCPU(r13) |
266 | cmpdi r4,0 | |
f0888f70 | 267 | /* if we have no vcpu to run, go back to sleep */ |
7b444c67 | 268 | beq kvm_no_guest |
f0888f70 | 269 | |
e0b7ec05 PM |
270 | /* Set HSTATE_DSCR(r13) to something sensible */ |
271 | LOAD_REG_ADDR(r6, dscr_default) | |
272 | ld r6, 0(r6) | |
273 | std r6, HSTATE_DSCR(r13) | |
274 | ||
275 | bl kvmppc_hv_entry | |
218309b7 PM |
276 | |
277 | /* Back from the guest, go back to nap */ | |
278 | /* Clear our vcpu pointer so we don't come back in early */ | |
279 | li r0, 0 | |
280 | std r0, HSTATE_KVM_VCPU(r13) | |
281 | lwsync | |
218309b7 PM |
282 | |
283 | /* increment the nap count and then go to nap mode */ | |
284 | ld r4, HSTATE_KVM_VCORE(r13) | |
285 | addi r4, r4, VCORE_NAP_COUNT | |
286 | lwsync /* make previous updates visible */ | |
287 | 51: lwarx r3, 0, r4 | |
288 | addi r3, r3, 1 | |
289 | stwcx. r3, 0, r4 | |
290 | bne 51b | |
291 | ||
292 | kvm_no_guest: | |
293 | li r0, KVM_HWTHREAD_IN_NAP | |
294 | stb r0, HSTATE_HWTHREAD_STATE(r13) | |
e0b7ec05 | 295 | kvm_do_nap: |
218309b7 PM |
296 | li r3, LPCR_PECE0 |
297 | mfspr r4, SPRN_LPCR | |
298 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 | |
299 | mtspr SPRN_LPCR, r4 | |
300 | isync | |
301 | std r0, HSTATE_SCRATCH0(r13) | |
302 | ptesync | |
303 | ld r0, HSTATE_SCRATCH0(r13) | |
304 | 1: cmpd r0, r0 | |
305 | bne 1b | |
306 | nap | |
307 | b . | |
308 | ||
309 | /****************************************************************************** | |
310 | * * | |
311 | * Entry code * | |
312 | * * | |
313 | *****************************************************************************/ | |
314 | ||
de56a948 PM |
315 | .global kvmppc_hv_entry |
316 | kvmppc_hv_entry: | |
317 | ||
318 | /* Required state: | |
319 | * | |
e0b7ec05 | 320 | * R4 = vcpu pointer (or NULL) |
de56a948 PM |
321 | * MSR = ~IR|DR |
322 | * R13 = PACA | |
323 | * R1 = host R1 | |
324 | * all other volatile GPRS = free | |
325 | */ | |
326 | mflr r0 | |
218309b7 PM |
327 | std r0, PPC_LR_STKOFF(r1) |
328 | stdu r1, -112(r1) | |
de56a948 | 329 | |
de56a948 PM |
330 | /* Save R1 in the PACA */ |
331 | std r1, HSTATE_HOST_R1(r13) | |
332 | ||
44a3add8 PM |
333 | li r6, KVM_GUEST_MODE_HOST_HV |
334 | stb r6, HSTATE_IN_GUEST(r13) | |
335 | ||
de56a948 PM |
336 | /* Clear out SLB */ |
337 | li r6,0 | |
338 | slbmte r6,r6 | |
339 | slbia | |
340 | ptesync | |
341 | ||
9e368f29 PM |
342 | BEGIN_FTR_SECTION |
343 | b 30f | |
344 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
345 | /* | |
346 | * POWER7 host -> guest partition switch code. | |
347 | * We don't have to lock against concurrent tlbies, | |
348 | * but we do have to coordinate across hardware threads. | |
349 | */ | |
371fefd6 PM |
350 | /* Increment entry count iff exit count is zero. */ |
351 | ld r5,HSTATE_KVM_VCORE(r13) | |
352 | addi r9,r5,VCORE_ENTRY_EXIT | |
353 | 21: lwarx r3,0,r9 | |
354 | cmpwi r3,0x100 /* any threads starting to exit? */ | |
355 | bge secondary_too_late /* if so we're too late to the party */ | |
356 | addi r3,r3,1 | |
357 | stwcx. r3,0,r9 | |
358 | bne 21b | |
359 | ||
360 | /* Primary thread switches to guest partition. */ | |
e0b7ec05 PM |
361 | ld r9,VCORE_KVM(r5) /* pointer to struct kvm */ |
362 | lbz r6,HSTATE_PTID(r13) | |
371fefd6 PM |
363 | cmpwi r6,0 |
364 | bne 20f | |
de56a948 PM |
365 | ld r6,KVM_SDR1(r9) |
366 | lwz r7,KVM_LPID(r9) | |
367 | li r0,LPID_RSVD /* switch to reserved LPID */ | |
368 | mtspr SPRN_LPID,r0 | |
369 | ptesync | |
370 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
371 | mtspr SPRN_LPID,r7 | |
372 | isync | |
1b400ba0 PM |
373 | |
374 | /* See if we need to flush the TLB */ | |
375 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ | |
376 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ | |
377 | srdi r6,r6,6 /* doubleword number */ | |
378 | sldi r6,r6,3 /* address offset */ | |
379 | add r6,r6,r9 | |
380 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ | |
371fefd6 | 381 | li r0,1 |
1b400ba0 PM |
382 | sld r0,r0,r7 |
383 | ld r7,0(r6) | |
384 | and. r7,r7,r0 | |
385 | beq 22f | |
386 | 23: ldarx r7,0,r6 /* if set, clear the bit */ | |
387 | andc r7,r7,r0 | |
388 | stdcx. r7,0,r6 | |
389 | bne 23b | |
ca252055 PM |
390 | /* Flush the TLB of any entries for this LPID */ |
391 | /* use arch 2.07S as a proxy for POWER8 */ | |
392 | BEGIN_FTR_SECTION | |
393 | li r6,512 /* POWER8 has 512 sets */ | |
394 | FTR_SECTION_ELSE | |
395 | li r6,128 /* POWER7 has 128 sets */ | |
396 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) | |
1b400ba0 PM |
397 | mtctr r6 |
398 | li r7,0x800 /* IS field = 0b10 */ | |
399 | ptesync | |
400 | 28: tlbiel r7 | |
401 | addi r7,r7,0x1000 | |
402 | bdnz 28b | |
403 | ptesync | |
404 | ||
93b0f4dc PM |
405 | /* Add timebase offset onto timebase */ |
406 | 22: ld r8,VCORE_TB_OFFSET(r5) | |
407 | cmpdi r8,0 | |
408 | beq 37f | |
409 | mftb r6 /* current host timebase */ | |
410 | add r8,r8,r6 | |
411 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
412 | mftb r7 /* check if lower 24 bits overflowed */ | |
413 | clrldi r6,r6,40 | |
414 | clrldi r7,r7,40 | |
415 | cmpld r7,r6 | |
416 | bge 37f | |
417 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
418 | mtspr SPRN_TBU40,r8 | |
419 | ||
388cc6e1 PM |
420 | /* Load guest PCR value to select appropriate compat mode */ |
421 | 37: ld r7, VCORE_PCR(r5) | |
422 | cmpdi r7, 0 | |
423 | beq 38f | |
424 | mtspr SPRN_PCR, r7 | |
425 | 38: | |
b005255e MN |
426 | |
427 | BEGIN_FTR_SECTION | |
428 | /* DPDES is shared between threads */ | |
429 | ld r8, VCORE_DPDES(r5) | |
430 | mtspr SPRN_DPDES, r8 | |
431 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
432 | ||
388cc6e1 | 433 | li r0,1 |
371fefd6 PM |
434 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
435 | b 10f | |
436 | ||
437 | /* Secondary threads wait for primary to have done partition switch */ | |
438 | 20: lbz r0,VCORE_IN_GUEST(r5) | |
439 | cmpwi r0,0 | |
440 | beq 20b | |
aa04b4cc | 441 | |
19ccb76a | 442 | /* Set LPCR and RMOR. */ |
a0144e2a | 443 | 10: ld r8,VCORE_LPCR(r5) |
19ccb76a | 444 | mtspr SPRN_LPCR,r8 |
aa04b4cc PM |
445 | ld r8,KVM_RMOR(r9) |
446 | mtspr SPRN_RMOR,r8 | |
de56a948 PM |
447 | isync |
448 | ||
449 | /* Check if HDEC expires soon */ | |
450 | mfspr r3,SPRN_HDEC | |
e0b7ec05 | 451 | cmpwi r3,512 /* 1 microsecond */ |
de56a948 | 452 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
de56a948 | 453 | blt hdec_soon |
9e368f29 PM |
454 | b 31f |
455 | ||
456 | /* | |
457 | * PPC970 host -> guest partition switch code. | |
458 | * We have to lock against concurrent tlbies, | |
459 | * using native_tlbie_lock to lock against host tlbies | |
460 | * and kvm->arch.tlbie_lock to lock against guest tlbies. | |
461 | * We also have to invalidate the TLB since its | |
462 | * entries aren't tagged with the LPID. | |
463 | */ | |
e0b7ec05 PM |
464 | 30: ld r5,HSTATE_KVM_VCORE(r13) |
465 | ld r9,VCORE_KVM(r5) /* pointer to struct kvm */ | |
9e368f29 PM |
466 | |
467 | /* first take native_tlbie_lock */ | |
468 | .section ".toc","aw" | |
469 | toc_tlbie_lock: | |
470 | .tc native_tlbie_lock[TC],native_tlbie_lock | |
471 | .previous | |
472 | ld r3,toc_tlbie_lock@toc(2) | |
54bb7f4b | 473 | #ifdef __BIG_ENDIAN__ |
9e368f29 | 474 | lwz r8,PACA_LOCK_TOKEN(r13) |
54bb7f4b AB |
475 | #else |
476 | lwz r8,PACAPACAINDEX(r13) | |
477 | #endif | |
9e368f29 PM |
478 | 24: lwarx r0,0,r3 |
479 | cmpwi r0,0 | |
480 | bne 24b | |
481 | stwcx. r8,0,r3 | |
482 | bne 24b | |
483 | isync | |
484 | ||
a0144e2a PM |
485 | ld r5,HSTATE_KVM_VCORE(r13) |
486 | ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */ | |
9e368f29 PM |
487 | li r0,0x18f |
488 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
489 | or r0,r7,r0 | |
490 | ptesync | |
491 | sync | |
492 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
493 | isync | |
494 | li r0,0 | |
495 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
496 | ||
497 | /* invalidate the whole TLB */ | |
498 | li r0,256 | |
499 | mtctr r0 | |
500 | li r6,0 | |
501 | 25: tlbiel r6 | |
502 | addi r6,r6,0x1000 | |
503 | bdnz 25b | |
504 | ptesync | |
505 | ||
506 | /* Take the guest's tlbie_lock */ | |
507 | addi r3,r9,KVM_TLBIE_LOCK | |
508 | 24: lwarx r0,0,r3 | |
509 | cmpwi r0,0 | |
510 | bne 24b | |
511 | stwcx. r8,0,r3 | |
512 | bne 24b | |
513 | isync | |
514 | ld r6,KVM_SDR1(r9) | |
515 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
516 | ||
517 | /* Set up HID4 with the guest's LPID etc. */ | |
518 | sync | |
519 | mtspr SPRN_HID4,r7 | |
520 | isync | |
521 | ||
522 | /* drop the guest's tlbie_lock */ | |
523 | li r0,0 | |
524 | stw r0,0(r3) | |
525 | ||
526 | /* Check if HDEC expires soon */ | |
527 | mfspr r3,SPRN_HDEC | |
528 | cmpwi r3,10 | |
529 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
9e368f29 PM |
530 | blt hdec_soon |
531 | ||
532 | /* Enable HDEC interrupts */ | |
533 | mfspr r0,SPRN_HID0 | |
534 | li r3,1 | |
535 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
536 | sync | |
537 | mtspr SPRN_HID0,r0 | |
538 | mfspr r0,SPRN_HID0 | |
539 | mfspr r0,SPRN_HID0 | |
540 | mfspr r0,SPRN_HID0 | |
541 | mfspr r0,SPRN_HID0 | |
542 | mfspr r0,SPRN_HID0 | |
543 | mfspr r0,SPRN_HID0 | |
e0b7ec05 PM |
544 | 31: |
545 | /* Do we have a guest vcpu to run? */ | |
546 | cmpdi r4, 0 | |
547 | beq kvmppc_primary_no_guest | |
548 | kvmppc_got_guest: | |
de56a948 PM |
549 | |
550 | /* Load up guest SLB entries */ | |
e0b7ec05 | 551 | lwz r5,VCPU_SLB_MAX(r4) |
de56a948 PM |
552 | cmpwi r5,0 |
553 | beq 9f | |
554 | mtctr r5 | |
555 | addi r6,r4,VCPU_SLB | |
556 | 1: ld r8,VCPU_SLB_E(r6) | |
557 | ld r9,VCPU_SLB_V(r6) | |
558 | slbmte r9,r8 | |
559 | addi r6,r6,VCPU_SLB_SIZE | |
560 | bdnz 1b | |
561 | 9: | |
e0b7ec05 PM |
562 | /* Increment yield count if they have a VPA */ |
563 | ld r3, VCPU_VPA(r4) | |
564 | cmpdi r3, 0 | |
565 | beq 25f | |
566 | lwz r5, LPPACA_YIELDCOUNT(r3) | |
567 | addi r5, r5, 1 | |
568 | stw r5, LPPACA_YIELDCOUNT(r3) | |
569 | li r6, 1 | |
570 | stb r6, VCPU_VPA_DIRTY(r4) | |
571 | 25: | |
572 | ||
573 | BEGIN_FTR_SECTION | |
574 | /* Save purr/spurr */ | |
575 | mfspr r5,SPRN_PURR | |
576 | mfspr r6,SPRN_SPURR | |
577 | std r5,HSTATE_PURR(r13) | |
578 | std r6,HSTATE_SPURR(r13) | |
579 | ld r7,VCPU_PURR(r4) | |
580 | ld r8,VCPU_SPURR(r4) | |
581 | mtspr SPRN_PURR,r7 | |
582 | mtspr SPRN_SPURR,r8 | |
583 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
584 | ||
585 | BEGIN_FTR_SECTION | |
586 | /* Set partition DABR */ | |
587 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ | |
8563bf52 | 588 | lwz r5,VCPU_DABRX(r4) |
e0b7ec05 PM |
589 | ld r6,VCPU_DABR(r4) |
590 | mtspr SPRN_DABRX,r5 | |
591 | mtspr SPRN_DABR,r6 | |
592 | BEGIN_FTR_SECTION_NESTED(89) | |
593 | isync | |
594 | END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89) | |
595 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
596 | ||
597 | /* Load guest PMU registers */ | |
598 | /* R4 is live here (vcpu pointer) */ | |
599 | li r3, 1 | |
600 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
601 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
602 | isync | |
603 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ | |
604 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
605 | lwz r6, VCPU_PMC + 8(r4) | |
606 | lwz r7, VCPU_PMC + 12(r4) | |
607 | lwz r8, VCPU_PMC + 16(r4) | |
608 | lwz r9, VCPU_PMC + 20(r4) | |
609 | BEGIN_FTR_SECTION | |
610 | lwz r10, VCPU_PMC + 24(r4) | |
611 | lwz r11, VCPU_PMC + 28(r4) | |
612 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
613 | mtspr SPRN_PMC1, r3 | |
614 | mtspr SPRN_PMC2, r5 | |
615 | mtspr SPRN_PMC3, r6 | |
616 | mtspr SPRN_PMC4, r7 | |
617 | mtspr SPRN_PMC5, r8 | |
618 | mtspr SPRN_PMC6, r9 | |
619 | BEGIN_FTR_SECTION | |
620 | mtspr SPRN_PMC7, r10 | |
621 | mtspr SPRN_PMC8, r11 | |
622 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
623 | ld r3, VCPU_MMCR(r4) | |
624 | ld r5, VCPU_MMCR + 8(r4) | |
625 | ld r6, VCPU_MMCR + 16(r4) | |
626 | ld r7, VCPU_SIAR(r4) | |
627 | ld r8, VCPU_SDAR(r4) | |
628 | mtspr SPRN_MMCR1, r5 | |
629 | mtspr SPRN_MMCRA, r6 | |
630 | mtspr SPRN_SIAR, r7 | |
631 | mtspr SPRN_SDAR, r8 | |
b005255e MN |
632 | BEGIN_FTR_SECTION |
633 | ld r5, VCPU_MMCR + 24(r4) | |
634 | ld r6, VCPU_SIER(r4) | |
635 | lwz r7, VCPU_PMC + 24(r4) | |
636 | lwz r8, VCPU_PMC + 28(r4) | |
637 | ld r9, VCPU_MMCR + 32(r4) | |
638 | mtspr SPRN_MMCR2, r5 | |
639 | mtspr SPRN_SIER, r6 | |
640 | mtspr SPRN_SPMC1, r7 | |
641 | mtspr SPRN_SPMC2, r8 | |
642 | mtspr SPRN_MMCRS, r9 | |
643 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
644 | mtspr SPRN_MMCR0, r3 |
645 | isync | |
646 | ||
647 | /* Load up FP, VMX and VSX registers */ | |
648 | bl kvmppc_load_fp | |
649 | ||
650 | ld r14, VCPU_GPR(R14)(r4) | |
651 | ld r15, VCPU_GPR(R15)(r4) | |
652 | ld r16, VCPU_GPR(R16)(r4) | |
653 | ld r17, VCPU_GPR(R17)(r4) | |
654 | ld r18, VCPU_GPR(R18)(r4) | |
655 | ld r19, VCPU_GPR(R19)(r4) | |
656 | ld r20, VCPU_GPR(R20)(r4) | |
657 | ld r21, VCPU_GPR(R21)(r4) | |
658 | ld r22, VCPU_GPR(R22)(r4) | |
659 | ld r23, VCPU_GPR(R23)(r4) | |
660 | ld r24, VCPU_GPR(R24)(r4) | |
661 | ld r25, VCPU_GPR(R25)(r4) | |
662 | ld r26, VCPU_GPR(R26)(r4) | |
663 | ld r27, VCPU_GPR(R27)(r4) | |
664 | ld r28, VCPU_GPR(R28)(r4) | |
665 | ld r29, VCPU_GPR(R29)(r4) | |
666 | ld r30, VCPU_GPR(R30)(r4) | |
667 | ld r31, VCPU_GPR(R31)(r4) | |
668 | ||
669 | BEGIN_FTR_SECTION | |
670 | /* Switch DSCR to guest value */ | |
671 | ld r5, VCPU_DSCR(r4) | |
672 | mtspr SPRN_DSCR, r5 | |
673 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
674 | ||
b005255e MN |
675 | BEGIN_FTR_SECTION |
676 | /* Skip next section on POWER7 or PPC970 */ | |
677 | b 8f | |
678 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
679 | /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */ | |
680 | mfmsr r8 | |
681 | li r0, 1 | |
682 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | |
683 | mtmsrd r8 | |
684 | ||
685 | /* Load up POWER8-specific registers */ | |
686 | ld r5, VCPU_IAMR(r4) | |
687 | lwz r6, VCPU_PSPB(r4) | |
688 | ld r7, VCPU_FSCR(r4) | |
689 | mtspr SPRN_IAMR, r5 | |
690 | mtspr SPRN_PSPB, r6 | |
691 | mtspr SPRN_FSCR, r7 | |
692 | ld r5, VCPU_DAWR(r4) | |
693 | ld r6, VCPU_DAWRX(r4) | |
694 | ld r7, VCPU_CIABR(r4) | |
695 | ld r8, VCPU_TAR(r4) | |
696 | mtspr SPRN_DAWR, r5 | |
697 | mtspr SPRN_DAWRX, r6 | |
698 | mtspr SPRN_CIABR, r7 | |
699 | mtspr SPRN_TAR, r8 | |
700 | ld r5, VCPU_IC(r4) | |
701 | ld r6, VCPU_VTB(r4) | |
702 | mtspr SPRN_IC, r5 | |
703 | mtspr SPRN_VTB, r6 | |
704 | ld r5, VCPU_TFHAR(r4) | |
705 | ld r6, VCPU_TFIAR(r4) | |
706 | ld r7, VCPU_TEXASR(r4) | |
707 | ld r8, VCPU_EBBHR(r4) | |
708 | mtspr SPRN_TFHAR, r5 | |
709 | mtspr SPRN_TFIAR, r6 | |
710 | mtspr SPRN_TEXASR, r7 | |
711 | mtspr SPRN_EBBHR, r8 | |
712 | ld r5, VCPU_EBBRR(r4) | |
713 | ld r6, VCPU_BESCR(r4) | |
714 | ld r7, VCPU_CSIGR(r4) | |
715 | ld r8, VCPU_TACR(r4) | |
716 | mtspr SPRN_EBBRR, r5 | |
717 | mtspr SPRN_BESCR, r6 | |
718 | mtspr SPRN_CSIGR, r7 | |
719 | mtspr SPRN_TACR, r8 | |
720 | ld r5, VCPU_TCSCR(r4) | |
721 | ld r6, VCPU_ACOP(r4) | |
722 | lwz r7, VCPU_GUEST_PID(r4) | |
723 | ld r8, VCPU_WORT(r4) | |
724 | mtspr SPRN_TCSCR, r5 | |
725 | mtspr SPRN_ACOP, r6 | |
726 | mtspr SPRN_PID, r7 | |
727 | mtspr SPRN_WORT, r8 | |
728 | 8: | |
729 | ||
e0b7ec05 PM |
730 | /* |
731 | * Set the decrementer to the guest decrementer. | |
732 | */ | |
733 | ld r8,VCPU_DEC_EXPIRES(r4) | |
734 | mftb r7 | |
735 | subf r3,r7,r8 | |
736 | mtspr SPRN_DEC,r3 | |
737 | stw r3,VCPU_DEC(r4) | |
738 | ||
739 | ld r5, VCPU_SPRG0(r4) | |
740 | ld r6, VCPU_SPRG1(r4) | |
741 | ld r7, VCPU_SPRG2(r4) | |
742 | ld r8, VCPU_SPRG3(r4) | |
743 | mtspr SPRN_SPRG0, r5 | |
744 | mtspr SPRN_SPRG1, r6 | |
745 | mtspr SPRN_SPRG2, r7 | |
746 | mtspr SPRN_SPRG3, r8 | |
747 | ||
748 | /* Load up DAR and DSISR */ | |
749 | ld r5, VCPU_DAR(r4) | |
750 | lwz r6, VCPU_DSISR(r4) | |
751 | mtspr SPRN_DAR, r5 | |
752 | mtspr SPRN_DSISR, r6 | |
753 | ||
754 | BEGIN_FTR_SECTION | |
755 | /* Restore AMR and UAMOR, set AMOR to all 1s */ | |
756 | ld r5,VCPU_AMR(r4) | |
757 | ld r6,VCPU_UAMOR(r4) | |
758 | li r7,-1 | |
759 | mtspr SPRN_AMR,r5 | |
760 | mtspr SPRN_UAMOR,r6 | |
761 | mtspr SPRN_AMOR,r7 | |
762 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 PM |
763 | |
764 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
765 | lwz r5,VCPU_CTRL(r4) | |
766 | andi. r5,r5,1 | |
767 | bne 4f | |
768 | mfspr r6,SPRN_CTRLF | |
769 | clrrdi r6,r6,1 | |
770 | mtspr SPRN_CTRLT,r6 | |
771 | 4: | |
772 | ld r6, VCPU_CTR(r4) | |
773 | lwz r7, VCPU_XER(r4) | |
774 | ||
775 | mtctr r6 | |
776 | mtxer r7 | |
777 | ||
e3bbbbfa | 778 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
4619ac88 PM |
779 | ld r10, VCPU_PC(r4) |
780 | ld r11, VCPU_MSR(r4) | |
de56a948 PM |
781 | ld r6, VCPU_SRR0(r4) |
782 | ld r7, VCPU_SRR1(r4) | |
e3bbbbfa PM |
783 | mtspr SPRN_SRR0, r6 |
784 | mtspr SPRN_SRR1, r7 | |
de56a948 | 785 | |
e3bbbbfa | 786 | deliver_guest_interrupt: |
4619ac88 | 787 | /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 PM |
788 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
789 | rotldi r11, r11, 1 + MSR_HV_LG | |
790 | ori r11, r11, MSR_ME | |
791 | ||
19ccb76a | 792 | /* Check if we can deliver an external or decrementer interrupt now */ |
e3bbbbfa PM |
793 | ld r0, VCPU_PENDING_EXC(r4) |
794 | rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63 | |
795 | cmpdi cr1, r0, 0 | |
796 | andi. r8, r11, MSR_EE | |
19ccb76a | 797 | BEGIN_FTR_SECTION |
e3bbbbfa PM |
798 | mfspr r8, SPRN_LPCR |
799 | /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */ | |
800 | rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH | |
801 | mtspr SPRN_LPCR, r8 | |
19ccb76a PM |
802 | isync |
803 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
804 | beq 5f | |
e3bbbbfa PM |
805 | li r0, BOOK3S_INTERRUPT_EXTERNAL |
806 | bne cr1, 12f | |
807 | mfspr r0, SPRN_DEC | |
808 | cmpwi r0, 0 | |
809 | li r0, BOOK3S_INTERRUPT_DECREMENTER | |
810 | bge 5f | |
811 | ||
812 | 12: mtspr SPRN_SRR0, r10 | |
19ccb76a | 813 | mr r10,r0 |
e3bbbbfa | 814 | mtspr SPRN_SRR1, r11 |
19ccb76a PM |
815 | li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ |
816 | rotldi r11,r11,63 | |
e3bbbbfa | 817 | 5: |
19ccb76a | 818 | |
27025a60 LPF |
819 | /* |
820 | * Required state: | |
821 | * R4 = vcpu | |
822 | * R10: value for HSRR0 | |
823 | * R11: value for HSRR1 | |
824 | * R13 = PACA | |
825 | */ | |
de56a948 | 826 | fast_guest_return: |
4619ac88 PM |
827 | li r0,0 |
828 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
de56a948 PM |
829 | mtspr SPRN_HSRR0,r10 |
830 | mtspr SPRN_HSRR1,r11 | |
831 | ||
832 | /* Activate guest mode, so faults get handled by KVM */ | |
44a3add8 | 833 | li r9, KVM_GUEST_MODE_GUEST_HV |
de56a948 PM |
834 | stb r9, HSTATE_IN_GUEST(r13) |
835 | ||
836 | /* Enter guest */ | |
837 | ||
0acb9111 PM |
838 | BEGIN_FTR_SECTION |
839 | ld r5, VCPU_CFAR(r4) | |
840 | mtspr SPRN_CFAR, r5 | |
841 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
842 | BEGIN_FTR_SECTION |
843 | ld r0, VCPU_PPR(r4) | |
844 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
0acb9111 | 845 | |
de56a948 PM |
846 | ld r5, VCPU_LR(r4) |
847 | lwz r6, VCPU_CR(r4) | |
848 | mtlr r5 | |
849 | mtcr r6 | |
850 | ||
c75df6f9 MN |
851 | ld r1, VCPU_GPR(R1)(r4) |
852 | ld r2, VCPU_GPR(R2)(r4) | |
853 | ld r3, VCPU_GPR(R3)(r4) | |
854 | ld r5, VCPU_GPR(R5)(r4) | |
855 | ld r6, VCPU_GPR(R6)(r4) | |
856 | ld r7, VCPU_GPR(R7)(r4) | |
857 | ld r8, VCPU_GPR(R8)(r4) | |
858 | ld r9, VCPU_GPR(R9)(r4) | |
859 | ld r10, VCPU_GPR(R10)(r4) | |
860 | ld r11, VCPU_GPR(R11)(r4) | |
861 | ld r12, VCPU_GPR(R12)(r4) | |
862 | ld r13, VCPU_GPR(R13)(r4) | |
863 | ||
4b8473c9 PM |
864 | BEGIN_FTR_SECTION |
865 | mtspr SPRN_PPR, r0 | |
866 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
867 | ld r0, VCPU_GPR(R0)(r4) | |
c75df6f9 | 868 | ld r4, VCPU_GPR(R4)(r4) |
de56a948 PM |
869 | |
870 | hrfid | |
871 | b . | |
872 | ||
873 | /****************************************************************************** | |
874 | * * | |
875 | * Exit code * | |
876 | * * | |
877 | *****************************************************************************/ | |
878 | ||
879 | /* | |
880 | * We come here from the first-level interrupt handlers. | |
881 | */ | |
dd96b2c2 AK |
882 | .globl kvmppc_interrupt_hv |
883 | kvmppc_interrupt_hv: | |
de56a948 PM |
884 | /* |
885 | * Register contents: | |
886 | * R12 = interrupt vector | |
887 | * R13 = PACA | |
888 | * guest CR, R12 saved in shadow VCPU SCRATCH1/0 | |
889 | * guest R13 saved in SPRN_SCRATCH0 | |
890 | */ | |
891 | /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */ | |
892 | std r9, HSTATE_HOST_R2(r13) | |
44a3add8 PM |
893 | |
894 | lbz r9, HSTATE_IN_GUEST(r13) | |
895 | cmpwi r9, KVM_GUEST_MODE_HOST_HV | |
896 | beq kvmppc_bad_host_intr | |
dd96b2c2 AK |
897 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
898 | cmpwi r9, KVM_GUEST_MODE_GUEST | |
899 | ld r9, HSTATE_HOST_R2(r13) | |
900 | beq kvmppc_interrupt_pr | |
901 | #endif | |
44a3add8 PM |
902 | /* We're now back in the host but in guest MMU context */ |
903 | li r9, KVM_GUEST_MODE_HOST_HV | |
904 | stb r9, HSTATE_IN_GUEST(r13) | |
905 | ||
de56a948 PM |
906 | ld r9, HSTATE_KVM_VCPU(r13) |
907 | ||
908 | /* Save registers */ | |
909 | ||
c75df6f9 MN |
910 | std r0, VCPU_GPR(R0)(r9) |
911 | std r1, VCPU_GPR(R1)(r9) | |
912 | std r2, VCPU_GPR(R2)(r9) | |
913 | std r3, VCPU_GPR(R3)(r9) | |
914 | std r4, VCPU_GPR(R4)(r9) | |
915 | std r5, VCPU_GPR(R5)(r9) | |
916 | std r6, VCPU_GPR(R6)(r9) | |
917 | std r7, VCPU_GPR(R7)(r9) | |
918 | std r8, VCPU_GPR(R8)(r9) | |
de56a948 | 919 | ld r0, HSTATE_HOST_R2(r13) |
c75df6f9 MN |
920 | std r0, VCPU_GPR(R9)(r9) |
921 | std r10, VCPU_GPR(R10)(r9) | |
922 | std r11, VCPU_GPR(R11)(r9) | |
de56a948 PM |
923 | ld r3, HSTATE_SCRATCH0(r13) |
924 | lwz r4, HSTATE_SCRATCH1(r13) | |
c75df6f9 | 925 | std r3, VCPU_GPR(R12)(r9) |
de56a948 | 926 | stw r4, VCPU_CR(r9) |
0acb9111 PM |
927 | BEGIN_FTR_SECTION |
928 | ld r3, HSTATE_CFAR(r13) | |
929 | std r3, VCPU_CFAR(r9) | |
930 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
931 | BEGIN_FTR_SECTION |
932 | ld r4, HSTATE_PPR(r13) | |
933 | std r4, VCPU_PPR(r9) | |
934 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
de56a948 PM |
935 | |
936 | /* Restore R1/R2 so we can handle faults */ | |
937 | ld r1, HSTATE_HOST_R1(r13) | |
938 | ld r2, PACATOC(r13) | |
939 | ||
940 | mfspr r10, SPRN_SRR0 | |
941 | mfspr r11, SPRN_SRR1 | |
942 | std r10, VCPU_SRR0(r9) | |
943 | std r11, VCPU_SRR1(r9) | |
944 | andi. r0, r12, 2 /* need to read HSRR0/1? */ | |
945 | beq 1f | |
946 | mfspr r10, SPRN_HSRR0 | |
947 | mfspr r11, SPRN_HSRR1 | |
948 | clrrdi r12, r12, 2 | |
949 | 1: std r10, VCPU_PC(r9) | |
950 | std r11, VCPU_MSR(r9) | |
951 | ||
952 | GET_SCRATCH0(r3) | |
953 | mflr r4 | |
c75df6f9 | 954 | std r3, VCPU_GPR(R13)(r9) |
de56a948 PM |
955 | std r4, VCPU_LR(r9) |
956 | ||
de56a948 PM |
957 | stw r12,VCPU_TRAP(r9) |
958 | ||
697d3899 PM |
959 | /* Save HEIR (HV emulation assist reg) in last_inst |
960 | if this is an HEI (HV emulation interrupt, e40) */ | |
961 | li r3,KVM_INST_FETCH_FAILED | |
962 | BEGIN_FTR_SECTION | |
963 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST | |
964 | bne 11f | |
965 | mfspr r3,SPRN_HEIR | |
966 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
967 | 11: stw r3,VCPU_LAST_INST(r9) | |
968 | ||
969 | /* these are volatile across C function calls */ | |
970 | mfctr r3 | |
971 | mfxer r4 | |
972 | std r3, VCPU_CTR(r9) | |
973 | stw r4, VCPU_XER(r9) | |
974 | ||
975 | BEGIN_FTR_SECTION | |
976 | /* If this is a page table miss then see if it's theirs or ours */ | |
977 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
978 | beq kvmppc_hdsi | |
342d3db7 PM |
979 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
980 | beq kvmppc_hisi | |
697d3899 PM |
981 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
982 | ||
de56a948 PM |
983 | /* See if this is a leftover HDEC interrupt */ |
984 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
985 | bne 2f | |
986 | mfspr r3,SPRN_HDEC | |
987 | cmpwi r3,0 | |
988 | bge ignore_hdec | |
989 | 2: | |
697d3899 | 990 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
991 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
992 | beq hcall_try_real_mode | |
de56a948 | 993 | |
54695c30 | 994 | /* Only handle external interrupts here on arch 206 and later */ |
9e368f29 | 995 | BEGIN_FTR_SECTION |
54695c30 BH |
996 | b ext_interrupt_to_host |
997 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) | |
998 | ||
999 | /* External interrupt ? */ | |
1000 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
1001 | bne+ ext_interrupt_to_host | |
1002 | ||
1003 | /* External interrupt, first check for host_ipi. If this is | |
1004 | * set, we know the host wants us out so let's do it now | |
1005 | */ | |
c934243c PM |
1006 | bl kvmppc_read_intr |
1007 | cmpdi r3, 0 | |
1008 | bgt ext_interrupt_to_host | |
54695c30 | 1009 | |
4619ac88 PM |
1010 | /* Check if any CPU is heading out to the host, if so head out too */ |
1011 | ld r5, HSTATE_KVM_VCORE(r13) | |
1012 | lwz r0, VCORE_ENTRY_EXIT(r5) | |
1013 | cmpwi r0, 0x100 | |
1014 | bge ext_interrupt_to_host | |
1015 | ||
e3bbbbfa PM |
1016 | /* Return to guest after delivering any pending interrupt */ |
1017 | mr r4, r9 | |
1018 | b deliver_guest_interrupt | |
54695c30 | 1019 | |
54695c30 | 1020 | ext_interrupt_to_host: |
de56a948 | 1021 | |
b4072df4 | 1022 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
de56a948 | 1023 | /* Save more register state */ |
de56a948 PM |
1024 | mfdar r6 |
1025 | mfdsisr r7 | |
de56a948 PM |
1026 | std r6, VCPU_DAR(r9) |
1027 | stw r7, VCPU_DSISR(r9) | |
9e368f29 | 1028 | BEGIN_FTR_SECTION |
697d3899 | 1029 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
de56a948 PM |
1030 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
1031 | beq 6f | |
9e368f29 | 1032 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
697d3899 | 1033 | std r6, VCPU_FAULT_DAR(r9) |
de56a948 PM |
1034 | stw r7, VCPU_FAULT_DSISR(r9) |
1035 | ||
b4072df4 PM |
1036 | /* See if it is a machine check */ |
1037 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1038 | beq machine_check_realmode | |
1039 | mc_cont: | |
1040 | ||
de56a948 | 1041 | /* Save guest CTRL register, set runlatch to 1 */ |
697d3899 | 1042 | 6: mfspr r6,SPRN_CTRLF |
de56a948 PM |
1043 | stw r6,VCPU_CTRL(r9) |
1044 | andi. r0,r6,1 | |
1045 | bne 4f | |
1046 | ori r6,r6,1 | |
1047 | mtspr SPRN_CTRLT,r6 | |
1048 | 4: | |
1049 | /* Read the guest SLB and save it away */ | |
1050 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ | |
1051 | mtctr r0 | |
1052 | li r6,0 | |
1053 | addi r7,r9,VCPU_SLB | |
1054 | li r5,0 | |
1055 | 1: slbmfee r8,r6 | |
1056 | andis. r0,r8,SLB_ESID_V@h | |
1057 | beq 2f | |
1058 | add r8,r8,r6 /* put index in */ | |
1059 | slbmfev r3,r6 | |
1060 | std r8,VCPU_SLB_E(r7) | |
1061 | std r3,VCPU_SLB_V(r7) | |
1062 | addi r7,r7,VCPU_SLB_SIZE | |
1063 | addi r5,r5,1 | |
1064 | 2: addi r6,r6,1 | |
1065 | bdnz 1b | |
1066 | stw r5,VCPU_SLB_MAX(r9) | |
1067 | ||
1068 | /* | |
1069 | * Save the guest PURR/SPURR | |
1070 | */ | |
9e368f29 | 1071 | BEGIN_FTR_SECTION |
de56a948 PM |
1072 | mfspr r5,SPRN_PURR |
1073 | mfspr r6,SPRN_SPURR | |
1074 | ld r7,VCPU_PURR(r9) | |
1075 | ld r8,VCPU_SPURR(r9) | |
1076 | std r5,VCPU_PURR(r9) | |
1077 | std r6,VCPU_SPURR(r9) | |
1078 | subf r5,r7,r5 | |
1079 | subf r6,r8,r6 | |
1080 | ||
1081 | /* | |
1082 | * Restore host PURR/SPURR and add guest times | |
1083 | * so that the time in the guest gets accounted. | |
1084 | */ | |
1085 | ld r3,HSTATE_PURR(r13) | |
1086 | ld r4,HSTATE_SPURR(r13) | |
1087 | add r3,r3,r5 | |
1088 | add r4,r4,r6 | |
1089 | mtspr SPRN_PURR,r3 | |
1090 | mtspr SPRN_SPURR,r4 | |
9e368f29 | 1091 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201) |
de56a948 | 1092 | |
e0b7ec05 PM |
1093 | /* Save DEC */ |
1094 | mfspr r5,SPRN_DEC | |
1095 | mftb r6 | |
1096 | extsw r5,r5 | |
1097 | add r5,r5,r6 | |
1098 | std r5,VCPU_DEC_EXPIRES(r9) | |
1099 | ||
b005255e MN |
1100 | BEGIN_FTR_SECTION |
1101 | b 8f | |
1102 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1103 | /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */ | |
1104 | mfmsr r8 | |
1105 | li r0, 1 | |
1106 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | |
1107 | mtmsrd r8 | |
1108 | ||
1109 | /* Save POWER8-specific registers */ | |
1110 | mfspr r5, SPRN_IAMR | |
1111 | mfspr r6, SPRN_PSPB | |
1112 | mfspr r7, SPRN_FSCR | |
1113 | std r5, VCPU_IAMR(r9) | |
1114 | stw r6, VCPU_PSPB(r9) | |
1115 | std r7, VCPU_FSCR(r9) | |
1116 | mfspr r5, SPRN_IC | |
1117 | mfspr r6, SPRN_VTB | |
1118 | mfspr r7, SPRN_TAR | |
1119 | std r5, VCPU_IC(r9) | |
1120 | std r6, VCPU_VTB(r9) | |
1121 | std r7, VCPU_TAR(r9) | |
1122 | mfspr r5, SPRN_TFHAR | |
1123 | mfspr r6, SPRN_TFIAR | |
1124 | mfspr r7, SPRN_TEXASR | |
1125 | mfspr r8, SPRN_EBBHR | |
1126 | std r5, VCPU_TFHAR(r9) | |
1127 | std r6, VCPU_TFIAR(r9) | |
1128 | std r7, VCPU_TEXASR(r9) | |
1129 | std r8, VCPU_EBBHR(r9) | |
1130 | mfspr r5, SPRN_EBBRR | |
1131 | mfspr r6, SPRN_BESCR | |
1132 | mfspr r7, SPRN_CSIGR | |
1133 | mfspr r8, SPRN_TACR | |
1134 | std r5, VCPU_EBBRR(r9) | |
1135 | std r6, VCPU_BESCR(r9) | |
1136 | std r7, VCPU_CSIGR(r9) | |
1137 | std r8, VCPU_TACR(r9) | |
1138 | mfspr r5, SPRN_TCSCR | |
1139 | mfspr r6, SPRN_ACOP | |
1140 | mfspr r7, SPRN_PID | |
1141 | mfspr r8, SPRN_WORT | |
1142 | std r5, VCPU_TCSCR(r9) | |
1143 | std r6, VCPU_ACOP(r9) | |
1144 | stw r7, VCPU_GUEST_PID(r9) | |
1145 | std r8, VCPU_WORT(r9) | |
1146 | 8: | |
1147 | ||
e0b7ec05 PM |
1148 | /* Save and reset AMR and UAMOR before turning on the MMU */ |
1149 | BEGIN_FTR_SECTION | |
1150 | mfspr r5,SPRN_AMR | |
1151 | mfspr r6,SPRN_UAMOR | |
1152 | std r5,VCPU_AMR(r9) | |
1153 | std r6,VCPU_UAMOR(r9) | |
1154 | li r6,0 | |
1155 | mtspr SPRN_AMR,r6 | |
1156 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
1157 | ||
1158 | /* Switch DSCR back to host value */ | |
1159 | BEGIN_FTR_SECTION | |
1160 | mfspr r8, SPRN_DSCR | |
1161 | ld r7, HSTATE_DSCR(r13) | |
1162 | std r8, VCPU_DSCR(r9) | |
1163 | mtspr SPRN_DSCR, r7 | |
1164 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
1165 | ||
1166 | /* Save non-volatile GPRs */ | |
1167 | std r14, VCPU_GPR(R14)(r9) | |
1168 | std r15, VCPU_GPR(R15)(r9) | |
1169 | std r16, VCPU_GPR(R16)(r9) | |
1170 | std r17, VCPU_GPR(R17)(r9) | |
1171 | std r18, VCPU_GPR(R18)(r9) | |
1172 | std r19, VCPU_GPR(R19)(r9) | |
1173 | std r20, VCPU_GPR(R20)(r9) | |
1174 | std r21, VCPU_GPR(R21)(r9) | |
1175 | std r22, VCPU_GPR(R22)(r9) | |
1176 | std r23, VCPU_GPR(R23)(r9) | |
1177 | std r24, VCPU_GPR(R24)(r9) | |
1178 | std r25, VCPU_GPR(R25)(r9) | |
1179 | std r26, VCPU_GPR(R26)(r9) | |
1180 | std r27, VCPU_GPR(R27)(r9) | |
1181 | std r28, VCPU_GPR(R28)(r9) | |
1182 | std r29, VCPU_GPR(R29)(r9) | |
1183 | std r30, VCPU_GPR(R30)(r9) | |
1184 | std r31, VCPU_GPR(R31)(r9) | |
1185 | ||
1186 | /* Save SPRGs */ | |
1187 | mfspr r3, SPRN_SPRG0 | |
1188 | mfspr r4, SPRN_SPRG1 | |
1189 | mfspr r5, SPRN_SPRG2 | |
1190 | mfspr r6, SPRN_SPRG3 | |
1191 | std r3, VCPU_SPRG0(r9) | |
1192 | std r4, VCPU_SPRG1(r9) | |
1193 | std r5, VCPU_SPRG2(r9) | |
1194 | std r6, VCPU_SPRG3(r9) | |
1195 | ||
1196 | /* save FP state */ | |
1197 | mr r3, r9 | |
1198 | bl kvmppc_save_fp | |
1199 | ||
1200 | /* Increment yield count if they have a VPA */ | |
1201 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
1202 | cmpdi r8, 0 | |
1203 | beq 25f | |
1204 | lwz r3, LPPACA_YIELDCOUNT(r8) | |
1205 | addi r3, r3, 1 | |
1206 | stw r3, LPPACA_YIELDCOUNT(r8) | |
1207 | li r3, 1 | |
1208 | stb r3, VCPU_VPA_DIRTY(r9) | |
1209 | 25: | |
1210 | /* Save PMU registers if requested */ | |
1211 | /* r8 and cr0.eq are live here */ | |
1212 | li r3, 1 | |
1213 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
1214 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
1215 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
1216 | mfspr r6, SPRN_MMCRA | |
1217 | BEGIN_FTR_SECTION | |
1218 | /* On P7, clear MMCRA in order to disable SDAR updates */ | |
1219 | li r7, 0 | |
1220 | mtspr SPRN_MMCRA, r7 | |
1221 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
1222 | isync | |
1223 | beq 21f /* if no VPA, save PMU stuff anyway */ | |
1224 | lbz r7, LPPACA_PMCINUSE(r8) | |
1225 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
1226 | bne 21f | |
1227 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
1228 | b 22f | |
1229 | 21: mfspr r5, SPRN_MMCR1 | |
1230 | mfspr r7, SPRN_SIAR | |
1231 | mfspr r8, SPRN_SDAR | |
1232 | std r4, VCPU_MMCR(r9) | |
1233 | std r5, VCPU_MMCR + 8(r9) | |
1234 | std r6, VCPU_MMCR + 16(r9) | |
1235 | std r7, VCPU_SIAR(r9) | |
1236 | std r8, VCPU_SDAR(r9) | |
1237 | mfspr r3, SPRN_PMC1 | |
1238 | mfspr r4, SPRN_PMC2 | |
1239 | mfspr r5, SPRN_PMC3 | |
1240 | mfspr r6, SPRN_PMC4 | |
1241 | mfspr r7, SPRN_PMC5 | |
1242 | mfspr r8, SPRN_PMC6 | |
1243 | BEGIN_FTR_SECTION | |
1244 | mfspr r10, SPRN_PMC7 | |
1245 | mfspr r11, SPRN_PMC8 | |
1246 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
1247 | stw r3, VCPU_PMC(r9) | |
1248 | stw r4, VCPU_PMC + 4(r9) | |
1249 | stw r5, VCPU_PMC + 8(r9) | |
1250 | stw r6, VCPU_PMC + 12(r9) | |
1251 | stw r7, VCPU_PMC + 16(r9) | |
1252 | stw r8, VCPU_PMC + 20(r9) | |
1253 | BEGIN_FTR_SECTION | |
1254 | stw r10, VCPU_PMC + 24(r9) | |
1255 | stw r11, VCPU_PMC + 28(r9) | |
1256 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
b005255e MN |
1257 | BEGIN_FTR_SECTION |
1258 | mfspr r4, SPRN_MMCR2 | |
1259 | mfspr r5, SPRN_SIER | |
1260 | mfspr r6, SPRN_SPMC1 | |
1261 | mfspr r7, SPRN_SPMC2 | |
1262 | mfspr r8, SPRN_MMCRS | |
1263 | std r4, VCPU_MMCR + 24(r9) | |
1264 | std r5, VCPU_SIER(r9) | |
1265 | stw r6, VCPU_PMC + 24(r9) | |
1266 | stw r7, VCPU_PMC + 28(r9) | |
1267 | std r8, VCPU_MMCR + 32(r9) | |
1268 | lis r4, 0x8000 | |
1269 | mtspr SPRN_MMCRS, r4 | |
1270 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 | 1271 | 22: |
de56a948 PM |
1272 | /* Clear out SLB */ |
1273 | li r5,0 | |
1274 | slbmte r5,r5 | |
1275 | slbia | |
1276 | ptesync | |
1277 | ||
e0b7ec05 | 1278 | hdec_soon: /* r12 = trap, r13 = paca */ |
9e368f29 PM |
1279 | BEGIN_FTR_SECTION |
1280 | b 32f | |
1281 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
1282 | /* | |
1283 | * POWER7 guest -> host partition switch code. | |
1284 | * We don't have to lock against tlbies but we do | |
1285 | * have to coordinate the hardware threads. | |
1286 | */ | |
371fefd6 PM |
1287 | /* Increment the threads-exiting-guest count in the 0xff00 |
1288 | bits of vcore->entry_exit_count */ | |
1289 | lwsync | |
1290 | ld r5,HSTATE_KVM_VCORE(r13) | |
1291 | addi r6,r5,VCORE_ENTRY_EXIT | |
1292 | 41: lwarx r3,0,r6 | |
1293 | addi r0,r3,0x100 | |
1294 | stwcx. r0,0,r6 | |
1295 | bne 41b | |
19ccb76a | 1296 | lwsync |
371fefd6 PM |
1297 | |
1298 | /* | |
1299 | * At this point we have an interrupt that we have to pass | |
1300 | * up to the kernel or qemu; we can't handle it in real mode. | |
1301 | * Thus we have to do a partition switch, so we have to | |
1302 | * collect the other threads, if we are the first thread | |
1303 | * to take an interrupt. To do this, we set the HDEC to 0, | |
1304 | * which causes an HDEC interrupt in all threads within 2ns | |
1305 | * because the HDEC register is shared between all 4 threads. | |
1306 | * However, we don't need to bother if this is an HDEC | |
1307 | * interrupt, since the other threads will already be on their | |
1308 | * way here in that case. | |
1309 | */ | |
19ccb76a PM |
1310 | cmpwi r3,0x100 /* Are we the first here? */ |
1311 | bge 43f | |
371fefd6 PM |
1312 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
1313 | beq 40f | |
371fefd6 PM |
1314 | li r0,0 |
1315 | mtspr SPRN_HDEC,r0 | |
1316 | 40: | |
19ccb76a PM |
1317 | /* |
1318 | * Send an IPI to any napping threads, since an HDEC interrupt | |
1319 | * doesn't wake CPUs up from nap. | |
1320 | */ | |
1321 | lwz r3,VCORE_NAPPING_THREADS(r5) | |
e0b7ec05 | 1322 | lbz r4,HSTATE_PTID(r13) |
19ccb76a | 1323 | li r0,1 |
2f584a14 | 1324 | sld r0,r0,r4 |
19ccb76a PM |
1325 | andc. r3,r3,r0 /* no sense IPI'ing ourselves */ |
1326 | beq 43f | |
1327 | mulli r4,r4,PACA_SIZE /* get paca for thread 0 */ | |
1328 | subf r6,r4,r13 | |
1329 | 42: andi. r0,r3,1 | |
1330 | beq 44f | |
1331 | ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */ | |
1332 | li r0,IPI_PRIORITY | |
54695c30 | 1333 | li r7,XICS_MFRR |
19ccb76a PM |
1334 | stbcix r0,r7,r8 /* trigger the IPI */ |
1335 | 44: srdi. r3,r3,1 | |
1336 | addi r6,r6,PACA_SIZE | |
1337 | bne 42b | |
371fefd6 | 1338 | |
e0b7ec05 | 1339 | secondary_too_late: |
371fefd6 | 1340 | /* Secondary threads wait for primary to do partition switch */ |
e0b7ec05 PM |
1341 | 43: ld r5,HSTATE_KVM_VCORE(r13) |
1342 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ | |
1343 | lbz r3,HSTATE_PTID(r13) | |
371fefd6 PM |
1344 | cmpwi r3,0 |
1345 | beq 15f | |
1346 | HMT_LOW | |
1347 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1348 | cmpwi r3,0 | |
1349 | bne 13b | |
1350 | HMT_MEDIUM | |
1351 | b 16f | |
1352 | ||
1353 | /* Primary thread waits for all the secondaries to exit guest */ | |
1354 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
1355 | srwi r0,r3,8 | |
1356 | clrldi r3,r3,56 | |
1357 | cmpw r3,r0 | |
1358 | bne 15b | |
1359 | isync | |
1360 | ||
1361 | /* Primary thread switches back to host partition */ | |
de56a948 PM |
1362 | ld r6,KVM_HOST_SDR1(r4) |
1363 | lwz r7,KVM_HOST_LPID(r4) | |
1364 | li r8,LPID_RSVD /* switch to reserved LPID */ | |
1365 | mtspr SPRN_LPID,r8 | |
1366 | ptesync | |
1367 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
1368 | mtspr SPRN_LPID,r7 | |
1369 | isync | |
93b0f4dc | 1370 | |
b005255e MN |
1371 | BEGIN_FTR_SECTION |
1372 | /* DPDES is shared between threads */ | |
1373 | mfspr r7, SPRN_DPDES | |
1374 | std r7, VCORE_DPDES(r5) | |
1375 | /* clear DPDES so we don't get guest doorbells in the host */ | |
1376 | li r8, 0 | |
1377 | mtspr SPRN_DPDES, r8 | |
1378 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
1379 | ||
93b0f4dc PM |
1380 | /* Subtract timebase offset from timebase */ |
1381 | ld r8,VCORE_TB_OFFSET(r5) | |
1382 | cmpdi r8,0 | |
1383 | beq 17f | |
1384 | mftb r6 /* current host timebase */ | |
1385 | subf r8,r8,r6 | |
1386 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
1387 | mftb r7 /* check if lower 24 bits overflowed */ | |
1388 | clrldi r6,r6,40 | |
1389 | clrldi r7,r7,40 | |
1390 | cmpld r7,r6 | |
1391 | bge 17f | |
1392 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
1393 | mtspr SPRN_TBU40,r8 | |
1394 | ||
388cc6e1 PM |
1395 | /* Reset PCR */ |
1396 | 17: ld r0, VCORE_PCR(r5) | |
1397 | cmpdi r0, 0 | |
1398 | beq 18f | |
1399 | li r0, 0 | |
1400 | mtspr SPRN_PCR, r0 | |
1401 | 18: | |
93b0f4dc | 1402 | /* Signal secondary CPUs to continue */ |
371fefd6 | 1403 | stb r0,VCORE_IN_GUEST(r5) |
de56a948 PM |
1404 | lis r8,0x7fff /* MAX_INT@h */ |
1405 | mtspr SPRN_HDEC,r8 | |
1406 | ||
371fefd6 | 1407 | 16: ld r8,KVM_HOST_LPCR(r4) |
de56a948 PM |
1408 | mtspr SPRN_LPCR,r8 |
1409 | isync | |
9e368f29 PM |
1410 | b 33f |
1411 | ||
1412 | /* | |
1413 | * PPC970 guest -> host partition switch code. | |
1414 | * We have to lock against concurrent tlbies, and | |
1415 | * we have to flush the whole TLB. | |
1416 | */ | |
e0b7ec05 PM |
1417 | 32: ld r5,HSTATE_KVM_VCORE(r13) |
1418 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ | |
9e368f29 PM |
1419 | |
1420 | /* Take the guest's tlbie_lock */ | |
54bb7f4b | 1421 | #ifdef __BIG_ENDIAN__ |
9e368f29 | 1422 | lwz r8,PACA_LOCK_TOKEN(r13) |
54bb7f4b AB |
1423 | #else |
1424 | lwz r8,PACAPACAINDEX(r13) | |
1425 | #endif | |
9e368f29 PM |
1426 | addi r3,r4,KVM_TLBIE_LOCK |
1427 | 24: lwarx r0,0,r3 | |
1428 | cmpwi r0,0 | |
1429 | bne 24b | |
1430 | stwcx. r8,0,r3 | |
1431 | bne 24b | |
1432 | isync | |
1433 | ||
1434 | ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */ | |
1435 | li r0,0x18f | |
1436 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
1437 | or r0,r7,r0 | |
1438 | ptesync | |
1439 | sync | |
1440 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
1441 | isync | |
1442 | li r0,0 | |
1443 | stw r0,0(r3) /* drop guest tlbie_lock */ | |
1444 | ||
1445 | /* invalidate the whole TLB */ | |
1446 | li r0,256 | |
1447 | mtctr r0 | |
1448 | li r6,0 | |
1449 | 25: tlbiel r6 | |
1450 | addi r6,r6,0x1000 | |
1451 | bdnz 25b | |
1452 | ptesync | |
1453 | ||
1454 | /* take native_tlbie_lock */ | |
1455 | ld r3,toc_tlbie_lock@toc(2) | |
1456 | 24: lwarx r0,0,r3 | |
1457 | cmpwi r0,0 | |
1458 | bne 24b | |
1459 | stwcx. r8,0,r3 | |
1460 | bne 24b | |
1461 | isync | |
1462 | ||
1463 | ld r6,KVM_HOST_SDR1(r4) | |
1464 | mtspr SPRN_SDR1,r6 /* switch to host page table */ | |
1465 | ||
1466 | /* Set up host HID4 value */ | |
1467 | sync | |
1468 | mtspr SPRN_HID4,r7 | |
1469 | isync | |
1470 | li r0,0 | |
1471 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
1472 | ||
1473 | lis r8,0x7fff /* MAX_INT@h */ | |
1474 | mtspr SPRN_HDEC,r8 | |
1475 | ||
1476 | /* Disable HDEC interrupts */ | |
1477 | mfspr r0,SPRN_HID0 | |
1478 | li r3,0 | |
1479 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
1480 | sync | |
1481 | mtspr SPRN_HID0,r0 | |
1482 | mfspr r0,SPRN_HID0 | |
1483 | mfspr r0,SPRN_HID0 | |
1484 | mfspr r0,SPRN_HID0 | |
1485 | mfspr r0,SPRN_HID0 | |
1486 | mfspr r0,SPRN_HID0 | |
1487 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
1488 | |
1489 | /* load host SLB entries */ | |
9e368f29 | 1490 | 33: ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
1491 | |
1492 | .rept SLB_NUM_BOLTED | |
1493 | ld r5,SLBSHADOW_SAVEAREA(r8) | |
1494 | ld r6,SLBSHADOW_SAVEAREA+8(r8) | |
1495 | andis. r7,r5,SLB_ESID_V@h | |
1496 | beq 1f | |
1497 | slbmte r6,r5 | |
1498 | 1: addi r8,r8,16 | |
1499 | .endr | |
1500 | ||
44a3add8 PM |
1501 | /* Unset guest mode */ |
1502 | li r0, KVM_GUEST_MODE_NONE | |
1503 | stb r0, HSTATE_IN_GUEST(r13) | |
1504 | ||
218309b7 PM |
1505 | ld r0, 112+PPC_LR_STKOFF(r1) |
1506 | addi r1, r1, 112 | |
1507 | mtlr r0 | |
1508 | blr | |
b4072df4 | 1509 | |
697d3899 PM |
1510 | /* |
1511 | * Check whether an HDSI is an HPTE not found fault or something else. | |
1512 | * If it is an HPTE not found fault that is due to the guest accessing | |
1513 | * a page that they have mapped but which we have paged out, then | |
1514 | * we continue on with the guest exit path. In all other cases, | |
1515 | * reflect the HDSI to the guest as a DSI. | |
1516 | */ | |
1517 | kvmppc_hdsi: | |
1518 | mfspr r4, SPRN_HDAR | |
1519 | mfspr r6, SPRN_HDSISR | |
4cf302bc PM |
1520 | /* HPTE not found fault or protection fault? */ |
1521 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h | |
697d3899 PM |
1522 | beq 1f /* if not, send it to the guest */ |
1523 | andi. r0, r11, MSR_DR /* data relocation enabled? */ | |
1524 | beq 3f | |
1525 | clrrdi r0, r4, 28 | |
c75df6f9 | 1526 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
697d3899 PM |
1527 | bne 1f /* if no SLB entry found */ |
1528 | 4: std r4, VCPU_FAULT_DAR(r9) | |
1529 | stw r6, VCPU_FAULT_DSISR(r9) | |
1530 | ||
1531 | /* Search the hash table. */ | |
1532 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 1533 | li r7, 1 /* data fault */ |
697d3899 PM |
1534 | bl .kvmppc_hpte_hv_fault |
1535 | ld r9, HSTATE_KVM_VCPU(r13) | |
1536 | ld r10, VCPU_PC(r9) | |
1537 | ld r11, VCPU_MSR(r9) | |
1538 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1539 | cmpdi r3, 0 /* retry the instruction */ | |
1540 | beq 6f | |
1541 | cmpdi r3, -1 /* handle in kernel mode */ | |
b4072df4 | 1542 | beq guest_exit_cont |
697d3899 PM |
1543 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
1544 | beq 2f | |
1545 | ||
1546 | /* Synthesize a DSI for the guest */ | |
1547 | ld r4, VCPU_FAULT_DAR(r9) | |
1548 | mr r6, r3 | |
1549 | 1: mtspr SPRN_DAR, r4 | |
1550 | mtspr SPRN_DSISR, r6 | |
1551 | mtspr SPRN_SRR0, r10 | |
1552 | mtspr SPRN_SRR1, r11 | |
1553 | li r10, BOOK3S_INTERRUPT_DATA_STORAGE | |
1554 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1555 | rotldi r11, r11, 63 | |
b4072df4 | 1556 | fast_interrupt_c_return: |
697d3899 PM |
1557 | 6: ld r7, VCPU_CTR(r9) |
1558 | lwz r8, VCPU_XER(r9) | |
1559 | mtctr r7 | |
1560 | mtxer r8 | |
1561 | mr r4, r9 | |
1562 | b fast_guest_return | |
1563 | ||
1564 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1565 | ld r5, KVM_VRMA_SLB_V(r5) | |
1566 | b 4b | |
1567 | ||
1568 | /* If this is for emulated MMIO, load the instruction word */ | |
1569 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
1570 | ||
1571 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
1572 | * we'll just continue at the next IP. */ | |
1573 | li r0, KVM_GUEST_MODE_SKIP | |
1574 | stb r0, HSTATE_IN_GUEST(r13) | |
1575 | ||
1576 | /* Do the access with MSR:DR enabled */ | |
1577 | mfmsr r3 | |
1578 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
1579 | mtmsrd r4 | |
1580 | lwz r8, 0(r10) | |
1581 | mtmsrd r3 | |
1582 | ||
1583 | /* Store the result */ | |
1584 | stw r8, VCPU_LAST_INST(r9) | |
1585 | ||
1586 | /* Unset guest mode. */ | |
44a3add8 | 1587 | li r0, KVM_GUEST_MODE_HOST_HV |
697d3899 | 1588 | stb r0, HSTATE_IN_GUEST(r13) |
b4072df4 | 1589 | b guest_exit_cont |
de56a948 | 1590 | |
342d3db7 PM |
1591 | /* |
1592 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
1593 | * it is an HPTE not found fault for a page that we have paged out. | |
1594 | */ | |
1595 | kvmppc_hisi: | |
1596 | andis. r0, r11, SRR1_ISI_NOPT@h | |
1597 | beq 1f | |
1598 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ | |
1599 | beq 3f | |
1600 | clrrdi r0, r10, 28 | |
c75df6f9 | 1601 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
342d3db7 PM |
1602 | bne 1f /* if no SLB entry found */ |
1603 | 4: | |
1604 | /* Search the hash table. */ | |
1605 | mr r3, r9 /* vcpu pointer */ | |
1606 | mr r4, r10 | |
1607 | mr r6, r11 | |
1608 | li r7, 0 /* instruction fault */ | |
1609 | bl .kvmppc_hpte_hv_fault | |
1610 | ld r9, HSTATE_KVM_VCPU(r13) | |
1611 | ld r10, VCPU_PC(r9) | |
1612 | ld r11, VCPU_MSR(r9) | |
1613 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
1614 | cmpdi r3, 0 /* retry the instruction */ | |
b4072df4 | 1615 | beq fast_interrupt_c_return |
342d3db7 | 1616 | cmpdi r3, -1 /* handle in kernel mode */ |
b4072df4 | 1617 | beq guest_exit_cont |
342d3db7 PM |
1618 | |
1619 | /* Synthesize an ISI for the guest */ | |
1620 | mr r11, r3 | |
1621 | 1: mtspr SPRN_SRR0, r10 | |
1622 | mtspr SPRN_SRR1, r11 | |
1623 | li r10, BOOK3S_INTERRUPT_INST_STORAGE | |
1624 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1625 | rotldi r11, r11, 63 | |
b4072df4 | 1626 | b fast_interrupt_c_return |
342d3db7 PM |
1627 | |
1628 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1629 | ld r5, KVM_VRMA_SLB_V(r6) | |
1630 | b 4b | |
1631 | ||
a8606e20 PM |
1632 | /* |
1633 | * Try to handle an hcall in real mode. | |
1634 | * Returns to the guest if we handle it, or continues on up to | |
1635 | * the kernel if we can't (i.e. if we don't have a handler for | |
1636 | * it, or if the handler returns H_TOO_HARD). | |
1637 | */ | |
1638 | .globl hcall_try_real_mode | |
1639 | hcall_try_real_mode: | |
c75df6f9 | 1640 | ld r3,VCPU_GPR(R3)(r9) |
a8606e20 | 1641 | andi. r0,r11,MSR_PR |
27025a60 LPF |
1642 | /* sc 1 from userspace - reflect to guest syscall */ |
1643 | bne sc_1_fast_return | |
a8606e20 PM |
1644 | clrrdi r3,r3,2 |
1645 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
b4072df4 | 1646 | bge guest_exit_cont |
a8606e20 | 1647 | LOAD_REG_ADDR(r4, hcall_real_table) |
4baa1d87 | 1648 | lwax r3,r3,r4 |
a8606e20 | 1649 | cmpwi r3,0 |
b4072df4 | 1650 | beq guest_exit_cont |
a8606e20 PM |
1651 | add r3,r3,r4 |
1652 | mtctr r3 | |
1653 | mr r3,r9 /* get vcpu pointer */ | |
c75df6f9 | 1654 | ld r4,VCPU_GPR(R4)(r9) |
a8606e20 PM |
1655 | bctrl |
1656 | cmpdi r3,H_TOO_HARD | |
1657 | beq hcall_real_fallback | |
1658 | ld r4,HSTATE_KVM_VCPU(r13) | |
c75df6f9 | 1659 | std r3,VCPU_GPR(R3)(r4) |
a8606e20 PM |
1660 | ld r10,VCPU_PC(r4) |
1661 | ld r11,VCPU_MSR(r4) | |
1662 | b fast_guest_return | |
1663 | ||
27025a60 LPF |
1664 | sc_1_fast_return: |
1665 | mtspr SPRN_SRR0,r10 | |
1666 | mtspr SPRN_SRR1,r11 | |
1667 | li r10, BOOK3S_INTERRUPT_SYSCALL | |
1668 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1669 | rotldi r11, r11, 63 | |
1670 | mr r4,r9 | |
1671 | b fast_guest_return | |
1672 | ||
a8606e20 PM |
1673 | /* We've attempted a real mode hcall, but it's punted it back |
1674 | * to userspace. We need to restore some clobbered volatiles | |
1675 | * before resuming the pass-it-to-qemu path */ | |
1676 | hcall_real_fallback: | |
1677 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
1678 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 | 1679 | |
b4072df4 | 1680 | b guest_exit_cont |
a8606e20 PM |
1681 | |
1682 | .globl hcall_real_table | |
1683 | hcall_real_table: | |
1684 | .long 0 /* 0 - unused */ | |
1685 | .long .kvmppc_h_remove - hcall_real_table | |
1686 | .long .kvmppc_h_enter - hcall_real_table | |
1687 | .long .kvmppc_h_read - hcall_real_table | |
1688 | .long 0 /* 0x10 - H_CLEAR_MOD */ | |
1689 | .long 0 /* 0x14 - H_CLEAR_REF */ | |
1690 | .long .kvmppc_h_protect - hcall_real_table | |
1691 | .long 0 /* 0x1c - H_GET_TCE */ | |
54738c09 | 1692 | .long .kvmppc_h_put_tce - hcall_real_table |
a8606e20 PM |
1693 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
1694 | .long .kvmppc_h_set_dabr - hcall_real_table | |
1695 | .long 0 /* 0x2c */ | |
1696 | .long 0 /* 0x30 */ | |
1697 | .long 0 /* 0x34 */ | |
1698 | .long 0 /* 0x38 */ | |
1699 | .long 0 /* 0x3c */ | |
1700 | .long 0 /* 0x40 */ | |
1701 | .long 0 /* 0x44 */ | |
1702 | .long 0 /* 0x48 */ | |
1703 | .long 0 /* 0x4c */ | |
1704 | .long 0 /* 0x50 */ | |
1705 | .long 0 /* 0x54 */ | |
1706 | .long 0 /* 0x58 */ | |
1707 | .long 0 /* 0x5c */ | |
1708 | .long 0 /* 0x60 */ | |
e7d26f28 BH |
1709 | #ifdef CONFIG_KVM_XICS |
1710 | .long .kvmppc_rm_h_eoi - hcall_real_table | |
1711 | .long .kvmppc_rm_h_cppr - hcall_real_table | |
1712 | .long .kvmppc_rm_h_ipi - hcall_real_table | |
1713 | .long 0 /* 0x70 - H_IPOLL */ | |
1714 | .long .kvmppc_rm_h_xirr - hcall_real_table | |
1715 | #else | |
1716 | .long 0 /* 0x64 - H_EOI */ | |
1717 | .long 0 /* 0x68 - H_CPPR */ | |
1718 | .long 0 /* 0x6c - H_IPI */ | |
1719 | .long 0 /* 0x70 - H_IPOLL */ | |
1720 | .long 0 /* 0x74 - H_XIRR */ | |
1721 | #endif | |
a8606e20 PM |
1722 | .long 0 /* 0x78 */ |
1723 | .long 0 /* 0x7c */ | |
1724 | .long 0 /* 0x80 */ | |
1725 | .long 0 /* 0x84 */ | |
1726 | .long 0 /* 0x88 */ | |
1727 | .long 0 /* 0x8c */ | |
1728 | .long 0 /* 0x90 */ | |
1729 | .long 0 /* 0x94 */ | |
1730 | .long 0 /* 0x98 */ | |
1731 | .long 0 /* 0x9c */ | |
1732 | .long 0 /* 0xa0 */ | |
1733 | .long 0 /* 0xa4 */ | |
1734 | .long 0 /* 0xa8 */ | |
1735 | .long 0 /* 0xac */ | |
1736 | .long 0 /* 0xb0 */ | |
1737 | .long 0 /* 0xb4 */ | |
1738 | .long 0 /* 0xb8 */ | |
1739 | .long 0 /* 0xbc */ | |
1740 | .long 0 /* 0xc0 */ | |
1741 | .long 0 /* 0xc4 */ | |
1742 | .long 0 /* 0xc8 */ | |
1743 | .long 0 /* 0xcc */ | |
1744 | .long 0 /* 0xd0 */ | |
1745 | .long 0 /* 0xd4 */ | |
1746 | .long 0 /* 0xd8 */ | |
1747 | .long 0 /* 0xdc */ | |
19ccb76a | 1748 | .long .kvmppc_h_cede - hcall_real_table |
a8606e20 PM |
1749 | .long 0 /* 0xe4 */ |
1750 | .long 0 /* 0xe8 */ | |
1751 | .long 0 /* 0xec */ | |
1752 | .long 0 /* 0xf0 */ | |
1753 | .long 0 /* 0xf4 */ | |
1754 | .long 0 /* 0xf8 */ | |
1755 | .long 0 /* 0xfc */ | |
1756 | .long 0 /* 0x100 */ | |
1757 | .long 0 /* 0x104 */ | |
1758 | .long 0 /* 0x108 */ | |
1759 | .long 0 /* 0x10c */ | |
1760 | .long 0 /* 0x110 */ | |
1761 | .long 0 /* 0x114 */ | |
1762 | .long 0 /* 0x118 */ | |
1763 | .long 0 /* 0x11c */ | |
1764 | .long 0 /* 0x120 */ | |
1765 | .long .kvmppc_h_bulk_remove - hcall_real_table | |
8563bf52 PM |
1766 | .long 0 /* 0x128 */ |
1767 | .long 0 /* 0x12c */ | |
1768 | .long 0 /* 0x130 */ | |
1769 | .long .kvmppc_h_set_xdabr - hcall_real_table | |
a8606e20 PM |
1770 | hcall_real_table_end: |
1771 | ||
de56a948 PM |
1772 | ignore_hdec: |
1773 | mr r4,r9 | |
1774 | b fast_guest_return | |
1775 | ||
8563bf52 PM |
1776 | _GLOBAL(kvmppc_h_set_xdabr) |
1777 | andi. r0, r5, DABRX_USER | DABRX_KERNEL | |
1778 | beq 6f | |
1779 | li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI | |
1780 | andc. r0, r5, r0 | |
1781 | beq 3f | |
1782 | 6: li r3, H_PARAMETER | |
1783 | blr | |
1784 | ||
a8606e20 | 1785 | _GLOBAL(kvmppc_h_set_dabr) |
8563bf52 PM |
1786 | li r5, DABRX_USER | DABRX_KERNEL |
1787 | 3: | |
eee7ff9d MN |
1788 | BEGIN_FTR_SECTION |
1789 | b 2f | |
1790 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
a8606e20 | 1791 | std r4,VCPU_DABR(r3) |
8563bf52 PM |
1792 | stw r5, VCPU_DABRX(r3) |
1793 | mtspr SPRN_DABRX, r5 | |
8943633c PM |
1794 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
1795 | 1: mtspr SPRN_DABR,r4 | |
1796 | mfspr r5, SPRN_DABR | |
1797 | cmpd r4, r5 | |
1798 | bne 1b | |
1799 | isync | |
8563bf52 PM |
1800 | li r3,0 |
1801 | blr | |
1802 | ||
1803 | /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */ | |
1804 | 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW | |
1805 | rlwimi r5, r4, 1, DAWRX_WT | |
1806 | clrrdi r4, r4, 3 | |
1807 | std r4, VCPU_DAWR(r3) | |
1808 | std r5, VCPU_DAWRX(r3) | |
1809 | mtspr SPRN_DAWR, r4 | |
1810 | mtspr SPRN_DAWRX, r5 | |
1811 | li r3, 0 | |
a8606e20 PM |
1812 | blr |
1813 | ||
19ccb76a PM |
1814 | _GLOBAL(kvmppc_h_cede) |
1815 | ori r11,r11,MSR_EE | |
1816 | std r11,VCPU_MSR(r3) | |
1817 | li r0,1 | |
1818 | stb r0,VCPU_CEDED(r3) | |
1819 | sync /* order setting ceded vs. testing prodded */ | |
1820 | lbz r5,VCPU_PRODDED(r3) | |
1821 | cmpwi r5,0 | |
04f995a5 | 1822 | bne kvm_cede_prodded |
19ccb76a PM |
1823 | li r0,0 /* set trap to 0 to say hcall is handled */ |
1824 | stw r0,VCPU_TRAP(r3) | |
1825 | li r0,H_SUCCESS | |
c75df6f9 | 1826 | std r0,VCPU_GPR(R3)(r3) |
19ccb76a | 1827 | BEGIN_FTR_SECTION |
04f995a5 | 1828 | b kvm_cede_exit /* just send it up to host on 970 */ |
19ccb76a PM |
1829 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) |
1830 | ||
1831 | /* | |
1832 | * Set our bit in the bitmask of napping threads unless all the | |
1833 | * other threads are already napping, in which case we send this | |
1834 | * up to the host. | |
1835 | */ | |
1836 | ld r5,HSTATE_KVM_VCORE(r13) | |
e0b7ec05 | 1837 | lbz r6,HSTATE_PTID(r13) |
19ccb76a PM |
1838 | lwz r8,VCORE_ENTRY_EXIT(r5) |
1839 | clrldi r8,r8,56 | |
1840 | li r0,1 | |
1841 | sld r0,r0,r6 | |
1842 | addi r6,r5,VCORE_NAPPING_THREADS | |
1843 | 31: lwarx r4,0,r6 | |
1844 | or r4,r4,r0 | |
c75df6f9 | 1845 | PPC_POPCNTW(R7,R4) |
19ccb76a | 1846 | cmpw r7,r8 |
04f995a5 | 1847 | bge kvm_cede_exit |
19ccb76a PM |
1848 | stwcx. r4,0,r6 |
1849 | bne 31b | |
e0b7ec05 | 1850 | li r0,NAPPING_CEDE |
19ccb76a PM |
1851 | stb r0,HSTATE_NAPPING(r13) |
1852 | /* order napping_threads update vs testing entry_exit_count */ | |
1853 | lwsync | |
19ccb76a PM |
1854 | lwz r7,VCORE_ENTRY_EXIT(r5) |
1855 | cmpwi r7,0x100 | |
1856 | bge 33f /* another thread already exiting */ | |
1857 | ||
1858 | /* | |
1859 | * Although not specifically required by the architecture, POWER7 | |
1860 | * preserves the following registers in nap mode, even if an SMT mode | |
1861 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
1862 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
1863 | */ | |
1864 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
1865 | std r14, VCPU_GPR(R14)(r3) |
1866 | std r15, VCPU_GPR(R15)(r3) | |
1867 | std r16, VCPU_GPR(R16)(r3) | |
1868 | std r17, VCPU_GPR(R17)(r3) | |
1869 | std r18, VCPU_GPR(R18)(r3) | |
1870 | std r19, VCPU_GPR(R19)(r3) | |
1871 | std r20, VCPU_GPR(R20)(r3) | |
1872 | std r21, VCPU_GPR(R21)(r3) | |
1873 | std r22, VCPU_GPR(R22)(r3) | |
1874 | std r23, VCPU_GPR(R23)(r3) | |
1875 | std r24, VCPU_GPR(R24)(r3) | |
1876 | std r25, VCPU_GPR(R25)(r3) | |
1877 | std r26, VCPU_GPR(R26)(r3) | |
1878 | std r27, VCPU_GPR(R27)(r3) | |
1879 | std r28, VCPU_GPR(R28)(r3) | |
1880 | std r29, VCPU_GPR(R29)(r3) | |
1881 | std r30, VCPU_GPR(R30)(r3) | |
1882 | std r31, VCPU_GPR(R31)(r3) | |
19ccb76a PM |
1883 | |
1884 | /* save FP state */ | |
595e4f7e | 1885 | bl kvmppc_save_fp |
19ccb76a PM |
1886 | |
1887 | /* | |
aa31e843 PM |
1888 | * Take a nap until a decrementer or external or doobell interrupt |
1889 | * occurs, with PECE1, PECE0 and PECEDP set in LPCR | |
19ccb76a | 1890 | */ |
f0888f70 PM |
1891 | li r0,1 |
1892 | stb r0,HSTATE_HWTHREAD_REQ(r13) | |
19ccb76a PM |
1893 | mfspr r5,SPRN_LPCR |
1894 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
aa31e843 PM |
1895 | BEGIN_FTR_SECTION |
1896 | oris r5,r5,LPCR_PECEDP@h | |
1897 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
19ccb76a PM |
1898 | mtspr SPRN_LPCR,r5 |
1899 | isync | |
1900 | li r0, 0 | |
1901 | std r0, HSTATE_SCRATCH0(r13) | |
1902 | ptesync | |
1903 | ld r0, HSTATE_SCRATCH0(r13) | |
1904 | 1: cmpd r0, r0 | |
1905 | bne 1b | |
1906 | nap | |
1907 | b . | |
1908 | ||
e3bbbbfa PM |
1909 | 33: mr r4, r3 |
1910 | li r3, 0 | |
1911 | li r12, 0 | |
1912 | b 34f | |
1913 | ||
19ccb76a | 1914 | kvm_end_cede: |
4619ac88 PM |
1915 | /* get vcpu pointer */ |
1916 | ld r4, HSTATE_KVM_VCPU(r13) | |
1917 | ||
19ccb76a PM |
1918 | /* Woken by external or decrementer interrupt */ |
1919 | ld r1, HSTATE_HOST_R1(r13) | |
19ccb76a | 1920 | |
19ccb76a PM |
1921 | /* load up FP state */ |
1922 | bl kvmppc_load_fp | |
1923 | ||
1924 | /* Load NV GPRS */ | |
c75df6f9 MN |
1925 | ld r14, VCPU_GPR(R14)(r4) |
1926 | ld r15, VCPU_GPR(R15)(r4) | |
1927 | ld r16, VCPU_GPR(R16)(r4) | |
1928 | ld r17, VCPU_GPR(R17)(r4) | |
1929 | ld r18, VCPU_GPR(R18)(r4) | |
1930 | ld r19, VCPU_GPR(R19)(r4) | |
1931 | ld r20, VCPU_GPR(R20)(r4) | |
1932 | ld r21, VCPU_GPR(R21)(r4) | |
1933 | ld r22, VCPU_GPR(R22)(r4) | |
1934 | ld r23, VCPU_GPR(R23)(r4) | |
1935 | ld r24, VCPU_GPR(R24)(r4) | |
1936 | ld r25, VCPU_GPR(R25)(r4) | |
1937 | ld r26, VCPU_GPR(R26)(r4) | |
1938 | ld r27, VCPU_GPR(R27)(r4) | |
1939 | ld r28, VCPU_GPR(R28)(r4) | |
1940 | ld r29, VCPU_GPR(R29)(r4) | |
1941 | ld r30, VCPU_GPR(R30)(r4) | |
1942 | ld r31, VCPU_GPR(R31)(r4) | |
e3bbbbfa PM |
1943 | |
1944 | /* Check the wake reason in SRR1 to see why we got here */ | |
1945 | bl kvmppc_check_wake_reason | |
19ccb76a PM |
1946 | |
1947 | /* clear our bit in vcore->napping_threads */ | |
e3bbbbfa PM |
1948 | 34: ld r5,HSTATE_KVM_VCORE(r13) |
1949 | lbz r7,HSTATE_PTID(r13) | |
19ccb76a | 1950 | li r0,1 |
e3bbbbfa | 1951 | sld r0,r0,r7 |
19ccb76a PM |
1952 | addi r6,r5,VCORE_NAPPING_THREADS |
1953 | 32: lwarx r7,0,r6 | |
1954 | andc r7,r7,r0 | |
1955 | stwcx. r7,0,r6 | |
1956 | bne 32b | |
1957 | li r0,0 | |
1958 | stb r0,HSTATE_NAPPING(r13) | |
1959 | ||
e3bbbbfa PM |
1960 | /* See if the wake reason means we need to exit */ |
1961 | stw r12, VCPU_TRAP(r4) | |
4619ac88 | 1962 | mr r9, r4 |
e3bbbbfa PM |
1963 | cmpdi r3, 0 |
1964 | bgt guest_exit_cont | |
4619ac88 | 1965 | |
19ccb76a PM |
1966 | /* see if any other thread is already exiting */ |
1967 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
1968 | cmpwi r0,0x100 | |
e3bbbbfa | 1969 | bge guest_exit_cont |
19ccb76a | 1970 | |
e3bbbbfa | 1971 | b kvmppc_cede_reentry /* if not go back to guest */ |
19ccb76a PM |
1972 | |
1973 | /* cede when already previously prodded case */ | |
04f995a5 PM |
1974 | kvm_cede_prodded: |
1975 | li r0,0 | |
19ccb76a PM |
1976 | stb r0,VCPU_PRODDED(r3) |
1977 | sync /* order testing prodded vs. clearing ceded */ | |
1978 | stb r0,VCPU_CEDED(r3) | |
1979 | li r3,H_SUCCESS | |
1980 | blr | |
1981 | ||
1982 | /* we've ceded but we want to give control to the host */ | |
04f995a5 | 1983 | kvm_cede_exit: |
4619ac88 | 1984 | b hcall_real_fallback |
19ccb76a | 1985 | |
b4072df4 PM |
1986 | /* Try to handle a machine check in real mode */ |
1987 | machine_check_realmode: | |
1988 | mr r3, r9 /* get vcpu pointer */ | |
1989 | bl .kvmppc_realmode_machine_check | |
1990 | nop | |
1991 | cmpdi r3, 0 /* continue exiting from guest? */ | |
1992 | ld r9, HSTATE_KVM_VCPU(r13) | |
1993 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1994 | beq mc_cont | |
1995 | /* If not, deliver a machine check. SRR0/1 are already set */ | |
1996 | li r10, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1997 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1998 | rotldi r11, r11, 63 | |
1999 | b fast_interrupt_c_return | |
2000 | ||
e3bbbbfa PM |
2001 | /* |
2002 | * Check the reason we woke from nap, and take appropriate action. | |
2003 | * Returns: | |
2004 | * 0 if nothing needs to be done | |
2005 | * 1 if something happened that needs to be handled by the host | |
2006 | * -1 if there was a guest wakeup (IPI) | |
2007 | * | |
2008 | * Also sets r12 to the interrupt vector for any interrupt that needs | |
2009 | * to be handled now by the host (0x500 for external interrupt), or zero. | |
2010 | */ | |
2011 | kvmppc_check_wake_reason: | |
2012 | mfspr r6, SPRN_SRR1 | |
aa31e843 PM |
2013 | BEGIN_FTR_SECTION |
2014 | rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */ | |
2015 | FTR_SECTION_ELSE | |
2016 | rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */ | |
2017 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) | |
2018 | cmpwi r6, 8 /* was it an external interrupt? */ | |
e3bbbbfa PM |
2019 | li r12, BOOK3S_INTERRUPT_EXTERNAL |
2020 | beq kvmppc_read_intr /* if so, see what it was */ | |
2021 | li r3, 0 | |
2022 | li r12, 0 | |
2023 | cmpwi r6, 6 /* was it the decrementer? */ | |
2024 | beq 0f | |
aa31e843 PM |
2025 | BEGIN_FTR_SECTION |
2026 | cmpwi r6, 5 /* privileged doorbell? */ | |
2027 | beq 0f | |
5d00f66b PM |
2028 | cmpwi r6, 3 /* hypervisor doorbell? */ |
2029 | beq 3f | |
aa31e843 | 2030 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
e3bbbbfa PM |
2031 | li r3, 1 /* anything else, return 1 */ |
2032 | 0: blr | |
2033 | ||
5d00f66b PM |
2034 | /* hypervisor doorbell */ |
2035 | 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL | |
2036 | li r3, 1 | |
2037 | blr | |
2038 | ||
c934243c PM |
2039 | /* |
2040 | * Determine what sort of external interrupt is pending (if any). | |
2041 | * Returns: | |
2042 | * 0 if no interrupt is pending | |
2043 | * 1 if an interrupt is pending that needs to be handled by the host | |
2044 | * -1 if there was a guest wakeup IPI (which has now been cleared) | |
2045 | */ | |
2046 | kvmppc_read_intr: | |
2047 | /* see if a host IPI is pending */ | |
2048 | li r3, 1 | |
2049 | lbz r0, HSTATE_HOST_IPI(r13) | |
2050 | cmpwi r0, 0 | |
2051 | bne 1f | |
371fefd6 | 2052 | |
c934243c PM |
2053 | /* Now read the interrupt from the ICP */ |
2054 | ld r6, HSTATE_XICS_PHYS(r13) | |
19ccb76a | 2055 | li r7, XICS_XIRR |
c934243c PM |
2056 | cmpdi r6, 0 |
2057 | beq- 1f | |
2058 | lwzcix r0, r6, r7 | |
2059 | rlwinm. r3, r0, 0, 0xffffff | |
19ccb76a | 2060 | sync |
c934243c | 2061 | beq 1f /* if nothing pending in the ICP */ |
371fefd6 | 2062 | |
c934243c PM |
2063 | /* We found something in the ICP... |
2064 | * | |
2065 | * If it's not an IPI, stash it in the PACA and return to | |
2066 | * the host, we don't (yet) handle directing real external | |
2067 | * interrupts directly to the guest | |
2068 | */ | |
2069 | cmpwi r3, XICS_IPI /* if there is, is it an IPI? */ | |
c934243c | 2070 | bne 42f |
371fefd6 | 2071 | |
c934243c PM |
2072 | /* It's an IPI, clear the MFRR and EOI it */ |
2073 | li r3, 0xff | |
2074 | li r8, XICS_MFRR | |
2075 | stbcix r3, r6, r8 /* clear the IPI */ | |
2076 | stwcix r0, r6, r7 /* EOI it */ | |
2077 | sync | |
f0888f70 | 2078 | |
c934243c PM |
2079 | /* We need to re-check host IPI now in case it got set in the |
2080 | * meantime. If it's clear, we bounce the interrupt to the | |
2081 | * guest | |
2082 | */ | |
2083 | lbz r0, HSTATE_HOST_IPI(r13) | |
2084 | cmpwi r0, 0 | |
2085 | bne- 43f | |
2086 | ||
2087 | /* OK, it's an IPI for us */ | |
2088 | li r3, -1 | |
2089 | 1: blr | |
2090 | ||
2091 | 42: /* It's not an IPI and it's for the host, stash it in the PACA | |
2092 | * before exit, it will be picked up by the host ICP driver | |
2093 | */ | |
2094 | stw r0, HSTATE_SAVED_XIRR(r13) | |
e3bbbbfa | 2095 | li r3, 1 |
c934243c PM |
2096 | b 1b |
2097 | ||
2098 | 43: /* We raced with the host, we need to resend that IPI, bummer */ | |
2099 | li r0, IPI_PRIORITY | |
2100 | stbcix r0, r6, r8 /* set the IPI */ | |
2101 | sync | |
e3bbbbfa | 2102 | li r3, 1 |
c934243c | 2103 | b 1b |
371fefd6 | 2104 | |
de56a948 PM |
2105 | /* |
2106 | * Save away FP, VMX and VSX registers. | |
2107 | * r3 = vcpu pointer | |
595e4f7e PM |
2108 | * N.B. r30 and r31 are volatile across this function, |
2109 | * thus it is not callable from C. | |
a8606e20 | 2110 | */ |
595e4f7e PM |
2111 | kvmppc_save_fp: |
2112 | mflr r30 | |
2113 | mr r31,r3 | |
8943633c PM |
2114 | mfmsr r5 |
2115 | ori r8,r5,MSR_FP | |
de56a948 PM |
2116 | #ifdef CONFIG_ALTIVEC |
2117 | BEGIN_FTR_SECTION | |
2118 | oris r8,r8,MSR_VEC@h | |
2119 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
2120 | #endif | |
2121 | #ifdef CONFIG_VSX | |
2122 | BEGIN_FTR_SECTION | |
2123 | oris r8,r8,MSR_VSX@h | |
2124 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
2125 | #endif | |
2126 | mtmsrd r8 | |
2127 | isync | |
595e4f7e PM |
2128 | addi r3,r3,VCPU_FPRS |
2129 | bl .store_fp_state | |
de56a948 PM |
2130 | #ifdef CONFIG_ALTIVEC |
2131 | BEGIN_FTR_SECTION | |
595e4f7e PM |
2132 | addi r3,r31,VCPU_VRS |
2133 | bl .store_vr_state | |
de56a948 PM |
2134 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2135 | #endif | |
2136 | mfspr r6,SPRN_VRSAVE | |
2137 | stw r6,VCPU_VRSAVE(r3) | |
595e4f7e | 2138 | mtlr r30 |
8943633c | 2139 | mtmsrd r5 |
de56a948 PM |
2140 | isync |
2141 | blr | |
2142 | ||
2143 | /* | |
2144 | * Load up FP, VMX and VSX registers | |
2145 | * r4 = vcpu pointer | |
595e4f7e PM |
2146 | * N.B. r30 and r31 are volatile across this function, |
2147 | * thus it is not callable from C. | |
de56a948 | 2148 | */ |
de56a948 | 2149 | kvmppc_load_fp: |
595e4f7e PM |
2150 | mflr r30 |
2151 | mr r31,r4 | |
de56a948 PM |
2152 | mfmsr r9 |
2153 | ori r8,r9,MSR_FP | |
2154 | #ifdef CONFIG_ALTIVEC | |
2155 | BEGIN_FTR_SECTION | |
2156 | oris r8,r8,MSR_VEC@h | |
2157 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
2158 | #endif | |
2159 | #ifdef CONFIG_VSX | |
2160 | BEGIN_FTR_SECTION | |
2161 | oris r8,r8,MSR_VSX@h | |
2162 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
2163 | #endif | |
2164 | mtmsrd r8 | |
2165 | isync | |
595e4f7e PM |
2166 | addi r3,r4,VCPU_FPRS |
2167 | bl .load_fp_state | |
de56a948 PM |
2168 | #ifdef CONFIG_ALTIVEC |
2169 | BEGIN_FTR_SECTION | |
595e4f7e PM |
2170 | addi r3,r31,VCPU_VRS |
2171 | bl .load_vr_state | |
de56a948 PM |
2172 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2173 | #endif | |
2174 | lwz r7,VCPU_VRSAVE(r4) | |
2175 | mtspr SPRN_VRSAVE,r7 | |
595e4f7e PM |
2176 | mtlr r30 |
2177 | mr r4,r31 | |
de56a948 | 2178 | blr |
44a3add8 PM |
2179 | |
2180 | /* | |
2181 | * We come here if we get any exception or interrupt while we are | |
2182 | * executing host real mode code while in guest MMU context. | |
2183 | * For now just spin, but we should do something better. | |
2184 | */ | |
2185 | kvmppc_bad_host_intr: | |
2186 | b . |