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b823f98f SW |
1 | /* |
2 | * OpenPIC emulation | |
3 | * | |
4 | * Copyright (c) 2004 Jocelyn Mayer | |
5 | * 2011 Alexander Graf | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
b823f98f | 25 | |
5df554ad SW |
26 | #include <linux/slab.h> |
27 | #include <linux/mutex.h> | |
28 | #include <linux/kvm_host.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/fs.h> | |
31 | #include <linux/anon_inodes.h> | |
32 | #include <asm/uaccess.h> | |
33 | #include <asm/mpic.h> | |
34 | #include <asm/kvm_para.h> | |
35 | #include <asm/kvm_host.h> | |
36 | #include <asm/kvm_ppc.h> | |
37 | #include "iodev.h" | |
38 | ||
b823f98f SW |
39 | #define MAX_CPU 32 |
40 | #define MAX_SRC 256 | |
41 | #define MAX_TMR 4 | |
42 | #define MAX_IPI 4 | |
43 | #define MAX_MSI 8 | |
44 | #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR) | |
45 | #define VID 0x03 /* MPIC version ID */ | |
46 | ||
47 | /* OpenPIC capability flags */ | |
48 | #define OPENPIC_FLAG_IDR_CRIT (1 << 0) | |
49 | #define OPENPIC_FLAG_ILR (2 << 0) | |
50 | ||
51 | /* OpenPIC address map */ | |
5df554ad | 52 | #define OPENPIC_REG_SIZE 0x40000 |
b823f98f SW |
53 | #define OPENPIC_GLB_REG_START 0x0 |
54 | #define OPENPIC_GLB_REG_SIZE 0x10F0 | |
55 | #define OPENPIC_TMR_REG_START 0x10F0 | |
56 | #define OPENPIC_TMR_REG_SIZE 0x220 | |
57 | #define OPENPIC_MSI_REG_START 0x1600 | |
58 | #define OPENPIC_MSI_REG_SIZE 0x200 | |
f0f5c481 SW |
59 | #define OPENPIC_SUMMARY_REG_START 0x3800 |
60 | #define OPENPIC_SUMMARY_REG_SIZE 0x800 | |
b823f98f SW |
61 | #define OPENPIC_SRC_REG_START 0x10000 |
62 | #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20) | |
63 | #define OPENPIC_CPU_REG_START 0x20000 | |
f0f5c481 | 64 | #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000)) |
b823f98f | 65 | |
f0f5c481 | 66 | struct fsl_mpic_info { |
b823f98f | 67 | int max_ext; |
f0f5c481 | 68 | }; |
b823f98f | 69 | |
f0f5c481 | 70 | static struct fsl_mpic_info fsl_mpic_20 = { |
b823f98f SW |
71 | .max_ext = 12, |
72 | }; | |
73 | ||
f0f5c481 | 74 | static struct fsl_mpic_info fsl_mpic_42 = { |
b823f98f SW |
75 | .max_ext = 12, |
76 | }; | |
77 | ||
78 | #define FRR_NIRQ_SHIFT 16 | |
79 | #define FRR_NCPU_SHIFT 8 | |
80 | #define FRR_VID_SHIFT 0 | |
81 | ||
82 | #define VID_REVISION_1_2 2 | |
83 | #define VID_REVISION_1_3 3 | |
84 | ||
85 | #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */ | |
86 | ||
87 | #define GCR_RESET 0x80000000 | |
88 | #define GCR_MODE_PASS 0x00000000 | |
89 | #define GCR_MODE_MIXED 0x20000000 | |
90 | #define GCR_MODE_PROXY 0x60000000 | |
91 | ||
92 | #define TBCR_CI 0x80000000 /* count inhibit */ | |
93 | #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */ | |
94 | ||
95 | #define IDR_EP_SHIFT 31 | |
96 | #define IDR_EP_MASK (1 << IDR_EP_SHIFT) | |
97 | #define IDR_CI0_SHIFT 30 | |
98 | #define IDR_CI1_SHIFT 29 | |
99 | #define IDR_P1_SHIFT 1 | |
100 | #define IDR_P0_SHIFT 0 | |
101 | ||
102 | #define ILR_INTTGT_MASK 0x000000ff | |
103 | #define ILR_INTTGT_INT 0x00 | |
104 | #define ILR_INTTGT_CINT 0x01 /* critical */ | |
105 | #define ILR_INTTGT_MCP 0x02 /* machine check */ | |
5df554ad | 106 | #define NUM_OUTPUTS 3 |
b823f98f | 107 | |
b823f98f SW |
108 | #define MSIIR_OFFSET 0x140 |
109 | #define MSIIR_SRS_SHIFT 29 | |
110 | #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT) | |
111 | #define MSIIR_IBS_SHIFT 24 | |
112 | #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT) | |
113 | ||
114 | static int get_current_cpu(void) | |
115 | { | |
5df554ad SW |
116 | #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) |
117 | struct kvm_vcpu *vcpu = current->thread.kvm_vcpu; | |
eb1e4f43 | 118 | return vcpu ? vcpu->arch.irq_cpu_id : -1; |
5df554ad SW |
119 | #else |
120 | /* XXX */ | |
121 | return -1; | |
122 | #endif | |
b823f98f SW |
123 | } |
124 | ||
5df554ad SW |
125 | static int openpic_cpu_write_internal(void *opaque, gpa_t addr, |
126 | u32 val, int idx); | |
127 | static int openpic_cpu_read_internal(void *opaque, gpa_t addr, | |
128 | u32 *ptr, int idx); | |
b823f98f | 129 | |
f0f5c481 | 130 | enum irq_type { |
b823f98f SW |
131 | IRQ_TYPE_NORMAL = 0, |
132 | IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ | |
133 | IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ | |
f0f5c481 | 134 | }; |
b823f98f | 135 | |
f0f5c481 | 136 | struct irq_queue { |
b823f98f SW |
137 | /* Round up to the nearest 64 IRQs so that the queue length |
138 | * won't change when moving between 32 and 64 bit hosts. | |
139 | */ | |
140 | unsigned long queue[BITS_TO_LONGS((MAX_IRQ + 63) & ~63)]; | |
141 | int next; | |
142 | int priority; | |
f0f5c481 | 143 | }; |
b823f98f | 144 | |
f0f5c481 | 145 | struct irq_source { |
b823f98f SW |
146 | uint32_t ivpr; /* IRQ vector/priority register */ |
147 | uint32_t idr; /* IRQ destination register */ | |
148 | uint32_t destmask; /* bitmap of CPU destinations */ | |
149 | int last_cpu; | |
5df554ad | 150 | int output; /* IRQ level, e.g. ILR_INTTGT_INT */ |
b823f98f | 151 | int pending; /* TRUE if IRQ is pending */ |
f0f5c481 | 152 | enum irq_type type; |
b823f98f | 153 | bool level:1; /* level-triggered */ |
f0f5c481 SW |
154 | bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ |
155 | }; | |
b823f98f SW |
156 | |
157 | #define IVPR_MASK_SHIFT 31 | |
158 | #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT) | |
159 | #define IVPR_ACTIVITY_SHIFT 30 | |
160 | #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT) | |
161 | #define IVPR_MODE_SHIFT 29 | |
162 | #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT) | |
163 | #define IVPR_POLARITY_SHIFT 23 | |
164 | #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT) | |
165 | #define IVPR_SENSE_SHIFT 22 | |
166 | #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT) | |
167 | ||
168 | #define IVPR_PRIORITY_MASK (0xF << 16) | |
169 | #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) | |
170 | #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) | |
171 | ||
172 | /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ | |
173 | #define IDR_EP 0x80000000 /* external pin */ | |
174 | #define IDR_CI 0x40000000 /* critical interrupt */ | |
175 | ||
f0f5c481 | 176 | struct irq_dest { |
5df554ad SW |
177 | struct kvm_vcpu *vcpu; |
178 | ||
b823f98f | 179 | int32_t ctpr; /* CPU current task priority */ |
f0f5c481 SW |
180 | struct irq_queue raised; |
181 | struct irq_queue servicing; | |
b823f98f SW |
182 | |
183 | /* Count of IRQ sources asserting on non-INT outputs */ | |
5df554ad | 184 | uint32_t outputs_active[NUM_OUTPUTS]; |
f0f5c481 | 185 | }; |
b823f98f | 186 | |
f0f5c481 | 187 | struct openpic { |
5df554ad SW |
188 | struct kvm *kvm; |
189 | struct kvm_device *dev; | |
190 | struct kvm_io_device mmio; | |
191 | struct list_head mmio_regions; | |
192 | atomic_t users; | |
193 | bool mmio_mapped; | |
194 | ||
195 | gpa_t reg_base; | |
196 | spinlock_t lock; | |
197 | ||
b823f98f | 198 | /* Behavior control */ |
f0f5c481 | 199 | struct fsl_mpic_info *fsl; |
b823f98f SW |
200 | uint32_t model; |
201 | uint32_t flags; | |
202 | uint32_t nb_irqs; | |
203 | uint32_t vid; | |
204 | uint32_t vir; /* Vendor identification register */ | |
205 | uint32_t vector_mask; | |
206 | uint32_t tfrr_reset; | |
207 | uint32_t ivpr_reset; | |
208 | uint32_t idr_reset; | |
209 | uint32_t brr1; | |
210 | uint32_t mpic_mode_mask; | |
211 | ||
b823f98f SW |
212 | /* Global registers */ |
213 | uint32_t frr; /* Feature reporting register */ | |
214 | uint32_t gcr; /* Global configuration register */ | |
215 | uint32_t pir; /* Processor initialization register */ | |
216 | uint32_t spve; /* Spurious vector register */ | |
217 | uint32_t tfrr; /* Timer frequency reporting register */ | |
218 | /* Source registers */ | |
f0f5c481 | 219 | struct irq_source src[MAX_IRQ]; |
b823f98f | 220 | /* Local registers per output pin */ |
f0f5c481 | 221 | struct irq_dest dst[MAX_CPU]; |
b823f98f SW |
222 | uint32_t nb_cpus; |
223 | /* Timer registers */ | |
224 | struct { | |
225 | uint32_t tccr; /* Global timer current count register */ | |
226 | uint32_t tbcr; /* Global timer base count register */ | |
227 | } timers[MAX_TMR]; | |
228 | /* Shared MSI registers */ | |
229 | struct { | |
230 | uint32_t msir; /* Shared Message Signaled Interrupt Register */ | |
231 | } msi[MAX_MSI]; | |
232 | uint32_t max_irq; | |
233 | uint32_t irq_ipi0; | |
234 | uint32_t irq_tim0; | |
235 | uint32_t irq_msi; | |
f0f5c481 | 236 | }; |
b823f98f | 237 | |
5df554ad SW |
238 | |
239 | static void mpic_irq_raise(struct openpic *opp, struct irq_dest *dst, | |
240 | int output) | |
241 | { | |
242 | struct kvm_interrupt irq = { | |
243 | .irq = KVM_INTERRUPT_SET_LEVEL, | |
244 | }; | |
245 | ||
246 | if (!dst->vcpu) { | |
247 | pr_debug("%s: destination cpu %d does not exist\n", | |
248 | __func__, (int)(dst - &opp->dst[0])); | |
249 | return; | |
250 | } | |
251 | ||
eb1e4f43 | 252 | pr_debug("%s: cpu %d output %d\n", __func__, dst->vcpu->arch.irq_cpu_id, |
5df554ad SW |
253 | output); |
254 | ||
255 | if (output != ILR_INTTGT_INT) /* TODO */ | |
256 | return; | |
257 | ||
258 | kvm_vcpu_ioctl_interrupt(dst->vcpu, &irq); | |
259 | } | |
260 | ||
261 | static void mpic_irq_lower(struct openpic *opp, struct irq_dest *dst, | |
262 | int output) | |
263 | { | |
264 | if (!dst->vcpu) { | |
265 | pr_debug("%s: destination cpu %d does not exist\n", | |
266 | __func__, (int)(dst - &opp->dst[0])); | |
267 | return; | |
268 | } | |
269 | ||
eb1e4f43 | 270 | pr_debug("%s: cpu %d output %d\n", __func__, dst->vcpu->arch.irq_cpu_id, |
5df554ad SW |
271 | output); |
272 | ||
273 | if (output != ILR_INTTGT_INT) /* TODO */ | |
274 | return; | |
275 | ||
276 | kvmppc_core_dequeue_external(dst->vcpu); | |
277 | } | |
278 | ||
f0f5c481 | 279 | static inline void IRQ_setbit(struct irq_queue *q, int n_IRQ) |
b823f98f SW |
280 | { |
281 | set_bit(n_IRQ, q->queue); | |
282 | } | |
283 | ||
f0f5c481 | 284 | static inline void IRQ_resetbit(struct irq_queue *q, int n_IRQ) |
b823f98f SW |
285 | { |
286 | clear_bit(n_IRQ, q->queue); | |
287 | } | |
288 | ||
f0f5c481 | 289 | static inline int IRQ_testbit(struct irq_queue *q, int n_IRQ) |
b823f98f SW |
290 | { |
291 | return test_bit(n_IRQ, q->queue); | |
292 | } | |
293 | ||
f0f5c481 | 294 | static void IRQ_check(struct openpic *opp, struct irq_queue *q) |
b823f98f SW |
295 | { |
296 | int irq = -1; | |
297 | int next = -1; | |
298 | int priority = -1; | |
299 | ||
300 | for (;;) { | |
301 | irq = find_next_bit(q->queue, opp->max_irq, irq + 1); | |
f0f5c481 | 302 | if (irq == opp->max_irq) |
b823f98f | 303 | break; |
b823f98f | 304 | |
f0f5c481 | 305 | pr_debug("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n", |
b823f98f SW |
306 | irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); |
307 | ||
308 | if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { | |
309 | next = irq; | |
310 | priority = IVPR_PRIORITY(opp->src[irq].ivpr); | |
311 | } | |
312 | } | |
313 | ||
314 | q->next = next; | |
315 | q->priority = priority; | |
316 | } | |
317 | ||
f0f5c481 | 318 | static int IRQ_get_next(struct openpic *opp, struct irq_queue *q) |
b823f98f SW |
319 | { |
320 | /* XXX: optimize */ | |
321 | IRQ_check(opp, q); | |
322 | ||
323 | return q->next; | |
324 | } | |
325 | ||
f0f5c481 | 326 | static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ, |
b823f98f SW |
327 | bool active, bool was_active) |
328 | { | |
f0f5c481 SW |
329 | struct irq_dest *dst; |
330 | struct irq_source *src; | |
b823f98f SW |
331 | int priority; |
332 | ||
333 | dst = &opp->dst[n_CPU]; | |
334 | src = &opp->src[n_IRQ]; | |
335 | ||
f0f5c481 | 336 | pr_debug("%s: IRQ %d active %d was %d\n", |
b823f98f SW |
337 | __func__, n_IRQ, active, was_active); |
338 | ||
5df554ad | 339 | if (src->output != ILR_INTTGT_INT) { |
f0f5c481 | 340 | pr_debug("%s: output %d irq %d active %d was %d count %d\n", |
b823f98f SW |
341 | __func__, src->output, n_IRQ, active, was_active, |
342 | dst->outputs_active[src->output]); | |
343 | ||
344 | /* On Freescale MPIC, critical interrupts ignore priority, | |
345 | * IACK, EOI, etc. Before MPIC v4.1 they also ignore | |
346 | * masking. | |
347 | */ | |
348 | if (active) { | |
f0f5c481 SW |
349 | if (!was_active && |
350 | dst->outputs_active[src->output]++ == 0) { | |
351 | pr_debug("%s: Raise OpenPIC output %d cpu %d irq %d\n", | |
352 | __func__, src->output, n_CPU, n_IRQ); | |
5df554ad | 353 | mpic_irq_raise(opp, dst, src->output); |
b823f98f SW |
354 | } |
355 | } else { | |
f0f5c481 SW |
356 | if (was_active && |
357 | --dst->outputs_active[src->output] == 0) { | |
358 | pr_debug("%s: Lower OpenPIC output %d cpu %d irq %d\n", | |
359 | __func__, src->output, n_CPU, n_IRQ); | |
5df554ad | 360 | mpic_irq_lower(opp, dst, src->output); |
b823f98f SW |
361 | } |
362 | } | |
363 | ||
364 | return; | |
365 | } | |
366 | ||
367 | priority = IVPR_PRIORITY(src->ivpr); | |
368 | ||
369 | /* Even if the interrupt doesn't have enough priority, | |
370 | * it is still raised, in case ctpr is lowered later. | |
371 | */ | |
f0f5c481 | 372 | if (active) |
b823f98f | 373 | IRQ_setbit(&dst->raised, n_IRQ); |
f0f5c481 | 374 | else |
b823f98f | 375 | IRQ_resetbit(&dst->raised, n_IRQ); |
b823f98f SW |
376 | |
377 | IRQ_check(opp, &dst->raised); | |
378 | ||
379 | if (active && priority <= dst->ctpr) { | |
f0f5c481 SW |
380 | pr_debug("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n", |
381 | __func__, n_IRQ, priority, dst->ctpr, n_CPU); | |
b823f98f SW |
382 | active = 0; |
383 | } | |
384 | ||
385 | if (active) { | |
386 | if (IRQ_get_next(opp, &dst->servicing) >= 0 && | |
387 | priority <= dst->servicing.priority) { | |
f0f5c481 SW |
388 | pr_debug("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", |
389 | __func__, n_IRQ, dst->servicing.next, n_CPU); | |
b823f98f | 390 | } else { |
f0f5c481 SW |
391 | pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n", |
392 | __func__, n_CPU, n_IRQ, dst->raised.next); | |
5df554ad | 393 | mpic_irq_raise(opp, dst, ILR_INTTGT_INT); |
b823f98f SW |
394 | } |
395 | } else { | |
396 | IRQ_get_next(opp, &dst->servicing); | |
397 | if (dst->raised.priority > dst->ctpr && | |
398 | dst->raised.priority > dst->servicing.priority) { | |
f0f5c481 SW |
399 | pr_debug("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n", |
400 | __func__, n_IRQ, dst->raised.next, | |
401 | dst->raised.priority, dst->ctpr, | |
402 | dst->servicing.priority, n_CPU); | |
b823f98f SW |
403 | /* IRQ line stays asserted */ |
404 | } else { | |
f0f5c481 SW |
405 | pr_debug("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n", |
406 | __func__, n_IRQ, dst->ctpr, | |
407 | dst->servicing.priority, n_CPU); | |
5df554ad | 408 | mpic_irq_lower(opp, dst, ILR_INTTGT_INT); |
b823f98f SW |
409 | } |
410 | } | |
411 | } | |
412 | ||
413 | /* update pic state because registers for n_IRQ have changed value */ | |
f0f5c481 | 414 | static void openpic_update_irq(struct openpic *opp, int n_IRQ) |
b823f98f | 415 | { |
f0f5c481 | 416 | struct irq_source *src; |
b823f98f SW |
417 | bool active, was_active; |
418 | int i; | |
419 | ||
420 | src = &opp->src[n_IRQ]; | |
421 | active = src->pending; | |
422 | ||
423 | if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { | |
424 | /* Interrupt source is disabled */ | |
f0f5c481 | 425 | pr_debug("%s: IRQ %d is disabled\n", __func__, n_IRQ); |
b823f98f SW |
426 | active = false; |
427 | } | |
428 | ||
f0f5c481 | 429 | was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); |
b823f98f SW |
430 | |
431 | /* | |
432 | * We don't have a similar check for already-active because | |
433 | * ctpr may have changed and we need to withdraw the interrupt. | |
434 | */ | |
435 | if (!active && !was_active) { | |
f0f5c481 | 436 | pr_debug("%s: IRQ %d is already inactive\n", __func__, n_IRQ); |
b823f98f SW |
437 | return; |
438 | } | |
439 | ||
f0f5c481 | 440 | if (active) |
b823f98f | 441 | src->ivpr |= IVPR_ACTIVITY_MASK; |
f0f5c481 | 442 | else |
b823f98f | 443 | src->ivpr &= ~IVPR_ACTIVITY_MASK; |
b823f98f SW |
444 | |
445 | if (src->destmask == 0) { | |
446 | /* No target */ | |
f0f5c481 | 447 | pr_debug("%s: IRQ %d has no target\n", __func__, n_IRQ); |
b823f98f SW |
448 | return; |
449 | } | |
450 | ||
451 | if (src->destmask == (1 << src->last_cpu)) { | |
452 | /* Only one CPU is allowed to receive this IRQ */ | |
453 | IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); | |
454 | } else if (!(src->ivpr & IVPR_MODE_MASK)) { | |
455 | /* Directed delivery mode */ | |
456 | for (i = 0; i < opp->nb_cpus; i++) { | |
457 | if (src->destmask & (1 << i)) { | |
458 | IRQ_local_pipe(opp, i, n_IRQ, active, | |
459 | was_active); | |
460 | } | |
461 | } | |
462 | } else { | |
463 | /* Distributed delivery mode */ | |
464 | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { | |
f0f5c481 | 465 | if (i == opp->nb_cpus) |
b823f98f | 466 | i = 0; |
f0f5c481 | 467 | |
b823f98f SW |
468 | if (src->destmask & (1 << i)) { |
469 | IRQ_local_pipe(opp, i, n_IRQ, active, | |
470 | was_active); | |
471 | src->last_cpu = i; | |
472 | break; | |
473 | } | |
474 | } | |
475 | } | |
476 | } | |
477 | ||
478 | static void openpic_set_irq(void *opaque, int n_IRQ, int level) | |
479 | { | |
f0f5c481 SW |
480 | struct openpic *opp = opaque; |
481 | struct irq_source *src; | |
b823f98f SW |
482 | |
483 | if (n_IRQ >= MAX_IRQ) { | |
5df554ad SW |
484 | WARN_ONCE(1, "%s: IRQ %d out of range\n", __func__, n_IRQ); |
485 | return; | |
b823f98f SW |
486 | } |
487 | ||
488 | src = &opp->src[n_IRQ]; | |
f0f5c481 | 489 | pr_debug("openpic: set irq %d = %d ivpr=0x%08x\n", |
b823f98f SW |
490 | n_IRQ, level, src->ivpr); |
491 | if (src->level) { | |
492 | /* level-sensitive irq */ | |
493 | src->pending = level; | |
494 | openpic_update_irq(opp, n_IRQ); | |
495 | } else { | |
496 | /* edge-sensitive irq */ | |
497 | if (level) { | |
498 | src->pending = 1; | |
499 | openpic_update_irq(opp, n_IRQ); | |
500 | } | |
501 | ||
5df554ad | 502 | if (src->output != ILR_INTTGT_INT) { |
b823f98f SW |
503 | /* Edge-triggered interrupts shouldn't be used |
504 | * with non-INT delivery, but just in case, | |
505 | * try to make it do something sane rather than | |
506 | * cause an interrupt storm. This is close to | |
507 | * what you'd probably see happen in real hardware. | |
508 | */ | |
509 | src->pending = 0; | |
510 | openpic_update_irq(opp, n_IRQ); | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
5df554ad | 515 | static void openpic_reset(struct openpic *opp) |
b823f98f | 516 | { |
b823f98f SW |
517 | int i; |
518 | ||
519 | opp->gcr = GCR_RESET; | |
520 | /* Initialise controller registers */ | |
521 | opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) | | |
b823f98f SW |
522 | (opp->vid << FRR_VID_SHIFT); |
523 | ||
524 | opp->pir = 0; | |
525 | opp->spve = -1 & opp->vector_mask; | |
526 | opp->tfrr = opp->tfrr_reset; | |
527 | /* Initialise IRQ sources */ | |
528 | for (i = 0; i < opp->max_irq; i++) { | |
529 | opp->src[i].ivpr = opp->ivpr_reset; | |
530 | opp->src[i].idr = opp->idr_reset; | |
531 | ||
532 | switch (opp->src[i].type) { | |
533 | case IRQ_TYPE_NORMAL: | |
534 | opp->src[i].level = | |
f0f5c481 | 535 | !!(opp->ivpr_reset & IVPR_SENSE_MASK); |
b823f98f SW |
536 | break; |
537 | ||
538 | case IRQ_TYPE_FSLINT: | |
539 | opp->src[i].ivpr |= IVPR_POLARITY_MASK; | |
540 | break; | |
541 | ||
542 | case IRQ_TYPE_FSLSPECIAL: | |
543 | break; | |
544 | } | |
545 | } | |
546 | /* Initialise IRQ destinations */ | |
547 | for (i = 0; i < MAX_CPU; i++) { | |
548 | opp->dst[i].ctpr = 15; | |
f0f5c481 | 549 | memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue)); |
b823f98f | 550 | opp->dst[i].raised.next = -1; |
f0f5c481 | 551 | memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue)); |
b823f98f SW |
552 | opp->dst[i].servicing.next = -1; |
553 | } | |
554 | /* Initialise timers */ | |
555 | for (i = 0; i < MAX_TMR; i++) { | |
556 | opp->timers[i].tccr = 0; | |
557 | opp->timers[i].tbcr = TBCR_CI; | |
558 | } | |
559 | /* Go out of RESET state */ | |
560 | opp->gcr = 0; | |
561 | } | |
562 | ||
f0f5c481 | 563 | static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ) |
b823f98f SW |
564 | { |
565 | return opp->src[n_IRQ].idr; | |
566 | } | |
567 | ||
f0f5c481 | 568 | static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ) |
b823f98f | 569 | { |
f0f5c481 | 570 | if (opp->flags & OPENPIC_FLAG_ILR) |
5df554ad | 571 | return opp->src[n_IRQ].output; |
b823f98f SW |
572 | |
573 | return 0xffffffff; | |
574 | } | |
575 | ||
f0f5c481 | 576 | static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ) |
b823f98f SW |
577 | { |
578 | return opp->src[n_IRQ].ivpr; | |
579 | } | |
580 | ||
f0f5c481 SW |
581 | static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ, |
582 | uint32_t val) | |
b823f98f | 583 | { |
f0f5c481 | 584 | struct irq_source *src = &opp->src[n_IRQ]; |
b823f98f SW |
585 | uint32_t normal_mask = (1UL << opp->nb_cpus) - 1; |
586 | uint32_t crit_mask = 0; | |
587 | uint32_t mask = normal_mask; | |
588 | int crit_shift = IDR_EP_SHIFT - opp->nb_cpus; | |
589 | int i; | |
590 | ||
591 | if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { | |
592 | crit_mask = mask << crit_shift; | |
593 | mask |= crit_mask | IDR_EP; | |
594 | } | |
595 | ||
596 | src->idr = val & mask; | |
f0f5c481 | 597 | pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); |
b823f98f SW |
598 | |
599 | if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { | |
600 | if (src->idr & crit_mask) { | |
601 | if (src->idr & normal_mask) { | |
f0f5c481 SW |
602 | pr_debug("%s: IRQ configured for multiple output types, using critical\n", |
603 | __func__); | |
b823f98f SW |
604 | } |
605 | ||
5df554ad | 606 | src->output = ILR_INTTGT_CINT; |
b823f98f SW |
607 | src->nomask = true; |
608 | src->destmask = 0; | |
609 | ||
610 | for (i = 0; i < opp->nb_cpus; i++) { | |
611 | int n_ci = IDR_CI0_SHIFT - i; | |
612 | ||
f0f5c481 | 613 | if (src->idr & (1UL << n_ci)) |
b823f98f | 614 | src->destmask |= 1UL << i; |
b823f98f SW |
615 | } |
616 | } else { | |
5df554ad | 617 | src->output = ILR_INTTGT_INT; |
b823f98f SW |
618 | src->nomask = false; |
619 | src->destmask = src->idr & normal_mask; | |
620 | } | |
621 | } else { | |
622 | src->destmask = src->idr; | |
623 | } | |
624 | } | |
625 | ||
f0f5c481 SW |
626 | static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ, |
627 | uint32_t val) | |
b823f98f SW |
628 | { |
629 | if (opp->flags & OPENPIC_FLAG_ILR) { | |
f0f5c481 | 630 | struct irq_source *src = &opp->src[n_IRQ]; |
b823f98f | 631 | |
5df554ad | 632 | src->output = val & ILR_INTTGT_MASK; |
f0f5c481 | 633 | pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, |
b823f98f SW |
634 | src->output); |
635 | ||
636 | /* TODO: on MPIC v4.0 only, set nomask for non-INT */ | |
637 | } | |
638 | } | |
639 | ||
f0f5c481 | 640 | static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ, |
b823f98f SW |
641 | uint32_t val) |
642 | { | |
643 | uint32_t mask; | |
644 | ||
645 | /* NOTE when implementing newer FSL MPIC models: starting with v4.0, | |
646 | * the polarity bit is read-only on internal interrupts. | |
647 | */ | |
648 | mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK | | |
649 | IVPR_POLARITY_MASK | opp->vector_mask; | |
650 | ||
651 | /* ACTIVITY bit is read-only */ | |
652 | opp->src[n_IRQ].ivpr = | |
653 | (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); | |
654 | ||
655 | /* For FSL internal interrupts, The sense bit is reserved and zero, | |
656 | * and the interrupt is always level-triggered. Timers and IPIs | |
657 | * have no sense or polarity bits, and are edge-triggered. | |
658 | */ | |
659 | switch (opp->src[n_IRQ].type) { | |
660 | case IRQ_TYPE_NORMAL: | |
661 | opp->src[n_IRQ].level = | |
f0f5c481 | 662 | !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); |
b823f98f SW |
663 | break; |
664 | ||
665 | case IRQ_TYPE_FSLINT: | |
666 | opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK; | |
667 | break; | |
668 | ||
669 | case IRQ_TYPE_FSLSPECIAL: | |
670 | opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK); | |
671 | break; | |
672 | } | |
673 | ||
674 | openpic_update_irq(opp, n_IRQ); | |
f0f5c481 | 675 | pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, |
b823f98f SW |
676 | opp->src[n_IRQ].ivpr); |
677 | } | |
678 | ||
f0f5c481 | 679 | static void openpic_gcr_write(struct openpic *opp, uint64_t val) |
b823f98f | 680 | { |
b823f98f | 681 | if (val & GCR_RESET) { |
5df554ad | 682 | openpic_reset(opp); |
b823f98f SW |
683 | return; |
684 | } | |
685 | ||
686 | opp->gcr &= ~opp->mpic_mode_mask; | |
687 | opp->gcr |= val & opp->mpic_mode_mask; | |
b823f98f SW |
688 | } |
689 | ||
5df554ad | 690 | static int openpic_gbl_write(void *opaque, gpa_t addr, u32 val) |
b823f98f | 691 | { |
f0f5c481 | 692 | struct openpic *opp = opaque; |
5df554ad | 693 | int err = 0; |
b823f98f | 694 | |
5df554ad | 695 | pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val); |
f0f5c481 | 696 | if (addr & 0xF) |
5df554ad | 697 | return 0; |
f0f5c481 | 698 | |
b823f98f | 699 | switch (addr) { |
f0f5c481 | 700 | case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ |
b823f98f SW |
701 | break; |
702 | case 0x40: | |
703 | case 0x50: | |
704 | case 0x60: | |
705 | case 0x70: | |
706 | case 0x80: | |
707 | case 0x90: | |
708 | case 0xA0: | |
709 | case 0xB0: | |
5df554ad SW |
710 | err = openpic_cpu_write_internal(opp, addr, val, |
711 | get_current_cpu()); | |
b823f98f SW |
712 | break; |
713 | case 0x1000: /* FRR */ | |
714 | break; | |
715 | case 0x1020: /* GCR */ | |
716 | openpic_gcr_write(opp, val); | |
717 | break; | |
718 | case 0x1080: /* VIR */ | |
719 | break; | |
720 | case 0x1090: /* PIR */ | |
5df554ad SW |
721 | /* |
722 | * This register is used to reset a CPU core -- | |
723 | * let userspace handle it. | |
724 | */ | |
725 | err = -ENXIO; | |
b823f98f SW |
726 | break; |
727 | case 0x10A0: /* IPI_IVPR */ | |
728 | case 0x10B0: | |
729 | case 0x10C0: | |
f0f5c481 SW |
730 | case 0x10D0: { |
731 | int idx; | |
732 | idx = (addr - 0x10A0) >> 4; | |
733 | write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); | |
b823f98f | 734 | break; |
f0f5c481 | 735 | } |
b823f98f SW |
736 | case 0x10E0: /* SPVE */ |
737 | opp->spve = val & opp->vector_mask; | |
738 | break; | |
739 | default: | |
740 | break; | |
741 | } | |
5df554ad SW |
742 | |
743 | return err; | |
b823f98f SW |
744 | } |
745 | ||
5df554ad | 746 | static int openpic_gbl_read(void *opaque, gpa_t addr, u32 *ptr) |
b823f98f | 747 | { |
f0f5c481 | 748 | struct openpic *opp = opaque; |
5df554ad SW |
749 | u32 retval; |
750 | int err = 0; | |
b823f98f | 751 | |
5df554ad | 752 | pr_debug("%s: addr %#llx\n", __func__, addr); |
b823f98f | 753 | retval = 0xFFFFFFFF; |
f0f5c481 | 754 | if (addr & 0xF) |
5df554ad | 755 | goto out; |
f0f5c481 | 756 | |
b823f98f SW |
757 | switch (addr) { |
758 | case 0x1000: /* FRR */ | |
759 | retval = opp->frr; | |
5df554ad | 760 | retval |= (opp->nb_cpus - 1) << FRR_NCPU_SHIFT; |
b823f98f SW |
761 | break; |
762 | case 0x1020: /* GCR */ | |
763 | retval = opp->gcr; | |
764 | break; | |
765 | case 0x1080: /* VIR */ | |
766 | retval = opp->vir; | |
767 | break; | |
768 | case 0x1090: /* PIR */ | |
769 | retval = 0x00000000; | |
770 | break; | |
771 | case 0x00: /* Block Revision Register1 (BRR1) */ | |
772 | retval = opp->brr1; | |
773 | break; | |
774 | case 0x40: | |
775 | case 0x50: | |
776 | case 0x60: | |
777 | case 0x70: | |
778 | case 0x80: | |
779 | case 0x90: | |
780 | case 0xA0: | |
781 | case 0xB0: | |
5df554ad SW |
782 | err = openpic_cpu_read_internal(opp, addr, |
783 | &retval, get_current_cpu()); | |
b823f98f SW |
784 | break; |
785 | case 0x10A0: /* IPI_IVPR */ | |
786 | case 0x10B0: | |
787 | case 0x10C0: | |
788 | case 0x10D0: | |
789 | { | |
790 | int idx; | |
791 | idx = (addr - 0x10A0) >> 4; | |
792 | retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx); | |
793 | } | |
794 | break; | |
795 | case 0x10E0: /* SPVE */ | |
796 | retval = opp->spve; | |
797 | break; | |
798 | default: | |
799 | break; | |
800 | } | |
b823f98f | 801 | |
5df554ad SW |
802 | out: |
803 | pr_debug("%s: => 0x%08x\n", __func__, retval); | |
804 | *ptr = retval; | |
805 | return err; | |
b823f98f SW |
806 | } |
807 | ||
5df554ad | 808 | static int openpic_tmr_write(void *opaque, gpa_t addr, u32 val) |
b823f98f | 809 | { |
f0f5c481 | 810 | struct openpic *opp = opaque; |
b823f98f SW |
811 | int idx; |
812 | ||
813 | addr += 0x10f0; | |
814 | ||
5df554ad | 815 | pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val); |
f0f5c481 | 816 | if (addr & 0xF) |
5df554ad | 817 | return 0; |
b823f98f SW |
818 | |
819 | if (addr == 0x10f0) { | |
820 | /* TFRR */ | |
821 | opp->tfrr = val; | |
5df554ad | 822 | return 0; |
b823f98f SW |
823 | } |
824 | ||
825 | idx = (addr >> 6) & 0x3; | |
826 | addr = addr & 0x30; | |
827 | ||
828 | switch (addr & 0x30) { | |
829 | case 0x00: /* TCCR */ | |
830 | break; | |
831 | case 0x10: /* TBCR */ | |
832 | if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && | |
833 | (val & TBCR_CI) == 0 && | |
f0f5c481 | 834 | (opp->timers[idx].tbcr & TBCR_CI) != 0) |
b823f98f | 835 | opp->timers[idx].tccr &= ~TCCR_TOG; |
f0f5c481 | 836 | |
b823f98f SW |
837 | opp->timers[idx].tbcr = val; |
838 | break; | |
839 | case 0x20: /* TVPR */ | |
840 | write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val); | |
841 | break; | |
842 | case 0x30: /* TDR */ | |
843 | write_IRQreg_idr(opp, opp->irq_tim0 + idx, val); | |
844 | break; | |
845 | } | |
5df554ad SW |
846 | |
847 | return 0; | |
b823f98f SW |
848 | } |
849 | ||
5df554ad | 850 | static int openpic_tmr_read(void *opaque, gpa_t addr, u32 *ptr) |
b823f98f | 851 | { |
f0f5c481 | 852 | struct openpic *opp = opaque; |
b823f98f SW |
853 | uint32_t retval = -1; |
854 | int idx; | |
855 | ||
5df554ad | 856 | pr_debug("%s: addr %#llx\n", __func__, addr); |
f0f5c481 | 857 | if (addr & 0xF) |
b823f98f | 858 | goto out; |
f0f5c481 | 859 | |
b823f98f SW |
860 | idx = (addr >> 6) & 0x3; |
861 | if (addr == 0x0) { | |
862 | /* TFRR */ | |
863 | retval = opp->tfrr; | |
864 | goto out; | |
865 | } | |
5df554ad | 866 | |
b823f98f SW |
867 | switch (addr & 0x30) { |
868 | case 0x00: /* TCCR */ | |
869 | retval = opp->timers[idx].tccr; | |
870 | break; | |
871 | case 0x10: /* TBCR */ | |
872 | retval = opp->timers[idx].tbcr; | |
873 | break; | |
874 | case 0x20: /* TIPV */ | |
875 | retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); | |
876 | break; | |
877 | case 0x30: /* TIDE (TIDR) */ | |
878 | retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx); | |
879 | break; | |
880 | } | |
881 | ||
882 | out: | |
f0f5c481 | 883 | pr_debug("%s: => 0x%08x\n", __func__, retval); |
5df554ad SW |
884 | *ptr = retval; |
885 | return 0; | |
b823f98f SW |
886 | } |
887 | ||
5df554ad | 888 | static int openpic_src_write(void *opaque, gpa_t addr, u32 val) |
b823f98f | 889 | { |
f0f5c481 | 890 | struct openpic *opp = opaque; |
b823f98f SW |
891 | int idx; |
892 | ||
5df554ad | 893 | pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val); |
b823f98f SW |
894 | |
895 | addr = addr & 0xffff; | |
896 | idx = addr >> 5; | |
897 | ||
898 | switch (addr & 0x1f) { | |
899 | case 0x00: | |
900 | write_IRQreg_ivpr(opp, idx, val); | |
901 | break; | |
902 | case 0x10: | |
903 | write_IRQreg_idr(opp, idx, val); | |
904 | break; | |
905 | case 0x18: | |
906 | write_IRQreg_ilr(opp, idx, val); | |
907 | break; | |
908 | } | |
5df554ad SW |
909 | |
910 | return 0; | |
b823f98f SW |
911 | } |
912 | ||
5df554ad | 913 | static int openpic_src_read(void *opaque, gpa_t addr, u32 *ptr) |
b823f98f | 914 | { |
f0f5c481 | 915 | struct openpic *opp = opaque; |
b823f98f SW |
916 | uint32_t retval; |
917 | int idx; | |
918 | ||
5df554ad | 919 | pr_debug("%s: addr %#llx\n", __func__, addr); |
b823f98f SW |
920 | retval = 0xFFFFFFFF; |
921 | ||
922 | addr = addr & 0xffff; | |
923 | idx = addr >> 5; | |
924 | ||
925 | switch (addr & 0x1f) { | |
926 | case 0x00: | |
927 | retval = read_IRQreg_ivpr(opp, idx); | |
928 | break; | |
929 | case 0x10: | |
930 | retval = read_IRQreg_idr(opp, idx); | |
931 | break; | |
932 | case 0x18: | |
933 | retval = read_IRQreg_ilr(opp, idx); | |
934 | break; | |
935 | } | |
936 | ||
f0f5c481 | 937 | pr_debug("%s: => 0x%08x\n", __func__, retval); |
5df554ad SW |
938 | *ptr = retval; |
939 | return 0; | |
b823f98f SW |
940 | } |
941 | ||
5df554ad | 942 | static int openpic_msi_write(void *opaque, gpa_t addr, u32 val) |
b823f98f | 943 | { |
f0f5c481 | 944 | struct openpic *opp = opaque; |
b823f98f SW |
945 | int idx = opp->irq_msi; |
946 | int srs, ibs; | |
947 | ||
5df554ad | 948 | pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val); |
f0f5c481 | 949 | if (addr & 0xF) |
5df554ad | 950 | return 0; |
b823f98f SW |
951 | |
952 | switch (addr) { | |
953 | case MSIIR_OFFSET: | |
954 | srs = val >> MSIIR_SRS_SHIFT; | |
955 | idx += srs; | |
956 | ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT; | |
957 | opp->msi[srs].msir |= 1 << ibs; | |
958 | openpic_set_irq(opp, idx, 1); | |
959 | break; | |
960 | default: | |
961 | /* most registers are read-only, thus ignored */ | |
962 | break; | |
963 | } | |
5df554ad SW |
964 | |
965 | return 0; | |
b823f98f SW |
966 | } |
967 | ||
5df554ad | 968 | static int openpic_msi_read(void *opaque, gpa_t addr, u32 *ptr) |
b823f98f | 969 | { |
f0f5c481 | 970 | struct openpic *opp = opaque; |
5df554ad | 971 | uint32_t r = 0; |
b823f98f SW |
972 | int i, srs; |
973 | ||
5df554ad | 974 | pr_debug("%s: addr %#llx\n", __func__, addr); |
f0f5c481 | 975 | if (addr & 0xF) |
5df554ad | 976 | return -ENXIO; |
b823f98f SW |
977 | |
978 | srs = addr >> 4; | |
979 | ||
980 | switch (addr) { | |
981 | case 0x00: | |
982 | case 0x10: | |
983 | case 0x20: | |
984 | case 0x30: | |
985 | case 0x40: | |
986 | case 0x50: | |
987 | case 0x60: | |
988 | case 0x70: /* MSIRs */ | |
989 | r = opp->msi[srs].msir; | |
990 | /* Clear on read */ | |
991 | opp->msi[srs].msir = 0; | |
992 | openpic_set_irq(opp, opp->irq_msi + srs, 0); | |
993 | break; | |
994 | case 0x120: /* MSISR */ | |
f0f5c481 | 995 | for (i = 0; i < MAX_MSI; i++) |
b823f98f | 996 | r |= (opp->msi[i].msir ? 1 : 0) << i; |
b823f98f SW |
997 | break; |
998 | } | |
999 | ||
5df554ad SW |
1000 | pr_debug("%s: => 0x%08x\n", __func__, r); |
1001 | *ptr = r; | |
1002 | return 0; | |
b823f98f SW |
1003 | } |
1004 | ||
5df554ad | 1005 | static int openpic_summary_read(void *opaque, gpa_t addr, u32 *ptr) |
b823f98f | 1006 | { |
5df554ad | 1007 | uint32_t r = 0; |
b823f98f | 1008 | |
5df554ad | 1009 | pr_debug("%s: addr %#llx\n", __func__, addr); |
b823f98f SW |
1010 | |
1011 | /* TODO: EISR/EIMR */ | |
1012 | ||
5df554ad SW |
1013 | *ptr = r; |
1014 | return 0; | |
b823f98f SW |
1015 | } |
1016 | ||
5df554ad | 1017 | static int openpic_summary_write(void *opaque, gpa_t addr, u32 val) |
b823f98f | 1018 | { |
5df554ad | 1019 | pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val); |
b823f98f SW |
1020 | |
1021 | /* TODO: EISR/EIMR */ | |
5df554ad | 1022 | return 0; |
b823f98f SW |
1023 | } |
1024 | ||
5df554ad SW |
1025 | static int openpic_cpu_write_internal(void *opaque, gpa_t addr, |
1026 | u32 val, int idx) | |
b823f98f | 1027 | { |
f0f5c481 SW |
1028 | struct openpic *opp = opaque; |
1029 | struct irq_source *src; | |
1030 | struct irq_dest *dst; | |
b823f98f SW |
1031 | int s_IRQ, n_IRQ; |
1032 | ||
5df554ad | 1033 | pr_debug("%s: cpu %d addr %#llx <= 0x%08x\n", __func__, idx, |
b823f98f SW |
1034 | addr, val); |
1035 | ||
f0f5c481 | 1036 | if (idx < 0) |
5df554ad | 1037 | return 0; |
b823f98f | 1038 | |
f0f5c481 | 1039 | if (addr & 0xF) |
5df554ad | 1040 | return 0; |
f0f5c481 | 1041 | |
b823f98f SW |
1042 | dst = &opp->dst[idx]; |
1043 | addr &= 0xFF0; | |
1044 | switch (addr) { | |
1045 | case 0x40: /* IPIDR */ | |
1046 | case 0x50: | |
1047 | case 0x60: | |
1048 | case 0x70: | |
1049 | idx = (addr - 0x40) >> 4; | |
1050 | /* we use IDE as mask which CPUs to deliver the IPI to still. */ | |
1051 | opp->src[opp->irq_ipi0 + idx].destmask |= val; | |
1052 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 1); | |
1053 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); | |
1054 | break; | |
1055 | case 0x80: /* CTPR */ | |
1056 | dst->ctpr = val & 0x0000000F; | |
1057 | ||
f0f5c481 | 1058 | pr_debug("%s: set CPU %d ctpr to %d, raised %d servicing %d\n", |
b823f98f SW |
1059 | __func__, idx, dst->ctpr, dst->raised.priority, |
1060 | dst->servicing.priority); | |
1061 | ||
1062 | if (dst->raised.priority <= dst->ctpr) { | |
f0f5c481 SW |
1063 | pr_debug("%s: Lower OpenPIC INT output cpu %d due to ctpr\n", |
1064 | __func__, idx); | |
5df554ad | 1065 | mpic_irq_lower(opp, dst, ILR_INTTGT_INT); |
b823f98f | 1066 | } else if (dst->raised.priority > dst->servicing.priority) { |
f0f5c481 | 1067 | pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d\n", |
b823f98f | 1068 | __func__, idx, dst->raised.next); |
5df554ad | 1069 | mpic_irq_raise(opp, dst, ILR_INTTGT_INT); |
b823f98f SW |
1070 | } |
1071 | ||
1072 | break; | |
1073 | case 0x90: /* WHOAMI */ | |
1074 | /* Read-only register */ | |
1075 | break; | |
1076 | case 0xA0: /* IACK */ | |
1077 | /* Read-only register */ | |
1078 | break; | |
1079 | case 0xB0: /* EOI */ | |
f0f5c481 | 1080 | pr_debug("EOI\n"); |
b823f98f SW |
1081 | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
1082 | ||
1083 | if (s_IRQ < 0) { | |
f0f5c481 | 1084 | pr_debug("%s: EOI with no interrupt in service\n", |
b823f98f SW |
1085 | __func__); |
1086 | break; | |
1087 | } | |
1088 | ||
1089 | IRQ_resetbit(&dst->servicing, s_IRQ); | |
1090 | /* Set up next servicing IRQ */ | |
1091 | s_IRQ = IRQ_get_next(opp, &dst->servicing); | |
1092 | /* Check queued interrupts. */ | |
1093 | n_IRQ = IRQ_get_next(opp, &dst->raised); | |
1094 | src = &opp->src[n_IRQ]; | |
1095 | if (n_IRQ != -1 && | |
1096 | (s_IRQ == -1 || | |
1097 | IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { | |
f0f5c481 | 1098 | pr_debug("Raise OpenPIC INT output cpu %d irq %d\n", |
b823f98f | 1099 | idx, n_IRQ); |
5df554ad | 1100 | mpic_irq_raise(opp, dst, ILR_INTTGT_INT); |
b823f98f SW |
1101 | } |
1102 | break; | |
1103 | default: | |
1104 | break; | |
1105 | } | |
5df554ad SW |
1106 | |
1107 | return 0; | |
b823f98f SW |
1108 | } |
1109 | ||
5df554ad | 1110 | static int openpic_cpu_write(void *opaque, gpa_t addr, u32 val) |
b823f98f | 1111 | { |
5df554ad SW |
1112 | struct openpic *opp = opaque; |
1113 | ||
1114 | return openpic_cpu_write_internal(opp, addr, val, | |
1115 | (addr & 0x1f000) >> 12); | |
b823f98f SW |
1116 | } |
1117 | ||
f0f5c481 SW |
1118 | static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst, |
1119 | int cpu) | |
b823f98f | 1120 | { |
f0f5c481 | 1121 | struct irq_source *src; |
b823f98f SW |
1122 | int retval, irq; |
1123 | ||
f0f5c481 | 1124 | pr_debug("Lower OpenPIC INT output\n"); |
5df554ad | 1125 | mpic_irq_lower(opp, dst, ILR_INTTGT_INT); |
b823f98f SW |
1126 | |
1127 | irq = IRQ_get_next(opp, &dst->raised); | |
f0f5c481 | 1128 | pr_debug("IACK: irq=%d\n", irq); |
b823f98f | 1129 | |
f0f5c481 | 1130 | if (irq == -1) |
b823f98f SW |
1131 | /* No more interrupt pending */ |
1132 | return opp->spve; | |
b823f98f SW |
1133 | |
1134 | src = &opp->src[irq]; | |
1135 | if (!(src->ivpr & IVPR_ACTIVITY_MASK) || | |
1136 | !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { | |
f0f5c481 | 1137 | pr_err("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", |
b823f98f SW |
1138 | __func__, irq, dst->ctpr, src->ivpr); |
1139 | openpic_update_irq(opp, irq); | |
1140 | retval = opp->spve; | |
1141 | } else { | |
1142 | /* IRQ enter servicing state */ | |
1143 | IRQ_setbit(&dst->servicing, irq); | |
1144 | retval = IVPR_VECTOR(opp, src->ivpr); | |
1145 | } | |
1146 | ||
1147 | if (!src->level) { | |
1148 | /* edge-sensitive IRQ */ | |
1149 | src->ivpr &= ~IVPR_ACTIVITY_MASK; | |
1150 | src->pending = 0; | |
1151 | IRQ_resetbit(&dst->raised, irq); | |
1152 | } | |
1153 | ||
1154 | if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + MAX_IPI))) { | |
1155 | src->destmask &= ~(1 << cpu); | |
1156 | if (src->destmask && !src->level) { | |
1157 | /* trigger on CPUs that didn't know about it yet */ | |
1158 | openpic_set_irq(opp, irq, 1); | |
1159 | openpic_set_irq(opp, irq, 0); | |
1160 | /* if all CPUs knew about it, set active bit again */ | |
1161 | src->ivpr |= IVPR_ACTIVITY_MASK; | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | return retval; | |
1166 | } | |
1167 | ||
eb1e4f43 SW |
1168 | void kvmppc_mpic_set_epr(struct kvm_vcpu *vcpu) |
1169 | { | |
1170 | struct openpic *opp = vcpu->arch.mpic; | |
1171 | int cpu = vcpu->arch.irq_cpu_id; | |
1172 | unsigned long flags; | |
1173 | ||
1174 | spin_lock_irqsave(&opp->lock, flags); | |
1175 | ||
1176 | if ((opp->gcr & opp->mpic_mode_mask) == GCR_MODE_PROXY) | |
1177 | kvmppc_set_epr(vcpu, openpic_iack(opp, &opp->dst[cpu], cpu)); | |
1178 | ||
1179 | spin_unlock_irqrestore(&opp->lock, flags); | |
1180 | } | |
1181 | ||
5df554ad SW |
1182 | static int openpic_cpu_read_internal(void *opaque, gpa_t addr, |
1183 | u32 *ptr, int idx) | |
b823f98f | 1184 | { |
f0f5c481 SW |
1185 | struct openpic *opp = opaque; |
1186 | struct irq_dest *dst; | |
b823f98f SW |
1187 | uint32_t retval; |
1188 | ||
5df554ad | 1189 | pr_debug("%s: cpu %d addr %#llx\n", __func__, idx, addr); |
b823f98f SW |
1190 | retval = 0xFFFFFFFF; |
1191 | ||
f0f5c481 | 1192 | if (idx < 0) |
5df554ad | 1193 | goto out; |
b823f98f | 1194 | |
f0f5c481 | 1195 | if (addr & 0xF) |
5df554ad | 1196 | goto out; |
f0f5c481 | 1197 | |
b823f98f SW |
1198 | dst = &opp->dst[idx]; |
1199 | addr &= 0xFF0; | |
1200 | switch (addr) { | |
1201 | case 0x80: /* CTPR */ | |
1202 | retval = dst->ctpr; | |
1203 | break; | |
1204 | case 0x90: /* WHOAMI */ | |
1205 | retval = idx; | |
1206 | break; | |
1207 | case 0xA0: /* IACK */ | |
1208 | retval = openpic_iack(opp, dst, idx); | |
1209 | break; | |
1210 | case 0xB0: /* EOI */ | |
1211 | retval = 0; | |
1212 | break; | |
1213 | default: | |
1214 | break; | |
1215 | } | |
f0f5c481 | 1216 | pr_debug("%s: => 0x%08x\n", __func__, retval); |
b823f98f | 1217 | |
5df554ad SW |
1218 | out: |
1219 | *ptr = retval; | |
1220 | return 0; | |
b823f98f SW |
1221 | } |
1222 | ||
5df554ad | 1223 | static int openpic_cpu_read(void *opaque, gpa_t addr, u32 *ptr) |
b823f98f | 1224 | { |
5df554ad SW |
1225 | struct openpic *opp = opaque; |
1226 | ||
1227 | return openpic_cpu_read_internal(opp, addr, ptr, | |
1228 | (addr & 0x1f000) >> 12); | |
b823f98f SW |
1229 | } |
1230 | ||
5df554ad SW |
1231 | struct mem_reg { |
1232 | struct list_head list; | |
1233 | int (*read)(void *opaque, gpa_t addr, u32 *ptr); | |
1234 | int (*write)(void *opaque, gpa_t addr, u32 val); | |
1235 | gpa_t start_addr; | |
1236 | int size; | |
1237 | }; | |
1238 | ||
1239 | static struct mem_reg openpic_gbl_mmio = { | |
b823f98f SW |
1240 | .write = openpic_gbl_write, |
1241 | .read = openpic_gbl_read, | |
5df554ad SW |
1242 | .start_addr = OPENPIC_GLB_REG_START, |
1243 | .size = OPENPIC_GLB_REG_SIZE, | |
b823f98f SW |
1244 | }; |
1245 | ||
5df554ad | 1246 | static struct mem_reg openpic_tmr_mmio = { |
b823f98f SW |
1247 | .write = openpic_tmr_write, |
1248 | .read = openpic_tmr_read, | |
5df554ad SW |
1249 | .start_addr = OPENPIC_TMR_REG_START, |
1250 | .size = OPENPIC_TMR_REG_SIZE, | |
b823f98f SW |
1251 | }; |
1252 | ||
5df554ad | 1253 | static struct mem_reg openpic_cpu_mmio = { |
b823f98f SW |
1254 | .write = openpic_cpu_write, |
1255 | .read = openpic_cpu_read, | |
5df554ad SW |
1256 | .start_addr = OPENPIC_CPU_REG_START, |
1257 | .size = OPENPIC_CPU_REG_SIZE, | |
b823f98f SW |
1258 | }; |
1259 | ||
5df554ad | 1260 | static struct mem_reg openpic_src_mmio = { |
b823f98f SW |
1261 | .write = openpic_src_write, |
1262 | .read = openpic_src_read, | |
5df554ad SW |
1263 | .start_addr = OPENPIC_SRC_REG_START, |
1264 | .size = OPENPIC_SRC_REG_SIZE, | |
b823f98f SW |
1265 | }; |
1266 | ||
5df554ad | 1267 | static struct mem_reg openpic_msi_mmio = { |
b823f98f SW |
1268 | .read = openpic_msi_read, |
1269 | .write = openpic_msi_write, | |
5df554ad SW |
1270 | .start_addr = OPENPIC_MSI_REG_START, |
1271 | .size = OPENPIC_MSI_REG_SIZE, | |
b823f98f SW |
1272 | }; |
1273 | ||
5df554ad | 1274 | static struct mem_reg openpic_summary_mmio = { |
b823f98f SW |
1275 | .read = openpic_summary_read, |
1276 | .write = openpic_summary_write, | |
5df554ad SW |
1277 | .start_addr = OPENPIC_SUMMARY_REG_START, |
1278 | .size = OPENPIC_SUMMARY_REG_SIZE, | |
f0f5c481 | 1279 | }; |
b823f98f | 1280 | |
f0f5c481 | 1281 | static void fsl_common_init(struct openpic *opp) |
b823f98f SW |
1282 | { |
1283 | int i; | |
1284 | int virq = MAX_SRC; | |
1285 | ||
5df554ad SW |
1286 | list_add(&openpic_msi_mmio.list, &opp->mmio_regions); |
1287 | list_add(&openpic_summary_mmio.list, &opp->mmio_regions); | |
1288 | ||
b823f98f SW |
1289 | opp->vid = VID_REVISION_1_2; |
1290 | opp->vir = VIR_GENERIC; | |
1291 | opp->vector_mask = 0xFFFF; | |
1292 | opp->tfrr_reset = 0; | |
1293 | opp->ivpr_reset = IVPR_MASK_MASK; | |
1294 | opp->idr_reset = 1 << 0; | |
1295 | opp->max_irq = MAX_IRQ; | |
1296 | ||
1297 | opp->irq_ipi0 = virq; | |
1298 | virq += MAX_IPI; | |
1299 | opp->irq_tim0 = virq; | |
1300 | virq += MAX_TMR; | |
1301 | ||
5df554ad | 1302 | BUG_ON(virq > MAX_IRQ); |
b823f98f SW |
1303 | |
1304 | opp->irq_msi = 224; | |
1305 | ||
f0f5c481 | 1306 | for (i = 0; i < opp->fsl->max_ext; i++) |
b823f98f | 1307 | opp->src[i].level = false; |
b823f98f SW |
1308 | |
1309 | /* Internal interrupts, including message and MSI */ | |
1310 | for (i = 16; i < MAX_SRC; i++) { | |
1311 | opp->src[i].type = IRQ_TYPE_FSLINT; | |
1312 | opp->src[i].level = true; | |
1313 | } | |
1314 | ||
1315 | /* timers and IPIs */ | |
1316 | for (i = MAX_SRC; i < virq; i++) { | |
1317 | opp->src[i].type = IRQ_TYPE_FSLSPECIAL; | |
1318 | opp->src[i].level = false; | |
1319 | } | |
1320 | } | |
1321 | ||
5df554ad | 1322 | static int kvm_mpic_read_internal(struct openpic *opp, gpa_t addr, u32 *ptr) |
b823f98f | 1323 | { |
5df554ad | 1324 | struct list_head *node; |
b823f98f | 1325 | |
5df554ad SW |
1326 | list_for_each(node, &opp->mmio_regions) { |
1327 | struct mem_reg *mr = list_entry(node, struct mem_reg, list); | |
b823f98f | 1328 | |
5df554ad SW |
1329 | if (mr->start_addr > addr || addr >= mr->start_addr + mr->size) |
1330 | continue; | |
b823f98f | 1331 | |
5df554ad | 1332 | return mr->read(opp, addr - mr->start_addr, ptr); |
b823f98f | 1333 | } |
5df554ad SW |
1334 | |
1335 | return -ENXIO; | |
b823f98f SW |
1336 | } |
1337 | ||
5df554ad | 1338 | static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val) |
b823f98f | 1339 | { |
5df554ad SW |
1340 | struct list_head *node; |
1341 | ||
1342 | list_for_each(node, &opp->mmio_regions) { | |
1343 | struct mem_reg *mr = list_entry(node, struct mem_reg, list); | |
1344 | ||
1345 | if (mr->start_addr > addr || addr >= mr->start_addr + mr->size) | |
1346 | continue; | |
b823f98f | 1347 | |
5df554ad SW |
1348 | return mr->write(opp, addr - mr->start_addr, val); |
1349 | } | |
1350 | ||
1351 | return -ENXIO; | |
1352 | } | |
1353 | ||
1354 | static int kvm_mpic_read(struct kvm_io_device *this, gpa_t addr, | |
1355 | int len, void *ptr) | |
1356 | { | |
1357 | struct openpic *opp = container_of(this, struct openpic, mmio); | |
1358 | int ret; | |
1359 | union { | |
1360 | u32 val; | |
1361 | u8 bytes[4]; | |
1362 | } u; | |
1363 | ||
1364 | if (addr & (len - 1)) { | |
1365 | pr_debug("%s: bad alignment %llx/%d\n", | |
1366 | __func__, addr, len); | |
1367 | return -EINVAL; | |
1368 | } | |
1369 | ||
1370 | spin_lock_irq(&opp->lock); | |
1371 | ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val); | |
1372 | spin_unlock_irq(&opp->lock); | |
1373 | ||
1374 | /* | |
1375 | * Technically only 32-bit accesses are allowed, but be nice to | |
1376 | * people dumping registers a byte at a time -- it works in real | |
1377 | * hardware (reads only, not writes). | |
1378 | */ | |
1379 | if (len == 4) { | |
1380 | *(u32 *)ptr = u.val; | |
1381 | pr_debug("%s: addr %llx ret %d len 4 val %x\n", | |
1382 | __func__, addr, ret, u.val); | |
1383 | } else if (len == 1) { | |
1384 | *(u8 *)ptr = u.bytes[addr & 3]; | |
1385 | pr_debug("%s: addr %llx ret %d len 1 val %x\n", | |
1386 | __func__, addr, ret, u.bytes[addr & 3]); | |
1387 | } else { | |
1388 | pr_debug("%s: bad length %d\n", __func__, len); | |
1389 | return -EINVAL; | |
1390 | } | |
1391 | ||
1392 | return ret; | |
1393 | } | |
1394 | ||
1395 | static int kvm_mpic_write(struct kvm_io_device *this, gpa_t addr, | |
1396 | int len, const void *ptr) | |
1397 | { | |
1398 | struct openpic *opp = container_of(this, struct openpic, mmio); | |
1399 | int ret; | |
1400 | ||
1401 | if (len != 4) { | |
1402 | pr_debug("%s: bad length %d\n", __func__, len); | |
1403 | return -EOPNOTSUPP; | |
1404 | } | |
1405 | if (addr & 3) { | |
1406 | pr_debug("%s: bad alignment %llx/%d\n", __func__, addr, len); | |
1407 | return -EOPNOTSUPP; | |
1408 | } | |
1409 | ||
1410 | spin_lock_irq(&opp->lock); | |
1411 | ret = kvm_mpic_write_internal(opp, addr - opp->reg_base, | |
1412 | *(const u32 *)ptr); | |
1413 | spin_unlock_irq(&opp->lock); | |
1414 | ||
1415 | pr_debug("%s: addr %llx ret %d val %x\n", | |
1416 | __func__, addr, ret, *(const u32 *)ptr); | |
1417 | ||
1418 | return ret; | |
1419 | } | |
1420 | ||
1421 | static void kvm_mpic_dtor(struct kvm_io_device *this) | |
1422 | { | |
1423 | struct openpic *opp = container_of(this, struct openpic, mmio); | |
1424 | ||
1425 | opp->mmio_mapped = false; | |
1426 | } | |
1427 | ||
1428 | static const struct kvm_io_device_ops mpic_mmio_ops = { | |
1429 | .read = kvm_mpic_read, | |
1430 | .write = kvm_mpic_write, | |
1431 | .destructor = kvm_mpic_dtor, | |
1432 | }; | |
1433 | ||
1434 | static void map_mmio(struct openpic *opp) | |
1435 | { | |
1436 | BUG_ON(opp->mmio_mapped); | |
1437 | opp->mmio_mapped = true; | |
1438 | ||
1439 | kvm_iodevice_init(&opp->mmio, &mpic_mmio_ops); | |
1440 | ||
1441 | kvm_io_bus_register_dev(opp->kvm, KVM_MMIO_BUS, | |
1442 | opp->reg_base, OPENPIC_REG_SIZE, | |
1443 | &opp->mmio); | |
1444 | } | |
1445 | ||
1446 | static void unmap_mmio(struct openpic *opp) | |
1447 | { | |
eb1e4f43 SW |
1448 | if (opp->mmio_mapped) { |
1449 | opp->mmio_mapped = false; | |
1450 | kvm_io_bus_unregister_dev(opp->kvm, KVM_MMIO_BUS, &opp->mmio); | |
1451 | } | |
5df554ad SW |
1452 | } |
1453 | ||
1454 | static int set_base_addr(struct openpic *opp, struct kvm_device_attr *attr) | |
1455 | { | |
1456 | u64 base; | |
1457 | ||
1458 | if (copy_from_user(&base, (u64 __user *)(long)attr->addr, sizeof(u64))) | |
1459 | return -EFAULT; | |
1460 | ||
1461 | if (base & 0x3ffff) { | |
1462 | pr_debug("kvm mpic %s: KVM_DEV_MPIC_BASE_ADDR %08llx not aligned\n", | |
1463 | __func__, base); | |
1464 | return -EINVAL; | |
1465 | } | |
1466 | ||
1467 | if (base == opp->reg_base) | |
1468 | return 0; | |
1469 | ||
1470 | mutex_lock(&opp->kvm->slots_lock); | |
1471 | ||
1472 | unmap_mmio(opp); | |
1473 | opp->reg_base = base; | |
1474 | ||
1475 | pr_debug("kvm mpic %s: KVM_DEV_MPIC_BASE_ADDR %08llx\n", | |
1476 | __func__, base); | |
1477 | ||
1478 | if (base == 0) | |
1479 | goto out; | |
1480 | ||
1481 | map_mmio(opp); | |
1482 | ||
1483 | mutex_unlock(&opp->kvm->slots_lock); | |
1484 | out: | |
1485 | return 0; | |
1486 | } | |
1487 | ||
1488 | #define ATTR_SET 0 | |
1489 | #define ATTR_GET 1 | |
1490 | ||
1491 | static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type) | |
1492 | { | |
1493 | int ret; | |
1494 | ||
1495 | if (addr & 3) | |
1496 | return -ENXIO; | |
1497 | ||
1498 | spin_lock_irq(&opp->lock); | |
1499 | ||
1500 | if (type == ATTR_SET) | |
1501 | ret = kvm_mpic_write_internal(opp, addr, *val); | |
1502 | else | |
1503 | ret = kvm_mpic_read_internal(opp, addr, val); | |
1504 | ||
1505 | spin_unlock_irq(&opp->lock); | |
1506 | ||
1507 | pr_debug("%s: type %d addr %llx val %x\n", __func__, type, addr, *val); | |
1508 | ||
1509 | return ret; | |
1510 | } | |
1511 | ||
1512 | static int mpic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
1513 | { | |
1514 | struct openpic *opp = dev->private; | |
1515 | u32 attr32; | |
1516 | ||
1517 | switch (attr->group) { | |
1518 | case KVM_DEV_MPIC_GRP_MISC: | |
1519 | switch (attr->attr) { | |
1520 | case KVM_DEV_MPIC_BASE_ADDR: | |
1521 | return set_base_addr(opp, attr); | |
1522 | } | |
1523 | ||
1524 | break; | |
1525 | ||
1526 | case KVM_DEV_MPIC_GRP_REGISTER: | |
1527 | if (get_user(attr32, (u32 __user *)(long)attr->addr)) | |
1528 | return -EFAULT; | |
1529 | ||
1530 | return access_reg(opp, attr->attr, &attr32, ATTR_SET); | |
1531 | ||
1532 | case KVM_DEV_MPIC_GRP_IRQ_ACTIVE: | |
1533 | if (attr->attr > MAX_SRC) | |
1534 | return -EINVAL; | |
1535 | ||
1536 | if (get_user(attr32, (u32 __user *)(long)attr->addr)) | |
1537 | return -EFAULT; | |
1538 | ||
1539 | if (attr32 != 0 && attr32 != 1) | |
1540 | return -EINVAL; | |
1541 | ||
1542 | spin_lock_irq(&opp->lock); | |
1543 | openpic_set_irq(opp, attr->attr, attr32); | |
1544 | spin_unlock_irq(&opp->lock); | |
1545 | return 0; | |
1546 | } | |
1547 | ||
1548 | return -ENXIO; | |
1549 | } | |
1550 | ||
1551 | static int mpic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
1552 | { | |
1553 | struct openpic *opp = dev->private; | |
1554 | u64 attr64; | |
1555 | u32 attr32; | |
1556 | int ret; | |
1557 | ||
1558 | switch (attr->group) { | |
1559 | case KVM_DEV_MPIC_GRP_MISC: | |
1560 | switch (attr->attr) { | |
1561 | case KVM_DEV_MPIC_BASE_ADDR: | |
1562 | mutex_lock(&opp->kvm->slots_lock); | |
1563 | attr64 = opp->reg_base; | |
1564 | mutex_unlock(&opp->kvm->slots_lock); | |
1565 | ||
1566 | if (copy_to_user((u64 __user *)(long)attr->addr, | |
1567 | &attr64, sizeof(u64))) | |
1568 | return -EFAULT; | |
1569 | ||
1570 | return 0; | |
1571 | } | |
1572 | ||
1573 | break; | |
1574 | ||
1575 | case KVM_DEV_MPIC_GRP_REGISTER: | |
1576 | ret = access_reg(opp, attr->attr, &attr32, ATTR_GET); | |
1577 | if (ret) | |
1578 | return ret; | |
1579 | ||
1580 | if (put_user(attr32, (u32 __user *)(long)attr->addr)) | |
1581 | return -EFAULT; | |
1582 | ||
1583 | return 0; | |
1584 | ||
1585 | case KVM_DEV_MPIC_GRP_IRQ_ACTIVE: | |
1586 | if (attr->attr > MAX_SRC) | |
1587 | return -EINVAL; | |
1588 | ||
1589 | spin_lock_irq(&opp->lock); | |
1590 | attr32 = opp->src[attr->attr].pending; | |
1591 | spin_unlock_irq(&opp->lock); | |
1592 | ||
1593 | if (put_user(attr32, (u32 __user *)(long)attr->addr)) | |
1594 | return -EFAULT; | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | return -ENXIO; | |
1600 | } | |
1601 | ||
1602 | static int mpic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
1603 | { | |
1604 | switch (attr->group) { | |
1605 | case KVM_DEV_MPIC_GRP_MISC: | |
1606 | switch (attr->attr) { | |
1607 | case KVM_DEV_MPIC_BASE_ADDR: | |
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | break; | |
1612 | ||
1613 | case KVM_DEV_MPIC_GRP_REGISTER: | |
1614 | return 0; | |
1615 | ||
1616 | case KVM_DEV_MPIC_GRP_IRQ_ACTIVE: | |
1617 | if (attr->attr > MAX_SRC) | |
1618 | break; | |
1619 | ||
1620 | return 0; | |
1621 | } | |
1622 | ||
1623 | return -ENXIO; | |
1624 | } | |
1625 | ||
1626 | static void mpic_destroy(struct kvm_device *dev) | |
1627 | { | |
1628 | struct openpic *opp = dev->private; | |
1629 | ||
1630 | if (opp->mmio_mapped) { | |
1631 | /* | |
1632 | * Normally we get unmapped by kvm_io_bus_destroy(), | |
1633 | * which happens before the VCPUs release their references. | |
1634 | * | |
1635 | * Thus, we should only get here if no VCPUs took a reference | |
1636 | * to us in the first place. | |
1637 | */ | |
1638 | WARN_ON(opp->nb_cpus != 0); | |
1639 | unmap_mmio(opp); | |
1640 | } | |
1641 | ||
1642 | kfree(opp); | |
1643 | } | |
1644 | ||
1645 | static int mpic_create(struct kvm_device *dev, u32 type) | |
1646 | { | |
1647 | struct openpic *opp; | |
1648 | int ret; | |
1649 | ||
1650 | opp = kzalloc(sizeof(struct openpic), GFP_KERNEL); | |
1651 | if (!opp) | |
1652 | return -ENOMEM; | |
1653 | ||
1654 | dev->private = opp; | |
1655 | opp->kvm = dev->kvm; | |
1656 | opp->dev = dev; | |
1657 | opp->model = type; | |
1658 | spin_lock_init(&opp->lock); | |
1659 | ||
1660 | INIT_LIST_HEAD(&opp->mmio_regions); | |
1661 | list_add(&openpic_gbl_mmio.list, &opp->mmio_regions); | |
1662 | list_add(&openpic_tmr_mmio.list, &opp->mmio_regions); | |
1663 | list_add(&openpic_src_mmio.list, &opp->mmio_regions); | |
1664 | list_add(&openpic_cpu_mmio.list, &opp->mmio_regions); | |
b823f98f SW |
1665 | |
1666 | switch (opp->model) { | |
5df554ad | 1667 | case KVM_DEV_TYPE_FSL_MPIC_20: |
b823f98f SW |
1668 | opp->fsl = &fsl_mpic_20; |
1669 | opp->brr1 = 0x00400200; | |
1670 | opp->flags |= OPENPIC_FLAG_IDR_CRIT; | |
1671 | opp->nb_irqs = 80; | |
1672 | opp->mpic_mode_mask = GCR_MODE_MIXED; | |
1673 | ||
1674 | fsl_common_init(opp); | |
b823f98f SW |
1675 | |
1676 | break; | |
1677 | ||
5df554ad | 1678 | case KVM_DEV_TYPE_FSL_MPIC_42: |
b823f98f SW |
1679 | opp->fsl = &fsl_mpic_42; |
1680 | opp->brr1 = 0x00400402; | |
1681 | opp->flags |= OPENPIC_FLAG_ILR; | |
1682 | opp->nb_irqs = 196; | |
1683 | opp->mpic_mode_mask = GCR_MODE_PROXY; | |
1684 | ||
1685 | fsl_common_init(opp); | |
b823f98f SW |
1686 | |
1687 | break; | |
5df554ad SW |
1688 | |
1689 | default: | |
1690 | ret = -ENODEV; | |
1691 | goto err; | |
b823f98f SW |
1692 | } |
1693 | ||
5df554ad | 1694 | openpic_reset(opp); |
b823f98f | 1695 | return 0; |
5df554ad SW |
1696 | |
1697 | err: | |
1698 | kfree(opp); | |
1699 | return ret; | |
b823f98f | 1700 | } |
5df554ad SW |
1701 | |
1702 | struct kvm_device_ops kvm_mpic_ops = { | |
1703 | .name = "kvm-mpic", | |
1704 | .create = mpic_create, | |
1705 | .destroy = mpic_destroy, | |
1706 | .set_attr = mpic_set_attr, | |
1707 | .get_attr = mpic_get_attr, | |
1708 | .has_attr = mpic_has_attr, | |
1709 | }; | |
eb1e4f43 SW |
1710 | |
1711 | int kvmppc_mpic_connect_vcpu(struct kvm_device *dev, struct kvm_vcpu *vcpu, | |
1712 | u32 cpu) | |
1713 | { | |
1714 | struct openpic *opp = dev->private; | |
1715 | int ret = 0; | |
1716 | ||
1717 | if (dev->ops != &kvm_mpic_ops) | |
1718 | return -EPERM; | |
1719 | if (opp->kvm != vcpu->kvm) | |
1720 | return -EPERM; | |
1721 | if (cpu < 0 || cpu >= MAX_CPU) | |
1722 | return -EPERM; | |
1723 | ||
1724 | spin_lock_irq(&opp->lock); | |
1725 | ||
1726 | if (opp->dst[cpu].vcpu) { | |
1727 | ret = -EEXIST; | |
1728 | goto out; | |
1729 | } | |
1730 | if (vcpu->arch.irq_type) { | |
1731 | ret = -EBUSY; | |
1732 | goto out; | |
1733 | } | |
1734 | ||
1735 | opp->dst[cpu].vcpu = vcpu; | |
1736 | opp->nb_cpus = max(opp->nb_cpus, cpu + 1); | |
1737 | ||
1738 | vcpu->arch.mpic = opp; | |
1739 | vcpu->arch.irq_cpu_id = cpu; | |
1740 | vcpu->arch.irq_type = KVMPPC_IRQ_MPIC; | |
1741 | ||
1742 | /* This might need to be changed if GCR gets extended */ | |
1743 | if (opp->mpic_mode_mask == GCR_MODE_PROXY) | |
1744 | vcpu->arch.epr_flags |= KVMPPC_EPR_KERNEL; | |
1745 | ||
1746 | kvm_device_get(dev); | |
1747 | out: | |
1748 | spin_unlock_irq(&opp->lock); | |
1749 | return ret; | |
1750 | } | |
1751 | ||
1752 | /* | |
1753 | * This should only happen immediately before the mpic is destroyed, | |
1754 | * so we shouldn't need to worry about anything still trying to | |
1755 | * access the vcpu pointer. | |
1756 | */ | |
1757 | void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu) | |
1758 | { | |
1759 | BUG_ON(!opp->dst[vcpu->arch.irq_cpu_id].vcpu); | |
1760 | ||
1761 | opp->dst[vcpu->arch.irq_cpu_id].vcpu = NULL; | |
1762 | kvm_device_put(opp->dev); | |
1763 | } |