Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
30 | #include <linux/ctype.h> | |
31 | #include <linux/cache.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/signal.h> | |
d9b2b2a2 | 34 | #include <linux/lmb.h> |
1da177e4 | 35 | |
1da177e4 LT |
36 | #include <asm/processor.h> |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/mmu.h> | |
39 | #include <asm/mmu_context.h> | |
40 | #include <asm/page.h> | |
41 | #include <asm/types.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/uaccess.h> | |
44 | #include <asm/machdep.h> | |
d9b2b2a2 | 45 | #include <asm/prom.h> |
1da177e4 LT |
46 | #include <asm/abs_addr.h> |
47 | #include <asm/tlbflush.h> | |
48 | #include <asm/io.h> | |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
1da177e4 | 53 | #include <asm/sections.h> |
d0f13e3c | 54 | #include <asm/spu.h> |
aa39be09 | 55 | #include <asm/udbg.h> |
1da177e4 LT |
56 | |
57 | #ifdef DEBUG | |
58 | #define DBG(fmt...) udbg_printf(fmt) | |
59 | #else | |
60 | #define DBG(fmt...) | |
61 | #endif | |
62 | ||
3c726f8d BH |
63 | #ifdef DEBUG_LOW |
64 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
65 | #else | |
66 | #define DBG_LOW(fmt...) | |
67 | #endif | |
68 | ||
69 | #define KB (1024) | |
70 | #define MB (1024*KB) | |
658013e9 | 71 | #define GB (1024L*MB) |
3c726f8d | 72 | |
1da177e4 LT |
73 | /* |
74 | * Note: pte --> Linux PTE | |
75 | * HPTE --> PowerPC Hashed Page Table Entry | |
76 | * | |
77 | * Execution context: | |
78 | * htab_initialize is called with the MMU off (of course), but | |
79 | * the kernel has been copied down to zero so it can directly | |
80 | * reference global data. At this point it is very difficult | |
81 | * to print debug info. | |
82 | * | |
83 | */ | |
84 | ||
85 | #ifdef CONFIG_U3_DART | |
86 | extern unsigned long dart_tablebase; | |
87 | #endif /* CONFIG_U3_DART */ | |
88 | ||
799d6046 PM |
89 | static unsigned long _SDR1; |
90 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
91 | ||
8e561e7e | 92 | struct hash_pte *htab_address; |
337a7128 | 93 | unsigned long htab_size_bytes; |
96e28449 | 94 | unsigned long htab_hash_mask; |
3c726f8d BH |
95 | int mmu_linear_psize = MMU_PAGE_4K; |
96 | int mmu_virtual_psize = MMU_PAGE_4K; | |
bf72aeba | 97 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
98 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
99 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
100 | #endif | |
bf72aeba | 101 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 PM |
102 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
103 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; | |
584f8b71 | 104 | u16 mmu_slb_size = 64; |
3c726f8d | 105 | #ifdef CONFIG_HUGETLB_PAGE |
3c726f8d BH |
106 | unsigned int HPAGE_SHIFT; |
107 | #endif | |
bf72aeba PM |
108 | #ifdef CONFIG_PPC_64K_PAGES |
109 | int mmu_ci_restrictions; | |
110 | #endif | |
370a908d BH |
111 | #ifdef CONFIG_DEBUG_PAGEALLOC |
112 | static u8 *linear_map_hash_slots; | |
113 | static unsigned long linear_map_hash_count; | |
ed166692 | 114 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 115 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1da177e4 | 116 | |
3c726f8d BH |
117 | /* There are definitions of page sizes arrays to be used when none |
118 | * is provided by the firmware. | |
119 | */ | |
1da177e4 | 120 | |
3c726f8d BH |
121 | /* Pre-POWER4 CPUs (4k pages only) |
122 | */ | |
09de9ff8 | 123 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
124 | [MMU_PAGE_4K] = { |
125 | .shift = 12, | |
126 | .sllp = 0, | |
127 | .penc = 0, | |
128 | .avpnm = 0, | |
129 | .tlbiel = 0, | |
130 | }, | |
131 | }; | |
132 | ||
133 | /* POWER4, GPUL, POWER5 | |
134 | * | |
135 | * Support for 16Mb large pages | |
136 | */ | |
09de9ff8 | 137 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
138 | [MMU_PAGE_4K] = { |
139 | .shift = 12, | |
140 | .sllp = 0, | |
141 | .penc = 0, | |
142 | .avpnm = 0, | |
143 | .tlbiel = 1, | |
144 | }, | |
145 | [MMU_PAGE_16M] = { | |
146 | .shift = 24, | |
147 | .sllp = SLB_VSID_L, | |
148 | .penc = 0, | |
149 | .avpnm = 0x1UL, | |
150 | .tlbiel = 0, | |
151 | }, | |
152 | }; | |
153 | ||
bc033b63 BH |
154 | static unsigned long htab_convert_pte_flags(unsigned long pteflags) |
155 | { | |
156 | unsigned long rflags = pteflags & 0x1fa; | |
157 | ||
158 | /* _PAGE_EXEC -> NOEXEC */ | |
159 | if ((pteflags & _PAGE_EXEC) == 0) | |
160 | rflags |= HPTE_R_N; | |
161 | ||
162 | /* PP bits. PAGE_USER is already PP bit 0x2, so we only | |
163 | * need to add in 0x1 if it's a read-only user page | |
164 | */ | |
165 | if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) && | |
166 | (pteflags & _PAGE_DIRTY))) | |
167 | rflags |= 1; | |
168 | ||
169 | /* Always add C */ | |
170 | return rflags | HPTE_R_C; | |
171 | } | |
3c726f8d BH |
172 | |
173 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 174 | unsigned long pstart, unsigned long prot, |
1189be65 | 175 | int psize, int ssize) |
1da177e4 | 176 | { |
3c726f8d BH |
177 | unsigned long vaddr, paddr; |
178 | unsigned int step, shift; | |
3c726f8d | 179 | int ret = 0; |
1da177e4 | 180 | |
3c726f8d BH |
181 | shift = mmu_psize_defs[psize].shift; |
182 | step = 1 << shift; | |
1da177e4 | 183 | |
bc033b63 BH |
184 | prot = htab_convert_pte_flags(prot); |
185 | ||
186 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
187 | vstart, vend, pstart, prot, psize, ssize); | |
188 | ||
3c726f8d BH |
189 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
190 | vaddr += step, paddr += step) { | |
370a908d | 191 | unsigned long hash, hpteg; |
1189be65 PM |
192 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
193 | unsigned long va = hpt_va(vaddr, vsid, ssize); | |
9e88ba4e PM |
194 | unsigned long tprot = prot; |
195 | ||
196 | /* Make kernel text executable */ | |
549e8152 | 197 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 198 | tprot &= ~HPTE_R_N; |
1da177e4 | 199 | |
1189be65 | 200 | hash = hpt_hash(va, shift, ssize); |
1da177e4 LT |
201 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
202 | ||
c30a4df3 | 203 | BUG_ON(!ppc_md.hpte_insert); |
9e88ba4e | 204 | ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot, |
bc033b63 | 205 | HPTE_V_BOLTED, psize, ssize); |
c30a4df3 | 206 | |
3c726f8d BH |
207 | if (ret < 0) |
208 | break; | |
370a908d BH |
209 | #ifdef CONFIG_DEBUG_PAGEALLOC |
210 | if ((paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
211 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; | |
212 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
213 | } |
214 | return ret < 0 ? ret : 0; | |
215 | } | |
1da177e4 | 216 | |
ae86f008 | 217 | #ifdef CONFIG_MEMORY_HOTPLUG |
52db9b44 | 218 | static int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
219 | int psize, int ssize) |
220 | { | |
221 | unsigned long vaddr; | |
222 | unsigned int step, shift; | |
223 | ||
224 | shift = mmu_psize_defs[psize].shift; | |
225 | step = 1 << shift; | |
226 | ||
227 | if (!ppc_md.hpte_removebolted) { | |
52db9b44 BP |
228 | printk(KERN_WARNING "Platform doesn't implement " |
229 | "hpte_removebolted\n"); | |
230 | return -EINVAL; | |
f8c8803b BP |
231 | } |
232 | ||
233 | for (vaddr = vstart; vaddr < vend; vaddr += step) | |
234 | ppc_md.hpte_removebolted(vaddr, psize, ssize); | |
52db9b44 BP |
235 | |
236 | return 0; | |
f8c8803b | 237 | } |
ae86f008 | 238 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
f8c8803b | 239 | |
1189be65 PM |
240 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
241 | const char *uname, int depth, | |
242 | void *data) | |
243 | { | |
244 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
245 | u32 *prop; | |
246 | unsigned long size = 0; | |
247 | ||
248 | /* We are scanning "cpu" nodes only */ | |
249 | if (type == NULL || strcmp(type, "cpu") != 0) | |
250 | return 0; | |
251 | ||
252 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", | |
253 | &size); | |
254 | if (prop == NULL) | |
255 | return 0; | |
256 | for (; size >= 4; size -= 4, ++prop) { | |
257 | if (prop[0] == 40) { | |
258 | DBG("1T segment support detected\n"); | |
259 | cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT; | |
f5534004 | 260 | return 1; |
1189be65 | 261 | } |
1189be65 | 262 | } |
f66bce5e | 263 | cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B; |
1189be65 PM |
264 | return 0; |
265 | } | |
266 | ||
267 | static void __init htab_init_seg_sizes(void) | |
268 | { | |
269 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
270 | } | |
271 | ||
3c726f8d BH |
272 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
273 | const char *uname, int depth, | |
274 | void *data) | |
275 | { | |
276 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
277 | u32 *prop; | |
278 | unsigned long size = 0; | |
279 | ||
280 | /* We are scanning "cpu" nodes only */ | |
281 | if (type == NULL || strcmp(type, "cpu") != 0) | |
282 | return 0; | |
283 | ||
284 | prop = (u32 *)of_get_flat_dt_prop(node, | |
285 | "ibm,segment-page-sizes", &size); | |
286 | if (prop != NULL) { | |
287 | DBG("Page sizes from device-tree:\n"); | |
288 | size /= 4; | |
289 | cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE); | |
290 | while(size > 0) { | |
291 | unsigned int shift = prop[0]; | |
292 | unsigned int slbenc = prop[1]; | |
293 | unsigned int lpnum = prop[2]; | |
294 | unsigned int lpenc = 0; | |
295 | struct mmu_psize_def *def; | |
296 | int idx = -1; | |
297 | ||
298 | size -= 3; prop += 3; | |
299 | while(size > 0 && lpnum) { | |
300 | if (prop[0] == shift) | |
301 | lpenc = prop[1]; | |
302 | prop += 2; size -= 2; | |
303 | lpnum--; | |
304 | } | |
305 | switch(shift) { | |
306 | case 0xc: | |
307 | idx = MMU_PAGE_4K; | |
308 | break; | |
309 | case 0x10: | |
310 | idx = MMU_PAGE_64K; | |
311 | break; | |
312 | case 0x14: | |
313 | idx = MMU_PAGE_1M; | |
314 | break; | |
315 | case 0x18: | |
316 | idx = MMU_PAGE_16M; | |
317 | cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE; | |
318 | break; | |
319 | case 0x22: | |
320 | idx = MMU_PAGE_16G; | |
321 | break; | |
322 | } | |
323 | if (idx < 0) | |
324 | continue; | |
325 | def = &mmu_psize_defs[idx]; | |
326 | def->shift = shift; | |
327 | if (shift <= 23) | |
328 | def->avpnm = 0; | |
329 | else | |
330 | def->avpnm = (1 << (shift - 23)) - 1; | |
331 | def->sllp = slbenc; | |
332 | def->penc = lpenc; | |
333 | /* We don't know for sure what's up with tlbiel, so | |
334 | * for now we only set it for 4K and 64K pages | |
335 | */ | |
336 | if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K) | |
337 | def->tlbiel = 1; | |
338 | else | |
339 | def->tlbiel = 0; | |
340 | ||
341 | DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, " | |
342 | "tlbiel=%d, penc=%d\n", | |
343 | idx, shift, def->sllp, def->avpnm, def->tlbiel, | |
344 | def->penc); | |
1da177e4 | 345 | } |
3c726f8d BH |
346 | return 1; |
347 | } | |
348 | return 0; | |
349 | } | |
350 | ||
e16a9c09 | 351 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
352 | /* Scan for 16G memory blocks that have been set aside for huge pages |
353 | * and reserve those blocks for 16G huge pages. | |
354 | */ | |
355 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
356 | const char *uname, int depth, | |
357 | void *data) { | |
358 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
359 | unsigned long *addr_prop; | |
360 | u32 *page_count_prop; | |
361 | unsigned int expected_pages; | |
362 | long unsigned int phys_addr; | |
363 | long unsigned int block_size; | |
364 | ||
365 | /* We are scanning "memory" nodes only */ | |
366 | if (type == NULL || strcmp(type, "memory") != 0) | |
367 | return 0; | |
368 | ||
369 | /* This property is the log base 2 of the number of virtual pages that | |
370 | * will represent this memory block. */ | |
371 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
372 | if (page_count_prop == NULL) | |
373 | return 0; | |
374 | expected_pages = (1 << page_count_prop[0]); | |
375 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); | |
376 | if (addr_prop == NULL) | |
377 | return 0; | |
378 | phys_addr = addr_prop[0]; | |
379 | block_size = addr_prop[1]; | |
380 | if (block_size != (16 * GB)) | |
381 | return 0; | |
382 | printk(KERN_INFO "Huge page(16GB) memory: " | |
383 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
384 | phys_addr, block_size, expected_pages); | |
4792adba JT |
385 | if (phys_addr + (16 * GB) <= lmb_end_of_DRAM()) { |
386 | lmb_reserve(phys_addr, block_size * expected_pages); | |
387 | add_gpage(phys_addr, block_size, expected_pages); | |
388 | } | |
658013e9 JT |
389 | return 0; |
390 | } | |
e16a9c09 | 391 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 392 | |
3c726f8d BH |
393 | static void __init htab_init_page_sizes(void) |
394 | { | |
395 | int rc; | |
396 | ||
397 | /* Default to 4K pages only */ | |
398 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
399 | sizeof(mmu_psize_defaults_old)); | |
400 | ||
401 | /* | |
402 | * Try to find the available page sizes in the device-tree | |
403 | */ | |
404 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
405 | if (rc != 0) /* Found */ | |
406 | goto found; | |
407 | ||
408 | /* | |
409 | * Not in the device-tree, let's fallback on known size | |
410 | * list for 16M capable GP & GR | |
411 | */ | |
0470466d | 412 | if (cpu_has_feature(CPU_FTR_16M_PAGE)) |
3c726f8d BH |
413 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
414 | sizeof(mmu_psize_defaults_gp)); | |
415 | found: | |
370a908d | 416 | #ifndef CONFIG_DEBUG_PAGEALLOC |
3c726f8d BH |
417 | /* |
418 | * Pick a size for the linear mapping. Currently, we only support | |
419 | * 16M, 1M and 4K which is the default | |
420 | */ | |
421 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
422 | mmu_linear_psize = MMU_PAGE_16M; | |
423 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
424 | mmu_linear_psize = MMU_PAGE_1M; | |
370a908d | 425 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
3c726f8d | 426 | |
bf72aeba | 427 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
428 | /* |
429 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
430 | * 64K for user mappings and vmalloc if supported by the processor. |
431 | * We only use 64k for ioremap if the processor | |
432 | * (and firmware) support cache-inhibited large pages. | |
433 | * If not, we use 4k and set mmu_ci_restrictions so that | |
434 | * hash_page knows to switch processes that use cache-inhibited | |
435 | * mappings to 4k pages. | |
3c726f8d | 436 | */ |
bf72aeba | 437 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 438 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 439 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
440 | if (mmu_linear_psize == MMU_PAGE_4K) |
441 | mmu_linear_psize = MMU_PAGE_64K; | |
cfe666b1 PM |
442 | if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) { |
443 | /* | |
444 | * Don't use 64k pages for ioremap on pSeries, since | |
445 | * that would stop us accessing the HEA ethernet. | |
446 | */ | |
447 | if (!machine_is(pseries)) | |
448 | mmu_io_psize = MMU_PAGE_64K; | |
449 | } else | |
bf72aeba PM |
450 | mmu_ci_restrictions = 1; |
451 | } | |
370a908d | 452 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 453 | |
cec08e7a BH |
454 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
455 | /* We try to use 16M pages for vmemmap if that is supported | |
456 | * and we have at least 1G of RAM at boot | |
457 | */ | |
458 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
459 | lmb_phys_mem_size() >= 0x40000000) | |
460 | mmu_vmemmap_psize = MMU_PAGE_16M; | |
461 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
462 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
463 | else | |
464 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
465 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
466 | ||
bf72aeba | 467 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
468 | "virtual = %d, io = %d" |
469 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
470 | ", vmemmap = %d" | |
471 | #endif | |
472 | "\n", | |
3c726f8d | 473 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 474 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
475 | mmu_psize_defs[mmu_io_psize].shift |
476 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
477 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
478 | #endif | |
479 | ); | |
3c726f8d BH |
480 | |
481 | #ifdef CONFIG_HUGETLB_PAGE | |
658013e9 JT |
482 | /* Reserve 16G huge page memory sections for huge pages */ |
483 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
484 | ||
0d9ea754 | 485 | /* Set default large page size. Currently, we pick 16M or 1M depending |
3c726f8d BH |
486 | * on what is available |
487 | */ | |
488 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
0d9ea754 | 489 | HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_16M].shift; |
7d24f0b8 DG |
490 | /* With 4k/4level pagetables, we can't (for now) cope with a |
491 | * huge page size < PMD_SIZE */ | |
3c726f8d | 492 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) |
0d9ea754 | 493 | HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_1M].shift; |
3c726f8d BH |
494 | #endif /* CONFIG_HUGETLB_PAGE */ |
495 | } | |
496 | ||
497 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
498 | const char *uname, int depth, | |
499 | void *data) | |
500 | { | |
501 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
502 | u32 *prop; | |
503 | ||
504 | /* We are scanning "cpu" nodes only */ | |
505 | if (type == NULL || strcmp(type, "cpu") != 0) | |
506 | return 0; | |
507 | ||
508 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL); | |
509 | if (prop != NULL) { | |
510 | /* pft_size[0] is the NUMA CEC cookie */ | |
511 | ppc64_pft_size = prop[1]; | |
512 | return 1; | |
1da177e4 | 513 | } |
3c726f8d | 514 | return 0; |
1da177e4 LT |
515 | } |
516 | ||
3c726f8d | 517 | static unsigned long __init htab_get_table_size(void) |
3eac8c69 | 518 | { |
13870b65 | 519 | unsigned long mem_size, rnd_mem_size, pteg_count, psize; |
3eac8c69 | 520 | |
3c726f8d | 521 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 522 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 523 | * calculate it now based on the total RAM size |
3eac8c69 | 524 | */ |
3c726f8d BH |
525 | if (ppc64_pft_size == 0) |
526 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
527 | if (ppc64_pft_size) |
528 | return 1UL << ppc64_pft_size; | |
529 | ||
530 | /* round mem_size up to next power of 2 */ | |
799d6046 PM |
531 | mem_size = lmb_phys_mem_size(); |
532 | rnd_mem_size = 1UL << __ilog2(mem_size); | |
533 | if (rnd_mem_size < mem_size) | |
3eac8c69 PM |
534 | rnd_mem_size <<= 1; |
535 | ||
536 | /* # pages / 2 */ | |
13870b65 AB |
537 | psize = mmu_psize_defs[mmu_virtual_psize].shift; |
538 | pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11); | |
3eac8c69 PM |
539 | |
540 | return pteg_count << 7; | |
541 | } | |
542 | ||
54b79248 MK |
543 | #ifdef CONFIG_MEMORY_HOTPLUG |
544 | void create_section_mapping(unsigned long start, unsigned long end) | |
545 | { | |
bc033b63 | 546 | BUG_ON(htab_bolt_mapping(start, end, __pa(start), |
f5ea64dc | 547 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, |
bc033b63 | 548 | mmu_kernel_ssize)); |
54b79248 | 549 | } |
f8c8803b | 550 | |
52db9b44 | 551 | int remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 552 | { |
52db9b44 BP |
553 | return htab_remove_mapping(start, end, mmu_linear_psize, |
554 | mmu_kernel_ssize); | |
f8c8803b | 555 | } |
54b79248 MK |
556 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
557 | ||
7d0daae4 ME |
558 | static inline void make_bl(unsigned int *insn_addr, void *func) |
559 | { | |
560 | unsigned long funcp = *((unsigned long *)func); | |
561 | int offset = funcp - (unsigned long)insn_addr; | |
562 | ||
563 | *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc)); | |
564 | flush_icache_range((unsigned long)insn_addr, 4+ | |
565 | (unsigned long)insn_addr); | |
566 | } | |
567 | ||
568 | static void __init htab_finish_init(void) | |
569 | { | |
570 | extern unsigned int *htab_call_hpte_insert1; | |
571 | extern unsigned int *htab_call_hpte_insert2; | |
572 | extern unsigned int *htab_call_hpte_remove; | |
573 | extern unsigned int *htab_call_hpte_updatepp; | |
574 | ||
16c2d476 | 575 | #ifdef CONFIG_PPC_HAS_HASH_64K |
7d0daae4 ME |
576 | extern unsigned int *ht64_call_hpte_insert1; |
577 | extern unsigned int *ht64_call_hpte_insert2; | |
578 | extern unsigned int *ht64_call_hpte_remove; | |
579 | extern unsigned int *ht64_call_hpte_updatepp; | |
580 | ||
581 | make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert); | |
582 | make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert); | |
583 | make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove); | |
584 | make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
5b825831 | 585 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
7d0daae4 ME |
586 | |
587 | make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert); | |
588 | make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert); | |
589 | make_bl(htab_call_hpte_remove, ppc_md.hpte_remove); | |
590 | make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
591 | } | |
592 | ||
1da177e4 LT |
593 | void __init htab_initialize(void) |
594 | { | |
337a7128 | 595 | unsigned long table; |
1da177e4 | 596 | unsigned long pteg_count; |
9e88ba4e | 597 | unsigned long prot; |
41d824bf | 598 | unsigned long base = 0, size = 0, limit; |
3c726f8d BH |
599 | int i; |
600 | ||
1da177e4 LT |
601 | DBG(" -> htab_initialize()\n"); |
602 | ||
1189be65 PM |
603 | /* Initialize segment sizes */ |
604 | htab_init_seg_sizes(); | |
605 | ||
3c726f8d BH |
606 | /* Initialize page sizes */ |
607 | htab_init_page_sizes(); | |
608 | ||
1189be65 PM |
609 | if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) { |
610 | mmu_kernel_ssize = MMU_SEGSIZE_1T; | |
611 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
612 | printk(KERN_INFO "Using 1TB segments\n"); | |
613 | } | |
614 | ||
1da177e4 LT |
615 | /* |
616 | * Calculate the required size of the htab. We want the number of | |
617 | * PTEGs to equal one half the number of real pages. | |
618 | */ | |
3c726f8d | 619 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
620 | pteg_count = htab_size_bytes >> 7; |
621 | ||
1da177e4 LT |
622 | htab_hash_mask = pteg_count - 1; |
623 | ||
57cfb814 | 624 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1da177e4 LT |
625 | /* Using a hypervisor which owns the htab */ |
626 | htab_address = NULL; | |
627 | _SDR1 = 0; | |
628 | } else { | |
629 | /* Find storage for the HPT. Must be contiguous in | |
41d824bf | 630 | * the absolute address space. On cell we want it to be |
31bf1119 | 631 | * in the first 2 Gig so we can use it for IOMMU hacks. |
1da177e4 | 632 | */ |
41d824bf | 633 | if (machine_is(cell)) |
31bf1119 | 634 | limit = 0x80000000; |
41d824bf ME |
635 | else |
636 | limit = 0; | |
637 | ||
638 | table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit); | |
1da177e4 LT |
639 | |
640 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
641 | htab_size_bytes); | |
642 | ||
1da177e4 LT |
643 | htab_address = abs_to_virt(table); |
644 | ||
645 | /* htab absolute addr + encoded htabsize */ | |
646 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
647 | ||
648 | /* Initialize the HPT with no entries */ | |
649 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 PM |
650 | |
651 | /* Set SDR1 */ | |
652 | mtspr(SPRN_SDR1, _SDR1); | |
1da177e4 LT |
653 | } |
654 | ||
f5ea64dc | 655 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 656 | |
370a908d BH |
657 | #ifdef CONFIG_DEBUG_PAGEALLOC |
658 | linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT; | |
659 | linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count, | |
660 | 1, lmb.rmo_size)); | |
661 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
662 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
663 | ||
1da177e4 LT |
664 | /* On U3 based machines, we need to reserve the DART area and |
665 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
666 | * cacheable later on | |
667 | */ | |
1da177e4 LT |
668 | |
669 | /* create bolted the linear mapping in the hash table */ | |
670 | for (i=0; i < lmb.memory.cnt; i++) { | |
b5666f70 | 671 | base = (unsigned long)__va(lmb.memory.region[i].base); |
1da177e4 LT |
672 | size = lmb.memory.region[i].size; |
673 | ||
bc033b63 | 674 | DBG("creating mapping for region: %lx..%lx (prot: %x)\n", |
9e88ba4e | 675 | base, size, prot); |
1da177e4 LT |
676 | |
677 | #ifdef CONFIG_U3_DART | |
678 | /* Do not map the DART space. Fortunately, it will be aligned | |
3c726f8d BH |
679 | * in such a way that it will not cross two lmb regions and |
680 | * will fit within a single 16Mb page. | |
681 | * The DART space is assumed to be a full 16Mb region even if | |
682 | * we only use 2Mb of that space. We will use more of it later | |
683 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
684 | */ |
685 | DBG("DART base: %lx\n", dart_tablebase); | |
686 | ||
687 | if (dart_tablebase != 0 && dart_tablebase >= base | |
688 | && dart_tablebase < (base + size)) { | |
caf80e57 | 689 | unsigned long dart_table_end = dart_tablebase + 16 * MB; |
1da177e4 | 690 | if (base != dart_tablebase) |
3c726f8d | 691 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
9e88ba4e | 692 | __pa(base), prot, |
1189be65 PM |
693 | mmu_linear_psize, |
694 | mmu_kernel_ssize)); | |
caf80e57 | 695 | if ((base + size) > dart_table_end) |
3c726f8d | 696 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
caf80e57 ME |
697 | base + size, |
698 | __pa(dart_table_end), | |
9e88ba4e | 699 | prot, |
1189be65 PM |
700 | mmu_linear_psize, |
701 | mmu_kernel_ssize)); | |
1da177e4 LT |
702 | continue; |
703 | } | |
704 | #endif /* CONFIG_U3_DART */ | |
caf80e57 | 705 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 706 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
3c726f8d | 707 | } |
1da177e4 LT |
708 | |
709 | /* | |
710 | * If we have a memory_limit and we've allocated TCEs then we need to | |
711 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
712 | * case that the TCEs start below memory_limit. | |
713 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
714 | * for either 4K or 16MB pages. | |
715 | */ | |
716 | if (tce_alloc_start) { | |
b5666f70 ME |
717 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
718 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
719 | |
720 | if (base + size >= tce_alloc_start) | |
721 | tce_alloc_start = base + size + 1; | |
722 | ||
caf80e57 | 723 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 724 | __pa(tce_alloc_start), prot, |
1189be65 | 725 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
726 | } |
727 | ||
7d0daae4 ME |
728 | htab_finish_init(); |
729 | ||
1da177e4 LT |
730 | DBG(" <- htab_initialize()\n"); |
731 | } | |
732 | #undef KB | |
733 | #undef MB | |
1da177e4 | 734 | |
e597cb32 | 735 | void htab_initialize_secondary(void) |
799d6046 | 736 | { |
57cfb814 | 737 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
799d6046 PM |
738 | mtspr(SPRN_SDR1, _SDR1); |
739 | } | |
740 | ||
1da177e4 LT |
741 | /* |
742 | * Called by asm hashtable.S for doing lazy icache flush | |
743 | */ | |
744 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
745 | { | |
746 | struct page *page; | |
747 | ||
76c8e25b BH |
748 | if (!pfn_valid(pte_pfn(pte))) |
749 | return pp; | |
750 | ||
1da177e4 LT |
751 | page = pte_page(pte); |
752 | ||
753 | /* page is dirty */ | |
754 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
755 | if (trap == 0x400) { | |
756 | __flush_dcache_icache(page_address(page)); | |
757 | set_bit(PG_arch_1, &page->flags); | |
758 | } else | |
3c726f8d | 759 | pp |= HPTE_R_N; |
1da177e4 LT |
760 | } |
761 | return pp; | |
762 | } | |
763 | ||
3a8247cc PM |
764 | #ifdef CONFIG_PPC_MM_SLICES |
765 | unsigned int get_paca_psize(unsigned long addr) | |
766 | { | |
767 | unsigned long index, slices; | |
768 | ||
769 | if (addr < SLICE_LOW_TOP) { | |
770 | slices = get_paca()->context.low_slices_psize; | |
771 | index = GET_LOW_SLICE_INDEX(addr); | |
772 | } else { | |
773 | slices = get_paca()->context.high_slices_psize; | |
774 | index = GET_HIGH_SLICE_INDEX(addr); | |
775 | } | |
776 | return (slices >> (index * 4)) & 0xF; | |
777 | } | |
778 | ||
779 | #else | |
780 | unsigned int get_paca_psize(unsigned long addr) | |
781 | { | |
782 | return get_paca()->context.user_psize; | |
783 | } | |
784 | #endif | |
785 | ||
721151d0 PM |
786 | /* |
787 | * Demote a segment to using 4k pages. | |
788 | * For now this makes the whole process use 4k pages. | |
789 | */ | |
721151d0 | 790 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 791 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 792 | { |
3a8247cc | 793 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 794 | return; |
3a8247cc | 795 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
1e57ba8d | 796 | #ifdef CONFIG_SPU_BASE |
721151d0 PM |
797 | spu_flush_all_slbs(mm); |
798 | #endif | |
3a8247cc | 799 | if (get_paca_psize(addr) != MMU_PAGE_4K) { |
fa28237c PM |
800 | get_paca()->context = mm->context; |
801 | slb_flush_and_rebolt(); | |
802 | } | |
721151d0 | 803 | } |
16f1c746 | 804 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 805 | |
fa28237c PM |
806 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
807 | /* | |
808 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
809 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
810 | * | |
811 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
812 | * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access. | |
813 | */ | |
814 | static int subpage_protection(pgd_t *pgdir, unsigned long ea) | |
815 | { | |
816 | struct subpage_prot_table *spt = pgd_subpage_prot(pgdir); | |
817 | u32 spp = 0; | |
818 | u32 **sbpm, *sbpp; | |
819 | ||
820 | if (ea >= spt->maxaddr) | |
821 | return 0; | |
822 | if (ea < 0x100000000) { | |
823 | /* addresses below 4GB use spt->low_prot */ | |
824 | sbpm = spt->low_prot; | |
825 | } else { | |
826 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
827 | if (!sbpm) | |
828 | return 0; | |
829 | } | |
830 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
831 | if (!sbpp) | |
832 | return 0; | |
833 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
834 | ||
835 | /* extract 2-bit bitfield for this 4k subpage */ | |
836 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
837 | ||
838 | /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */ | |
839 | spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0); | |
840 | return spp; | |
841 | } | |
842 | ||
843 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
844 | static inline int subpage_protection(pgd_t *pgdir, unsigned long ea) | |
845 | { | |
846 | return 0; | |
847 | } | |
848 | #endif | |
849 | ||
1da177e4 LT |
850 | /* Result code is: |
851 | * 0 - handled | |
852 | * 1 - normal page fault | |
853 | * -1 - critical hash insertion error | |
fa28237c | 854 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 LT |
855 | */ |
856 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap) | |
857 | { | |
858 | void *pgdir; | |
859 | unsigned long vsid; | |
860 | struct mm_struct *mm; | |
861 | pte_t *ptep; | |
1da177e4 | 862 | cpumask_t tmp; |
3c726f8d | 863 | int rc, user_region = 0, local = 0; |
1189be65 | 864 | int psize, ssize; |
1da177e4 | 865 | |
3c726f8d BH |
866 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
867 | ea, access, trap); | |
1f8d419e | 868 | |
3c726f8d BH |
869 | if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) { |
870 | DBG_LOW(" out of pgtable range !\n"); | |
871 | return 1; | |
872 | } | |
873 | ||
874 | /* Get region & vsid */ | |
1da177e4 LT |
875 | switch (REGION_ID(ea)) { |
876 | case USER_REGION_ID: | |
877 | user_region = 1; | |
878 | mm = current->mm; | |
3c726f8d BH |
879 | if (! mm) { |
880 | DBG_LOW(" user region with no mm !\n"); | |
1da177e4 | 881 | return 1; |
3c726f8d | 882 | } |
16c2d476 | 883 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
884 | ssize = user_segment_size(ea); |
885 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 886 | break; |
1da177e4 | 887 | case VMALLOC_REGION_ID: |
1da177e4 | 888 | mm = &init_mm; |
1189be65 | 889 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
890 | if (ea < VMALLOC_END) |
891 | psize = mmu_vmalloc_psize; | |
892 | else | |
893 | psize = mmu_io_psize; | |
1189be65 | 894 | ssize = mmu_kernel_ssize; |
1da177e4 | 895 | break; |
1da177e4 LT |
896 | default: |
897 | /* Not a valid range | |
898 | * Send the problem up to do_page_fault | |
899 | */ | |
900 | return 1; | |
1da177e4 | 901 | } |
3c726f8d | 902 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 903 | |
3c726f8d | 904 | /* Get pgdir */ |
1da177e4 | 905 | pgdir = mm->pgd; |
1da177e4 LT |
906 | if (pgdir == NULL) |
907 | return 1; | |
908 | ||
3c726f8d | 909 | /* Check CPU locality */ |
1da177e4 LT |
910 | tmp = cpumask_of_cpu(smp_processor_id()); |
911 | if (user_region && cpus_equal(mm->cpu_vm_mask, tmp)) | |
912 | local = 1; | |
913 | ||
d0f13e3c | 914 | #ifdef CONFIG_HUGETLB_PAGE |
3c726f8d | 915 | /* Handle hugepage regions */ |
0d9ea754 | 916 | if (HPAGE_SHIFT && mmu_huge_psizes[psize]) { |
3c726f8d | 917 | DBG_LOW(" -> huge page !\n"); |
cbf52afd | 918 | return hash_huge_page(mm, access, ea, vsid, local, trap); |
3c726f8d | 919 | } |
d0f13e3c | 920 | #endif /* CONFIG_HUGETLB_PAGE */ |
3c726f8d | 921 | |
16c2d476 BH |
922 | #ifndef CONFIG_PPC_64K_PAGES |
923 | /* If we use 4K pages and our psize is not 4K, then we are hitting | |
924 | * a special driver mapping, we need to align the address before | |
925 | * we fetch the PTE | |
926 | */ | |
927 | if (psize != MMU_PAGE_4K) | |
928 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
929 | #endif /* CONFIG_PPC_64K_PAGES */ | |
930 | ||
3c726f8d BH |
931 | /* Get PTE and page size from page tables */ |
932 | ptep = find_linux_pte(pgdir, ea); | |
933 | if (ptep == NULL || !pte_present(*ptep)) { | |
934 | DBG_LOW(" no PTE !\n"); | |
935 | return 1; | |
936 | } | |
937 | ||
938 | #ifndef CONFIG_PPC_64K_PAGES | |
939 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
940 | #else | |
941 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
942 | pte_val(*(ptep + PTRS_PER_PTE))); | |
943 | #endif | |
944 | /* Pre-check access permissions (will be re-checked atomically | |
945 | * in __hash_page_XX but this pre-check is a fast path | |
946 | */ | |
947 | if (access & ~pte_val(*ptep)) { | |
948 | DBG_LOW(" no access !\n"); | |
949 | return 1; | |
1da177e4 LT |
950 | } |
951 | ||
3c726f8d | 952 | /* Do actual hashing */ |
16c2d476 | 953 | #ifdef CONFIG_PPC_64K_PAGES |
721151d0 | 954 | /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */ |
3a8247cc | 955 | if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) { |
721151d0 PM |
956 | demote_segment_4k(mm, ea); |
957 | psize = MMU_PAGE_4K; | |
958 | } | |
959 | ||
16f1c746 BH |
960 | /* If this PTE is non-cacheable and we have restrictions on |
961 | * using non cacheable large pages, then we switch to 4k | |
962 | */ | |
963 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && | |
964 | (pte_val(*ptep) & _PAGE_NO_CACHE)) { | |
965 | if (user_region) { | |
966 | demote_segment_4k(mm, ea); | |
967 | psize = MMU_PAGE_4K; | |
968 | } else if (ea < VMALLOC_END) { | |
969 | /* | |
970 | * some driver did a non-cacheable mapping | |
971 | * in vmalloc space, so switch vmalloc | |
972 | * to 4k pages | |
973 | */ | |
974 | printk(KERN_ALERT "Reducing vmalloc segment " | |
975 | "to 4kB pages because of " | |
976 | "non-cacheable mapping\n"); | |
977 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
1e57ba8d | 978 | #ifdef CONFIG_SPU_BASE |
94b2a439 BH |
979 | spu_flush_all_slbs(mm); |
980 | #endif | |
bf72aeba | 981 | } |
16f1c746 BH |
982 | } |
983 | if (user_region) { | |
3a8247cc | 984 | if (psize != get_paca_psize(ea)) { |
f6ab0b92 | 985 | get_paca()->context = mm->context; |
bf72aeba PM |
986 | slb_flush_and_rebolt(); |
987 | } | |
16f1c746 BH |
988 | } else if (get_paca()->vmalloc_sllp != |
989 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
990 | get_paca()->vmalloc_sllp = | |
991 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
67439b76 | 992 | slb_vmalloc_update(); |
bf72aeba | 993 | } |
16c2d476 | 994 | #endif /* CONFIG_PPC_64K_PAGES */ |
16f1c746 | 995 | |
16c2d476 | 996 | #ifdef CONFIG_PPC_HAS_HASH_64K |
bf72aeba | 997 | if (psize == MMU_PAGE_64K) |
1189be65 | 998 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
3c726f8d | 999 | else |
16c2d476 | 1000 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
fa28237c PM |
1001 | { |
1002 | int spp = subpage_protection(pgdir, ea); | |
1003 | if (access & spp) | |
1004 | rc = -2; | |
1005 | else | |
1006 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
1007 | local, ssize, spp); | |
1008 | } | |
3c726f8d BH |
1009 | |
1010 | #ifndef CONFIG_PPC_64K_PAGES | |
1011 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1012 | #else | |
1013 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1014 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1015 | #endif | |
1016 | DBG_LOW(" -> rc=%d\n", rc); | |
1017 | return rc; | |
1da177e4 | 1018 | } |
67207b96 | 1019 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1020 | |
3c726f8d BH |
1021 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1022 | unsigned long access, unsigned long trap) | |
1da177e4 | 1023 | { |
3c726f8d BH |
1024 | unsigned long vsid; |
1025 | void *pgdir; | |
1026 | pte_t *ptep; | |
1027 | cpumask_t mask; | |
1028 | unsigned long flags; | |
1029 | int local = 0; | |
1189be65 | 1030 | int ssize; |
3c726f8d | 1031 | |
d0f13e3c BH |
1032 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1033 | ||
1034 | #ifdef CONFIG_PPC_MM_SLICES | |
1035 | /* We only prefault standard pages for now */ | |
2b02d139 | 1036 | if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize)) |
3c726f8d | 1037 | return; |
d0f13e3c | 1038 | #endif |
3c726f8d BH |
1039 | |
1040 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1041 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1042 | |
16f1c746 | 1043 | /* Get Linux PTE if available */ |
3c726f8d BH |
1044 | pgdir = mm->pgd; |
1045 | if (pgdir == NULL) | |
1046 | return; | |
1047 | ptep = find_linux_pte(pgdir, ea); | |
1048 | if (!ptep) | |
1049 | return; | |
16f1c746 BH |
1050 | |
1051 | #ifdef CONFIG_PPC_64K_PAGES | |
1052 | /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on | |
1053 | * a 64K kernel), then we don't preload, hash_page() will take | |
1054 | * care of it once we actually try to access the page. | |
1055 | * That way we don't have to duplicate all of the logic for segment | |
1056 | * page size demotion here | |
1057 | */ | |
1058 | if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE)) | |
1059 | return; | |
1060 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1061 | ||
1062 | /* Get VSID */ | |
1189be65 PM |
1063 | ssize = user_segment_size(ea); |
1064 | vsid = get_vsid(mm->context.id, ea, ssize); | |
3c726f8d | 1065 | |
16c2d476 | 1066 | /* Hash doesn't like irqs */ |
3c726f8d | 1067 | local_irq_save(flags); |
16c2d476 BH |
1068 | |
1069 | /* Is that local to this CPU ? */ | |
3c726f8d BH |
1070 | mask = cpumask_of_cpu(smp_processor_id()); |
1071 | if (cpus_equal(mm->cpu_vm_mask, mask)) | |
1072 | local = 1; | |
16c2d476 BH |
1073 | |
1074 | /* Hash it in */ | |
1075 | #ifdef CONFIG_PPC_HAS_HASH_64K | |
bf72aeba | 1076 | if (mm->context.user_psize == MMU_PAGE_64K) |
1189be65 | 1077 | __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
1da177e4 | 1078 | else |
5b825831 | 1079 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
fa28237c PM |
1080 | __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize, |
1081 | subpage_protection(pgdir, ea)); | |
16c2d476 | 1082 | |
3c726f8d BH |
1083 | local_irq_restore(flags); |
1084 | } | |
1085 | ||
f6ab0b92 BH |
1086 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1087 | * do not forget to update the assembly call site ! | |
1088 | */ | |
1189be65 PM |
1089 | void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize, |
1090 | int local) | |
3c726f8d BH |
1091 | { |
1092 | unsigned long hash, index, shift, hidx, slot; | |
1093 | ||
1094 | DBG_LOW("flush_hash_page(va=%016x)\n", va); | |
1095 | pte_iterate_hashed_subpages(pte, psize, va, index, shift) { | |
1189be65 | 1096 | hash = hpt_hash(va, shift, ssize); |
3c726f8d BH |
1097 | hidx = __rpte_to_hidx(pte, index); |
1098 | if (hidx & _PTEIDX_SECONDARY) | |
1099 | hash = ~hash; | |
1100 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1101 | slot += hidx & _PTEIDX_GROUP_IX; | |
1102 | DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx); | |
1189be65 | 1103 | ppc_md.hpte_invalidate(slot, va, psize, ssize, local); |
3c726f8d | 1104 | } pte_iterate_hashed_end(); |
1da177e4 LT |
1105 | } |
1106 | ||
61b1a942 | 1107 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1108 | { |
3c726f8d | 1109 | if (ppc_md.flush_hash_range) |
61b1a942 | 1110 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 1111 | else { |
1da177e4 | 1112 | int i; |
61b1a942 BH |
1113 | struct ppc64_tlb_batch *batch = |
1114 | &__get_cpu_var(ppc64_tlb_batch); | |
1da177e4 LT |
1115 | |
1116 | for (i = 0; i < number; i++) | |
3c726f8d | 1117 | flush_hash_page(batch->vaddr[i], batch->pte[i], |
1189be65 | 1118 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1119 | } |
1120 | } | |
1121 | ||
1da177e4 LT |
1122 | /* |
1123 | * low_hash_fault is called when we the low level hash code failed | |
1124 | * to instert a PTE due to an hypervisor error | |
1125 | */ | |
fa28237c | 1126 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 LT |
1127 | { |
1128 | if (user_mode(regs)) { | |
fa28237c PM |
1129 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1130 | if (rc == -2) | |
1131 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1132 | else | |
1133 | #endif | |
1134 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1135 | } else | |
1136 | bad_page_fault(regs, address, SIGBUS); | |
1da177e4 | 1137 | } |
370a908d BH |
1138 | |
1139 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
1140 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1141 | { | |
1189be65 PM |
1142 | unsigned long hash, hpteg; |
1143 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
1144 | unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize); | |
bc033b63 | 1145 | unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL); |
370a908d BH |
1146 | int ret; |
1147 | ||
1189be65 | 1148 | hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1149 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
1150 | ||
1151 | ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr), | |
1189be65 PM |
1152 | mode, HPTE_V_BOLTED, |
1153 | mmu_linear_psize, mmu_kernel_ssize); | |
370a908d BH |
1154 | BUG_ON (ret < 0); |
1155 | spin_lock(&linear_map_hash_lock); | |
1156 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1157 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1158 | spin_unlock(&linear_map_hash_lock); | |
1159 | } | |
1160 | ||
1161 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1162 | { | |
1189be65 PM |
1163 | unsigned long hash, hidx, slot; |
1164 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
1165 | unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize); | |
370a908d | 1166 | |
1189be65 | 1167 | hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1168 | spin_lock(&linear_map_hash_lock); |
1169 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1170 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1171 | linear_map_hash_slots[lmi] = 0; | |
1172 | spin_unlock(&linear_map_hash_lock); | |
1173 | if (hidx & _PTEIDX_SECONDARY) | |
1174 | hash = ~hash; | |
1175 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1176 | slot += hidx & _PTEIDX_GROUP_IX; | |
1189be65 | 1177 | ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0); |
370a908d BH |
1178 | } |
1179 | ||
1180 | void kernel_map_pages(struct page *page, int numpages, int enable) | |
1181 | { | |
1182 | unsigned long flags, vaddr, lmi; | |
1183 | int i; | |
1184 | ||
1185 | local_irq_save(flags); | |
1186 | for (i = 0; i < numpages; i++, page++) { | |
1187 | vaddr = (unsigned long)page_address(page); | |
1188 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1189 | if (lmi >= linear_map_hash_count) | |
1190 | continue; | |
1191 | if (enable) | |
1192 | kernel_map_linear_page(vaddr, lmi); | |
1193 | else | |
1194 | kernel_unmap_linear_page(vaddr, lmi); | |
1195 | } | |
1196 | local_irq_restore(flags); | |
1197 | } | |
1198 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |